2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
75 compatible = "arm,psci-1.0";
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 clocks = <&cru ARMCLKL>;
116 operating-points-v2 = <&cluster0_opp>;
121 compatible = "arm,cortex-a53", "arm,armv8";
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 operating-points-v2 = <&cluster0_opp>;
130 compatible = "arm,cortex-a53", "arm,armv8";
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster0_opp>;
148 compatible = "arm,cortex-a72", "arm,armv8";
150 enable-method = "psci";
151 #cooling-cells = <2>; /* min followed by max */
152 clocks = <&cru ARMCLKB>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a72", "arm,armv8";
160 enable-method = "psci";
161 clocks = <&cru ARMCLKB>;
162 operating-points-v2 = <&cluster1_opp>;
166 cluster0_opp: opp_table0 {
167 compatible = "operating-points-v2";
171 opp-hz = /bits/ 64 <408000000>;
172 opp-microvolt = <1000000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <600000000>;
177 opp-microvolt = <1000000>;
180 opp-hz = /bits/ 64 <816000000>;
181 opp-microvolt = <1000000>;
184 opp-hz = /bits/ 64 <1008000000>;
185 opp-microvolt = <1000000>;
189 cluster1_opp: opp_table1 {
190 compatible = "operating-points-v2";
194 opp-hz = /bits/ 64 <408000000>;
195 opp-microvolt = <1000000>;
196 clock-latency-ns = <40000>;
199 opp-hz = /bits/ 64 <600000000>;
200 opp-microvolt = <1000000>;
203 opp-hz = /bits/ 64 <816000000>;
204 opp-microvolt = <1000000>;
207 opp-hz = /bits/ 64 <1008000000>;
208 opp-microvolt = <1000000>;
211 opp-hz = /bits/ 64 <1200000000>;
212 opp-microvolt = <1000000>;
217 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
219 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
220 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
221 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
225 compatible = "arm,cortex-a53-pmu";
226 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
227 interrupt-affinity = <&cpu_l0>,
234 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
235 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
236 interrupt-affinity = <&cpu_b0>,
241 compatible = "fixed-clock";
243 clock-frequency = <24000000>;
244 clock-output-names = "xin24m";
248 compatible = "arm,amba-bus";
249 #address-cells = <2>;
253 dmac_bus: dma-controller@ff6d0000 {
254 compatible = "arm,pl330", "arm,primecell";
255 reg = <0x0 0xff6d0000 0x0 0x4000>;
256 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&cru ACLK_DMAC0_PERILP>;
260 clock-names = "apb_pclk";
263 dmac_peri: dma-controller@ff6e0000 {
264 compatible = "arm,pl330", "arm,primecell";
265 reg = <0x0 0xff6e0000 0x0 0x4000>;
266 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cru ACLK_DMAC1_PERILP>;
270 clock-names = "apb_pclk";
275 compatible = "rockchip,rk3399-emmc-phy";
276 reg-offset = <0xf780>;
278 rockchip,grf = <&grf>;
282 sdio0: dwmmc@fe310000 {
283 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
284 reg = <0x0 0xfe310000 0x0 0x4000>;
285 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
286 clock-freq-min-max = <400000 150000000>;
287 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
288 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
289 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
290 fifo-depth = <0x100>;
294 sdmmc: dwmmc@fe320000 {
295 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
296 reg = <0x0 0xfe320000 0x0 0x4000>;
297 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
298 clock-freq-min-max = <400000 150000000>;
299 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
300 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
302 fifo-depth = <0x100>;
306 sdhci: sdhci@fe330000 {
307 compatible = "arasan,sdhci-5.1";
308 reg = <0x0 0xfe330000 0x0 0x10000>;
309 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
311 clock-names = "clk_xin", "clk_ahb";
313 phy-names = "phy_arasan";
317 usb_host0_echi: usb@fe380000 {
318 compatible = "generic-ehci";
319 reg = <0x0 0xfe380000 0x0 0x20000>;
320 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&cru HCLK_HOST0>;
322 clock-names = "hclk_host0";
326 usb_host0_ohci: usb@fe3a0000 {
327 compatible = "generic-ohci";
328 reg = <0x0 0xfe3a0000 0x0 0x20000>;
329 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&cru HCLK_HOST0>;
331 clock-names = "hclk_host0";
335 usb_host1_echi: usb@fe3c0000 {
336 compatible = "generic-ehci";
337 reg = <0x0 0xfe3c0000 0x0 0x20000>;
338 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&cru HCLK_HOST1>;
340 clock-names = "hclk_host1";
344 usb_host1_ohci: usb@fe3e0000 {
345 compatible = "generic-ohci";
346 reg = <0x0 0xfe3e0000 0x0 0x20000>;
347 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru HCLK_HOST1>;
349 clock-names = "hclk_host1";
353 gic: interrupt-controller@fee00000 {
354 compatible = "arm,gic-v3";
355 #interrupt-cells = <3>;
356 #address-cells = <2>;
359 interrupt-controller;
361 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
362 <0x0 0xfef00000 0 0xc0000>, /* GICR */
363 <0x0 0xfff00000 0 0x10000>, /* GICC */
364 <0x0 0xfff10000 0 0x10000>, /* GICH */
365 <0x0 0xfff20000 0 0x10000>; /* GICV */
366 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
367 its: interrupt-controller@fee20000 {
368 compatible = "arm,gic-v3-its";
370 reg = <0x0 0xfee20000 0x0 0x20000>;
374 saradc: saradc@ff100000 {
375 compatible = "rockchip,rk3399-saradc";
376 reg = <0x0 0xff100000 0x0 0x100>;
377 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
378 #io-channel-cells = <1>;
379 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
380 clock-names = "saradc", "apb_pclk";
385 compatible = "rockchip,rk3399-i2c";
386 reg = <0x0 0xff3c0000 0x0 0x1000>;
387 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
388 clock-names = "i2c", "pclk";
389 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&i2c0_xfer>;
392 #address-cells = <1>;
398 compatible = "rockchip,rk3399-i2c";
399 reg = <0x0 0xff110000 0x0 0x1000>;
400 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
401 clock-names = "i2c", "pclk";
402 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&i2c1_xfer>;
405 #address-cells = <1>;
411 compatible = "rockchip,rk3399-i2c";
412 reg = <0x0 0xff120000 0x0 0x1000>;
413 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
414 clock-names = "i2c", "pclk";
415 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&i2c2_xfer>;
418 #address-cells = <1>;
424 compatible = "rockchip,rk3399-i2c";
425 reg = <0x0 0xff130000 0x0 0x1000>;
426 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
427 clock-names = "i2c", "pclk";
428 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&i2c3_xfer>;
431 #address-cells = <1>;
437 compatible = "rockchip,rk3399-i2c";
438 reg = <0x0 0xff140000 0x0 0x1000>;
439 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
440 clock-names = "i2c", "pclk";
441 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&i2c5_xfer>;
444 #address-cells = <1>;
450 compatible = "rockchip,rk3399-i2c";
451 reg = <0x0 0xff150000 0x0 0x1000>;
452 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
453 clock-names = "i2c", "pclk";
454 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&i2c6_xfer>;
457 #address-cells = <1>;
463 compatible = "rockchip,rk3399-i2c";
464 reg = <0x0 0xff160000 0x0 0x1000>;
465 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
466 clock-names = "i2c", "pclk";
467 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&i2c7_xfer>;
470 #address-cells = <1>;
475 uart0: serial@ff180000 {
476 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
477 reg = <0x0 0xff180000 0x0 0x100>;
478 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
479 clock-names = "baudclk", "apb_pclk";
480 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
488 uart1: serial@ff190000 {
489 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
490 reg = <0x0 0xff190000 0x0 0x100>;
491 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
492 clock-names = "baudclk", "apb_pclk";
493 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&uart1_xfer>;
501 uart2: serial@ff1a0000 {
502 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
503 reg = <0x0 0xff1a0000 0x0 0x100>;
504 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
505 clock-names = "baudclk", "apb_pclk";
506 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&uart2c_xfer>;
514 uart3: serial@ff1b0000 {
515 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
516 reg = <0x0 0xff1b0000 0x0 0x100>;
517 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
518 clock-names = "baudclk", "apb_pclk";
519 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
528 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
529 reg = <0x0 0xff1c0000 0x0 0x1000>;
530 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
531 clock-names = "spiclk", "apb_pclk";
532 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
535 #address-cells = <1>;
541 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
542 reg = <0x0 0xff1d0000 0x0 0x1000>;
543 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
544 clock-names = "spiclk", "apb_pclk";
545 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
548 #address-cells = <1>;
554 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
555 reg = <0x0 0xff1e0000 0x0 0x1000>;
556 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
557 clock-names = "spiclk", "apb_pclk";
558 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
561 #address-cells = <1>;
567 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
568 reg = <0x0 0xff1f0000 0x0 0x1000>;
569 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
570 clock-names = "spiclk", "apb_pclk";
571 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
574 #address-cells = <1>;
580 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
581 reg = <0x0 0xff200000 0x0 0x1000>;
582 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
583 clock-names = "spiclk", "apb_pclk";
584 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
587 #address-cells = <1>;
593 #include "rk3368-thermal.dtsi"
596 tsadc: tsadc@ff260000 {
597 compatible = "rockchip,rk3399-tsadc";
598 reg = <0x0 0xff260000 0x0 0x100>;
599 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
601 clock-names = "tsadc", "apb_pclk";
602 resets = <&cru SRST_TSADC>;
603 reset-names = "tsadc-apb";
604 pinctrl-names = "init", "default", "sleep";
605 pinctrl-0 = <&otp_gpio>;
606 pinctrl-1 = <&otp_out>;
607 pinctrl-2 = <&otp_gpio>;
608 #thermal-sensor-cells = <1>;
609 rockchip,hw-tshut-temp = <95000>;
613 pmu: power-management@ff31000 {
614 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
615 reg = <0x0 0xff310000 0x0 0x1000>;
617 power: power-controller {
619 compatible = "rockchip,rk3399-power-controller";
620 #power-domain-cells = <1>;
621 #address-cells = <1>;
625 reg = <RK3399_PD_CENTER>;
626 #address-cells = <1>;
630 reg = <RK3399_PD_VDU>;
633 reg = <RK3399_PD_VCODEC>;
636 reg = <RK3399_PD_IEP>;
639 reg = <RK3399_PD_RGA>;
643 reg = <RK3399_PD_VIO>;
644 #address-cells = <1>;
648 reg = <RK3399_PD_ISP0>;
651 reg = <RK3399_PD_ISP1>;
654 reg = <RK3399_PD_HDCP>;
657 reg = <RK3399_PD_VO>;
658 #address-cells = <1>;
662 reg = <RK3399_PD_VOPB>;
665 reg = <RK3399_PD_VOPL>;
670 reg = <RK3399_PD_GPU>;
675 pmugrf: syscon@ff320000 {
676 compatible = "rockchip,rk3399-pmugrf", "syscon";
677 reg = <0x0 0xff320000 0x0 0x1000>;
681 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
682 reg = <0x0 0xff350000 0x0 0x1000>;
683 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
684 clock-names = "spiclk", "apb_pclk";
685 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
688 #address-cells = <1>;
693 uart4: serial@ff370000 {
694 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
695 reg = <0x0 0xff370000 0x0 0x100>;
696 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
697 clock-names = "baudclk", "apb_pclk";
698 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
701 pinctrl-names = "default";
702 pinctrl-0 = <&uart4_xfer>;
707 compatible = "rockchip,rk3399-i2c";
708 reg = <0x0 0xff3d0000 0x0 0x1000>;
709 clocks = <&cru SCLK_I2C4_PMU>, <&cru PCLK_I2C4_PMU>;
710 clock-names = "i2c", "pclk";
711 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
712 pinctrl-names = "default";
713 pinctrl-0 = <&i2c4_xfer>;
714 #address-cells = <1>;
720 compatible = "rockchip,rk3399-i2c";
721 reg = <0x0 0xff3e0000 0x0 0x1000>;
722 clocks = <&cru SCLK_I2C8_PMU>, <&cru PCLK_I2C8_PMU>;
723 clock-names = "i2c", "pclk";
724 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
725 pinctrl-names = "default";
726 pinctrl-0 = <&i2c8_xfer>;
727 #address-cells = <1>;
733 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
734 reg = <0x0 0xff420000 0x0 0x10>;
736 pinctrl-names = "default";
737 pinctrl-0 = <&pwm0_pin>;
738 clocks = <&cru PCLK_RKPWM_PMU>;
744 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
745 reg = <0x0 0xff420010 0x0 0x10>;
747 pinctrl-names = "default";
748 pinctrl-0 = <&pwm1_pin>;
749 clocks = <&cru PCLK_RKPWM_PMU>;
755 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
756 reg = <0x0 0xff420020 0x0 0x10>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&pwm2_pin>;
760 clocks = <&cru PCLK_RKPWM_PMU>;
766 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
767 reg = <0x0 0xff420030 0x0 0x10>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&pwm3a_pin>;
771 clocks = <&cru PCLK_RKPWM_PMU>;
776 pmucru: pmu-clock-controller@ff750000 {
777 compatible = "rockchip,rk3399-pmucru";
778 reg = <0x0 0xff750000 0x0 0x1000>;
779 rockchip,grf = <&pmugrf>;
782 assigned-clocks = <&cru PLL_PPLL>;
783 assigned-clock-rates = <676000000>;
786 cru: clock-controller@ff760000 {
787 compatible = "rockchip,rk3399-cru";
788 reg = <0x0 0xff760000 0x0 0x1000>;
789 rockchip,grf = <&grf>;
793 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
795 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
797 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
799 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
800 assigned-clock-rates =
801 <594000000>, <800000000>,
803 <150000000>, <75000000>,
805 <100000000>, <100000000>,
807 <100000000>, <50000000>;
810 grf: syscon@ff770000 {
811 compatible = "rockchip,rk3399-grf", "syscon";
812 reg = <0x0 0xff770000 0x0 0x10000>;
815 wdt0: watchdog@ff840000 {
816 compatible = "snps,dw-wdt";
817 reg = <0x0 0xff840000 0x0 0x100>;
818 clocks = <&cru PCLK_WDT>;
819 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
823 spdif: spdif@ff870000 {
824 compatible = "rockchip,rk3399-spdif";
825 reg = <0x0 0xff870000 0x0 0x1000>;
826 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
827 dmas = <&dmac_bus 7>;
829 clock-names = "hclk", "mclk";
830 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
831 pinctrl-names = "default";
832 pinctrl-0 = <&spdif_bus>;
837 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
838 reg = <0x0 0xff880000 0x0 0x1000>;
839 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
840 #address-cells = <1>;
842 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
843 dma-names = "tx", "rx";
844 clock-names = "i2s_hclk", "i2s_clk";
845 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
846 pinctrl-names = "default";
847 pinctrl-0 = <&i2s0_8ch_bus>;
852 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
853 reg = <0x0 0xff890000 0x0 0x1000>;
854 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells = <1>;
857 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
858 dma-names = "tx", "rx";
859 clock-names = "i2s_hclk", "i2s_clk";
860 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
861 pinctrl-names = "default";
862 pinctrl-0 = <&i2s1_2ch_bus>;
867 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
868 reg = <0x0 0xff8a0000 0x0 0x1000>;
869 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
870 #address-cells = <1>;
872 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
873 dma-names = "tx", "rx";
874 clock-names = "i2s_hclk", "i2s_clk";
875 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
880 compatible = "rockchip,rk3399-pinctrl";
881 rockchip,grf = <&grf>;
882 rockchip,pmu = <&pmugrf>;
883 #address-cells = <0x2>;
887 gpio0: gpio0@ff720000 {
888 compatible = "rockchip,gpio-bank";
889 reg = <0x0 0xff720000 0x0 0x100>;
890 clocks = <&cru PCLK_GPIO0_PMU>;
891 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
896 interrupt-controller;
897 #interrupt-cells = <0x2>;
900 gpio1: gpio1@ff730000 {
901 compatible = "rockchip,gpio-bank";
902 reg = <0x0 0xff730000 0x0 0x100>;
903 clocks = <&cru PCLK_GPIO1_PMU>;
904 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
909 interrupt-controller;
910 #interrupt-cells = <0x2>;
913 gpio2: gpio2@ff780000 {
914 compatible = "rockchip,gpio-bank";
915 reg = <0x0 0xff780000 0x0 0x100>;
916 clocks = <&cru PCLK_GPIO2>;
917 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
922 interrupt-controller;
923 #interrupt-cells = <0x2>;
926 gpio3: gpio3@ff788000 {
927 compatible = "rockchip,gpio-bank";
928 reg = <0x0 0xff788000 0x0 0x100>;
929 clocks = <&cru PCLK_GPIO3>;
930 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
935 interrupt-controller;
936 #interrupt-cells = <0x2>;
939 gpio4: gpio4@ff790000 {
940 compatible = "rockchip,gpio-bank";
941 reg = <0x0 0xff790000 0x0 0x100>;
942 clocks = <&cru PCLK_GPIO4>;
943 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
948 interrupt-controller;
949 #interrupt-cells = <0x2>;
952 pcfg_pull_up: pcfg-pull-up {
956 pcfg_pull_down: pcfg-pull-down {
960 pcfg_pull_none: pcfg-pull-none {
964 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
966 drive-strength = <12>;
969 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
971 drive-strength = <8>;
974 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
976 drive-strength = <4>;
979 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
981 drive-strength = <2>;
984 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
986 drive-strength = <12>;
992 <0 5 RK_FUNC_1 &pcfg_pull_up>;
997 rgmii_pins: rgmii-pins {
999 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1000 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1001 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1002 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1003 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1004 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
1005 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1006 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1007 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1008 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1009 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1010 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1011 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1012 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1013 <3 9 RK_FUNC_1 &pcfg_pull_none>;
1016 rmii_pins: rmii-pins {
1018 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1019 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1020 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1021 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1022 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1023 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1024 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1025 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1026 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1027 <3 10 RK_FUNC_1 &pcfg_pull_none>;
1032 i2c0_xfer: i2c0-xfer {
1034 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1035 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1040 i2c1_xfer: i2c1-xfer {
1042 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1043 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1048 i2c2_xfer: i2c2-xfer {
1050 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1051 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1056 i2c3_xfer: i2c3-xfer {
1058 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1059 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1064 i2c4_xfer: i2c4-xfer {
1066 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1067 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1072 i2c5_xfer: i2c5-xfer {
1074 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1075 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1080 i2c6_xfer: i2c6-xfer {
1082 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1083 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1088 i2c7_xfer: i2c7-xfer {
1090 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1091 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1096 i2c8_xfer: i2c8-xfer {
1098 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1099 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1104 i2s0_8ch_bus: i2s0-8ch-bus {
1106 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1107 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1108 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1109 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1110 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1111 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1112 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1113 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1114 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1119 i2s1_2ch_bus: i2s1-2ch-bus {
1121 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1122 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1123 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1124 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1125 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1130 sdio0_bus1: sdio0-bus1 {
1132 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1135 sdio0_bus4: sdio0-bus4 {
1137 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1138 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1139 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1140 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1143 sdio0_cmd: sdio0-cmd {
1145 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1148 sdio0_clk: sdio0-clk {
1150 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1153 sdio0_cd: sdio0-cd {
1155 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1158 sdio0_pwr: sdio0-pwr {
1160 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1163 sdio0_bkpwr: sdio0-bkpwr {
1165 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1168 sdio0_wp: sdio0-wp {
1170 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1173 sdio0_int: sdio0-int {
1175 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1180 sdmmc_bus1: sdmmc-bus1 {
1182 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1185 sdmmc_bus4: sdmmc-bus4 {
1187 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1188 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1189 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1190 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1193 sdmmc_clk: sdmmc-clk {
1195 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1198 sdmmc_cmd: sdmmc-cmd {
1200 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1203 sdmmc_cd: sdmcc-cd {
1205 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1208 sdmmc_wp: sdmmc-wp {
1210 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1215 spdif_bus: spdif-bus {
1217 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1222 spi0_clk: spi0-clk {
1224 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1226 spi0_cs0: spi0-cs0 {
1228 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1230 spi0_cs1: spi0-cs1 {
1232 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1236 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1240 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1245 spi1_clk: spi1-clk {
1247 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1249 spi1_cs0: spi1-cs0 {
1251 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1255 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1259 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1264 spi2_clk: spi2-clk {
1266 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1268 spi2_cs0: spi2-cs0 {
1270 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1274 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1278 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1283 spi3_clk: spi3-clk {
1285 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1287 spi3_cs0: spi3-cs0 {
1289 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1293 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1297 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1302 spi4_clk: spi4-clk {
1304 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1306 spi4_cs0: spi4-cs0 {
1308 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1312 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1316 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1321 spi5_clk: spi5-clk {
1323 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1325 spi5_cs0: spi5-cs0 {
1327 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1331 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1335 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1340 otp_gpio: otp-gpio {
1341 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1345 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1350 uart0_xfer: uart0-xfer {
1352 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1353 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1356 uart0_cts: uart0-cts {
1358 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1361 uart0_rts: uart0-rts {
1363 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1368 uart1_xfer: uart1-xfer {
1370 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1371 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1376 uart2a_xfer: uart2a-xfer {
1378 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1379 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1384 uart2b_xfer: uart2b-xfer {
1386 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1387 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1392 uart2c_xfer: uart2c-xfer {
1394 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1395 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1400 uart3_xfer: uart3-xfer {
1402 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1403 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1406 uart3_cts: uart3-cts {
1408 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1411 uart3_rts: uart3-rts {
1413 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1418 uart4_xfer: uart4-xfer {
1420 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1421 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1426 uarthdcp_xfer: uarthdcp-xfer {
1428 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1429 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1434 pwm0_pin: pwm0-pin {
1436 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1439 vop0_pwm_pin: vop0-pwm-pin {
1441 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1446 pwm1_pin: pwm1-pin {
1448 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1451 vop1_pwm_pin: vop1-pwm-pin {
1453 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1458 pwm2_pin: pwm2-pin {
1460 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1465 pwm3a_pin: pwm3a-pin {
1467 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1472 pwm3b_pin: pwm3b-pin {
1474 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1479 pmic_int_l: pmic-int-l {
1481 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;