2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/clock/rk3399-cru.h>
43 #include <dt-bindings/gpio/gpio.h>
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/pinctrl/rockchip.h>
47 #include <dt-bindings/thermal/thermal.h>
50 compatible = "rockchip,rk3399";
51 interrupt-parent = <&gic>;
94 compatible = "arm,cortex-a53", "arm,armv8";
97 #cooling-cells = <2>; /* min followed by max */
102 compatible = "arm,cortex-a53", "arm,armv8";
108 compatible = "arm,cortex-a53", "arm,armv8";
114 compatible = "arm,cortex-a53", "arm,armv8";
120 compatible = "arm,cortex-a72", "arm,armv8";
123 #cooling-cells = <2>; /* min followed by max */
128 compatible = "arm,cortex-a72", "arm,armv8";
134 compatible = "arm,armv8-timer";
135 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
142 compatible = "fixed-clock";
144 clock-frequency = <24000000>;
145 clock-output-names = "xin24m";
148 gic: interrupt-controller@fee00000 {
149 compatible = "arm,gic-v3";
150 #interrupt-cells = <3>;
151 #address-cells = <2>;
154 interrupt-controller;
156 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
157 <0x0 0xfef00000 0 0xc0000>, /* GICR */
158 <0x0 0xfff00000 0 0x10000>, /* GICC */
159 <0x0 0xfff10000 0 0x10000>, /* GICH */
160 <0x0 0xfff20000 0 0x10000>; /* GICV */
161 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
162 its: interrupt-controller@fee20000 {
163 compatible = "arm,gic-v3-its";
165 reg = <0x0 0xfee20000 0x0 0x20000>;
170 compatible = "arm,amba-bus";
171 #address-cells = <2>;
175 dmac_bus: dma-controller@ff6d0000 {
176 compatible = "arm,pl330", "arm,primecell";
177 reg = <0x0 0xff6d0000 0x0 0x4000>;
178 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&cru ACLK_DMAC0_PERILP>;
182 clock-names = "apb_pclk";
185 dmac_peri: dma-controller@ff6e0000 {
186 compatible = "arm,pl330", "arm,primecell";
187 reg = <0x0 0xff6e0000 0x0 0x4000>;
188 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&cru ACLK_DMAC1_PERILP>;
192 clock-names = "apb_pclk";
196 uart0: serial@ff180000 {
197 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
198 reg = <0x0 0xff180000 0x0 0x100>;
199 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
200 clock-names = "baudclk", "apb_pclk";
201 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
207 uart1: serial@ff190000 {
208 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
209 reg = <0x0 0xff190000 0x0 0x100>;
210 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
211 clock-names = "baudclk", "apb_pclk";
212 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
218 uart2: serial@ff1a0000 {
219 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
220 reg = <0x0 0xff1a0000 0x0 0x100>;
221 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
222 clock-names = "baudclk", "apb_pclk";
223 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
229 uart3: serial@ff1b0000 {
230 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
231 reg = <0x0 0xff1b0000 0x0 0x100>;
232 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
233 clock-names = "baudclk", "apb_pclk";
234 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
241 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
242 reg = <0x0 0xff110000 0x0 0x1000>;
243 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
244 clock-names = "spiclk", "apb_pclk";
245 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
248 #address-cells = <1>;
254 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
255 reg = <0x0 0xff120000 0x0 0x1000>;
256 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
257 clock-names = "spiclk", "apb_pclk";
258 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
261 #address-cells = <1>;
267 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
268 reg = <0x0 0xff130000 0x0 0x1000>;
269 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
270 clock-names = "spiclk", "apb_pclk";
271 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
274 #address-cells = <1>;
280 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
281 reg = <0x0 0xff120000 0x0 0x1000>;
282 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
283 clock-names = "spiclk", "apb_pclk";
284 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
287 #address-cells = <1>;
293 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
294 reg = <0x0 0xff130000 0x0 0x1000>;
295 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
296 clock-names = "spiclk", "apb_pclk";
297 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
300 #address-cells = <1>;
306 #include "rk3368-thermal.dtsi"
309 tsadc: tsadc@ff260000 {
310 compatible = "rockchip,rk3399-tsadc";
311 reg = <0x0 0xff260000 0x0 0x100>;
312 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
314 clock-names = "tsadc", "apb_pclk";
315 resets = <&cru SRST_TSADC>;
316 reset-names = "tsadc-apb";
317 pinctrl-names = "init", "default", "sleep";
318 pinctrl-0 = <&otp_gpio>;
319 pinctrl-1 = <&otp_out>;
320 pinctrl-2 = <&otp_gpio>;
321 #thermal-sensor-cells = <1>;
322 rockchip,hw-tshut-temp = <95000>;
326 pmugrf: syscon@ff320000 {
327 compatible = "rockchip,rk3399-pmugrf", "syscon";
328 reg = <0x0 0xff320000 0x0 0x1000>;
332 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
333 reg = <0x0 0xff110000 0x0 0x1000>;
334 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
335 clock-names = "spiclk", "apb_pclk";
336 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
339 #address-cells = <1>;
344 uart4: serial@ff370000 {
345 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
346 reg = <0x0 0xff370000 0x0 0x100>;
347 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
348 clock-names = "baudclk", "apb_pclk";
349 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
355 pmucru: pmu-clock-controller@ff750000 {
356 compatible = "rockchip,rk3399-pmucru";
357 reg = <0x0 0xff750000 0x0 0x1000>;
358 rockchip,grf = <&pmugrf>;
363 cru: clock-controller@ff760000 {
364 compatible = "rockchip,rk3399-cru";
365 reg = <0x0 0xff760000 0x0 0x1000>;
366 rockchip,grf = <&grf>;
371 grf: syscon@ff770000 {
372 compatible = "rockchip,rk3399-grf", "syscon";
373 reg = <0x0 0xff770000 0x0 0x10000>;
376 spdif: spdif@ff870000 {
377 compatible = "rockchip,rk3399-spdif";
378 reg = <0x0 0xff870000 0x0 0x1000>;
379 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
380 dmas = <&dmac_bus 7>;
382 clock-names = "hclk", "mclk";
383 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&spdif_bus>;
390 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
391 reg = <0x0 0xff880000 0x0 0x1000>;
392 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
393 #address-cells = <1>;
395 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
396 dma-names = "tx", "rx";
397 clock-names = "i2s_hclk", "i2s_clk";
398 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2s0_8ch_bus>;
405 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
406 reg = <0x0 0xff890000 0x0 0x1000>;
407 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
408 #address-cells = <1>;
410 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
411 dma-names = "tx", "rx";
412 clock-names = "i2s_hclk", "i2s_clk";
413 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&i2s1_2ch_bus>;
420 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
421 reg = <0x0 0xff8a0000 0x0 0x1000>;
422 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
423 #address-cells = <1>;
425 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
426 dma-names = "tx", "rx";
427 clock-names = "i2s_hclk", "i2s_clk";
428 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
433 compatible = "rockchip,rk3399-pinctrl";
434 rockchip,grf = <&grf>;
435 rockchip,pmu = <&pmugrf>;
436 #address-cells = <0x2>;
440 gpio0: gpio0@ff720000 {
441 compatible = "rockchip,gpio-bank";
442 reg = <0x0 0xff720000 0x0 0x100>;
444 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
449 interrupt-controller;
450 #interrupt-cells = <0x2>;
453 gpio1: gpio1@ff730000 {
454 compatible = "rockchip,gpio-bank";
455 reg = <0x0 0xff730000 0x0 0x100>;
457 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-controller;
463 #interrupt-cells = <0x2>;
466 gpio2: gpio2@ff780000 {
467 compatible = "rockchip,gpio-bank";
468 reg = <0x0 0xff780000 0x0 0x100>;
470 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
475 interrupt-controller;
476 #interrupt-cells = <0x2>;
479 gpio3: gpio3@ff788000 {
480 compatible = "rockchip,gpio-bank";
481 reg = <0x0 0xff788000 0x0 0x100>;
483 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
488 interrupt-controller;
489 #interrupt-cells = <0x2>;
492 gpio4: gpio4@ff790000 {
493 compatible = "rockchip,gpio-bank";
494 reg = <0x0 0xff790000 0x0 0x100>;
496 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
501 interrupt-controller;
502 #interrupt-cells = <0x2>;
505 pcfg_pull_up: pcfg-pull-up {
509 pcfg_pull_down: pcfg-pull-down {
513 pcfg_pull_none: pcfg-pull-none {
517 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
519 drive-strength = <12>;
522 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
524 drive-strength = <8>;
527 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
529 drive-strength = <4>;
532 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
534 drive-strength = <2>;
537 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
539 drive-strength = <12>;
545 <0 5 RK_FUNC_1 &pcfg_pull_up>;
550 rgmii_pins: rgmii-pins {
552 <3 11 RK_FUNC_1 &pcfg_pull_none>,
553 <3 13 RK_FUNC_1 &pcfg_pull_none>,
554 <3 8 RK_FUNC_1 &pcfg_pull_none>,
555 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
556 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
557 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
558 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
559 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
560 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
561 <3 6 RK_FUNC_1 &pcfg_pull_none>,
562 <3 7 RK_FUNC_1 &pcfg_pull_none>,
563 <3 2 RK_FUNC_1 &pcfg_pull_none>,
564 <3 3 RK_FUNC_1 &pcfg_pull_none>,
565 <3 14 RK_FUNC_1 &pcfg_pull_none>,
566 <3 9 RK_FUNC_1 &pcfg_pull_none>;
569 rmii_pins: rmii-pins {
571 <3 11 RK_FUNC_1 &pcfg_pull_none>,
572 <3 13 RK_FUNC_1 &pcfg_pull_none>,
573 <3 8 RK_FUNC_1 &pcfg_pull_none>,
574 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
575 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
576 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
577 <3 6 RK_FUNC_1 &pcfg_pull_none>,
578 <3 7 RK_FUNC_1 &pcfg_pull_none>,
579 <3 9 RK_FUNC_1 &pcfg_pull_none>,
580 <3 10 RK_FUNC_1 &pcfg_pull_none>;
585 i2c0_xfer: i2c0-xfer {
587 <1 15 RK_FUNC_2 &pcfg_pull_none>,
588 <1 16 RK_FUNC_2 &pcfg_pull_none>;
593 i2c1_xfer: i2c1-xfer {
595 <4 2 RK_FUNC_1 &pcfg_pull_none>,
596 <4 1 RK_FUNC_1 &pcfg_pull_none>;
601 i2c2_xfer: i2c2-xfer {
603 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
604 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
609 i2c3_xfer: i2c3-xfer {
611 <4 17 RK_FUNC_1 &pcfg_pull_none>,
612 <4 16 RK_FUNC_1 &pcfg_pull_none>;
617 i2c4_xfer: i2c4-xfer {
619 <1 12 RK_FUNC_1 &pcfg_pull_none>,
620 <1 11 RK_FUNC_1 &pcfg_pull_none>;
625 i2c5_xfer: i2c5-xfer {
627 <3 11 RK_FUNC_2 &pcfg_pull_none>,
628 <3 10 RK_FUNC_2 &pcfg_pull_none>;
633 i2c6_xfer: i2c6-xfer {
635 <2 10 RK_FUNC_2 &pcfg_pull_none>,
636 <2 9 RK_FUNC_2 &pcfg_pull_none>;
641 i2c7_xfer: i2c7-xfer {
643 <2 8 RK_FUNC_2 &pcfg_pull_none>,
644 <2 7 RK_FUNC_2 &pcfg_pull_none>;
649 i2c8_xfer: i2c8-xfer {
651 <1 21 RK_FUNC_1 &pcfg_pull_none>,
652 <1 20 RK_FUNC_1 &pcfg_pull_none>;
657 i2s0_8ch_bus: i2s0-8ch-bus {
659 <3 24 RK_FUNC_1 &pcfg_pull_none>,
660 <3 25 RK_FUNC_1 &pcfg_pull_none>,
661 <3 26 RK_FUNC_1 &pcfg_pull_none>,
662 <3 27 RK_FUNC_1 &pcfg_pull_none>,
663 <3 28 RK_FUNC_1 &pcfg_pull_none>,
664 <3 29 RK_FUNC_1 &pcfg_pull_none>,
665 <3 30 RK_FUNC_1 &pcfg_pull_none>,
666 <3 31 RK_FUNC_1 &pcfg_pull_none>,
667 <4 0 RK_FUNC_1 &pcfg_pull_none>;
672 i2s1_2ch_bus: i2s1-2ch-bus {
674 <4 3 RK_FUNC_1 &pcfg_pull_none>,
675 <4 4 RK_FUNC_1 &pcfg_pull_none>,
676 <4 5 RK_FUNC_1 &pcfg_pull_none>,
677 <4 6 RK_FUNC_1 &pcfg_pull_none>,
678 <4 7 RK_FUNC_1 &pcfg_pull_none>;
683 sdio0_bus1: sdio0-bus1 {
685 <2 20 RK_FUNC_1 &pcfg_pull_up>;
688 sdio0_bus4: sdio0-bus4 {
690 <2 20 RK_FUNC_1 &pcfg_pull_up>,
691 <2 21 RK_FUNC_1 &pcfg_pull_up>,
692 <2 22 RK_FUNC_1 &pcfg_pull_up>,
693 <2 23 RK_FUNC_1 &pcfg_pull_up>;
696 sdio0_cmd: sdio0-cmd {
698 <2 24 RK_FUNC_1 &pcfg_pull_up>;
701 sdio0_clk: sdio0-clk {
703 <2 25 RK_FUNC_1 &pcfg_pull_none>;
708 <2 26 RK_FUNC_1 &pcfg_pull_up>;
711 sdio0_pwr: sdio0-pwr {
713 <2 27 RK_FUNC_1 &pcfg_pull_up>;
716 sdio0_bkpwr: sdio0-bkpwr {
718 <2 28 RK_FUNC_1 &pcfg_pull_up>;
723 <0 3 RK_FUNC_1 &pcfg_pull_up>;
726 sdio0_int: sdio0-int {
728 <0 4 RK_FUNC_1 &pcfg_pull_up>;
733 sdmmc_bus1: sdmmc-bus1 {
735 <4 8 RK_FUNC_1 &pcfg_pull_up>;
738 sdmmc_bus4: sdmmc-bus4 {
740 <4 8 RK_FUNC_1 &pcfg_pull_up>,
741 <4 9 RK_FUNC_1 &pcfg_pull_up>,
742 <4 10 RK_FUNC_1 &pcfg_pull_up>,
743 <4 11 RK_FUNC_1 &pcfg_pull_up>;
746 sdmmc_clk: sdmmc-clk {
748 <4 12 RK_FUNC_1 &pcfg_pull_none>;
751 sdmmc_cmd: sdmmc-cmd {
753 <4 13 RK_FUNC_1 &pcfg_pull_up>;
758 <0 7 RK_FUNC_1 &pcfg_pull_up>;
763 <0 8 RK_FUNC_1 &pcfg_pull_up>;
768 spdif_bus: spdif-bus {
770 <4 21 RK_FUNC_1 &pcfg_pull_none>;
777 <3 6 RK_FUNC_2 &pcfg_pull_up>;
781 <3 7 RK_FUNC_2 &pcfg_pull_up>;
785 <3 8 RK_FUNC_2 &pcfg_pull_up>;
789 <3 5 RK_FUNC_2 &pcfg_pull_up>;
793 <3 4 RK_FUNC_2 &pcfg_pull_up>;
800 <1 9 RK_FUNC_2 &pcfg_pull_up>;
804 <1 10 RK_FUNC_2 &pcfg_pull_up>;
808 <1 7 RK_FUNC_2 &pcfg_pull_up>;
812 <1 8 RK_FUNC_2 &pcfg_pull_up>;
819 <2 11 RK_FUNC_1 &pcfg_pull_up>;
823 <2 12 RK_FUNC_1 &pcfg_pull_up>;
827 <2 9 RK_FUNC_1 &pcfg_pull_up>;
831 <2 10 RK_FUNC_1 &pcfg_pull_up>;
838 <1 17 RK_FUNC_1 &pcfg_pull_up>;
842 <1 18 RK_FUNC_1 &pcfg_pull_up>;
846 <1 15 RK_FUNC_1 &pcfg_pull_up>;
850 <1 16 RK_FUNC_1 &pcfg_pull_up>;
857 <3 2 RK_FUNC_2 &pcfg_pull_up>;
861 <3 3 RK_FUNC_2 &pcfg_pull_up>;
865 <3 0 RK_FUNC_2 &pcfg_pull_up>;
869 <3 1 RK_FUNC_2 &pcfg_pull_up>;
876 <2 22 RK_FUNC_2 &pcfg_pull_up>;
880 <2 23 RK_FUNC_2 &pcfg_pull_up>;
884 <2 20 RK_FUNC_2 &pcfg_pull_up>;
888 <2 21 RK_FUNC_2 &pcfg_pull_up>;
894 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
898 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
903 uart0_xfer: uart0-xfer {
905 <2 16 RK_FUNC_1 &pcfg_pull_up>,
906 <2 17 RK_FUNC_1 &pcfg_pull_none>;
909 uart0_cts: uart0-cts {
911 <2 18 RK_FUNC_1 &pcfg_pull_none>;
914 uart0_rts: uart0-rts {
916 <2 19 RK_FUNC_1 &pcfg_pull_none>;
921 uart1_xfer: uart1-xfer {
923 <3 12 RK_FUNC_2 &pcfg_pull_up>,
924 <3 13 RK_FUNC_2 &pcfg_pull_none>;
929 uart2a_xfer: uart2a-xfer {
931 <4 8 RK_FUNC_2 &pcfg_pull_up>,
932 <4 9 RK_FUNC_2 &pcfg_pull_none>;
937 uart2b_xfer: uart2b-xfer {
939 <4 16 RK_FUNC_2 &pcfg_pull_up>,
940 <4 17 RK_FUNC_2 &pcfg_pull_none>;
945 uart2c_xfer: uart2c-xfer {
947 <4 19 RK_FUNC_1 &pcfg_pull_up>,
948 <4 20 RK_FUNC_1 &pcfg_pull_none>;
953 uart3_xfer: uart3-xfer {
955 <3 14 RK_FUNC_2 &pcfg_pull_up>,
956 <3 15 RK_FUNC_2 &pcfg_pull_none>;
959 uart3_cts: uart3-cts {
961 <3 18 RK_FUNC_2 &pcfg_pull_none>;
964 uart3_rts: uart3-rts {
966 <3 19 RK_FUNC_2 &pcfg_pull_none>;
971 uart4_xfer: uart4-xfer {
973 <1 7 RK_FUNC_1 &pcfg_pull_up>,
974 <1 8 RK_FUNC_1 &pcfg_pull_none>;
979 uarthdcp_xfer: uarthdcp-xfer {
981 <4 21 RK_FUNC_2 &pcfg_pull_up>,
982 <4 22 RK_FUNC_2 &pcfg_pull_none>;
989 <4 18 RK_FUNC_1 &pcfg_pull_none>;
992 vop0_pwm_pin: vop0-pwm-pin {
994 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1001 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1004 vop1_pwm_pin: vop1-pwm-pin {
1006 <4 18 RK_FUNC_3 &pcfg_pull_none>;