2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
105 compatible = "arm,cortex-a53", "arm,armv8";
108 #cooling-cells = <2>; /* min followed by max */
109 clocks = <&cru ARMCLKL>;
110 operating-points-v2 = <&cluster0_opp>;
115 compatible = "arm,cortex-a53", "arm,armv8";
117 clocks = <&cru ARMCLKL>;
118 operating-points-v2 = <&cluster0_opp>;
123 compatible = "arm,cortex-a53", "arm,armv8";
125 clocks = <&cru ARMCLKL>;
126 operating-points-v2 = <&cluster0_opp>;
131 compatible = "arm,cortex-a53", "arm,armv8";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
139 compatible = "arm,cortex-a72", "arm,armv8";
142 #cooling-cells = <2>; /* min followed by max */
143 clocks = <&cru ARMCLKB>;
144 operating-points-v2 = <&cluster1_opp>;
149 compatible = "arm,cortex-a72", "arm,armv8";
151 clocks = <&cru ARMCLKB>;
152 operating-points-v2 = <&cluster1_opp>;
156 cluster0_opp: opp_table0 {
157 compatible = "operating-points-v2";
161 opp-hz = /bits/ 64 <408000000>;
162 opp-microvolt = <1000000>;
163 clock-latency-ns = <40000>;
166 opp-hz = /bits/ 64 <600000000>;
167 opp-microvolt = <1000000>;
170 opp-hz = /bits/ 64 <816000000>;
171 opp-microvolt = <1000000>;
174 opp-hz = /bits/ 64 <1008000000>;
175 opp-microvolt = <1000000>;
179 cluster1_opp: opp_table1 {
180 compatible = "operating-points-v2";
184 opp-hz = /bits/ 64 <408000000>;
185 opp-microvolt = <1000000>;
186 clock-latency-ns = <40000>;
189 opp-hz = /bits/ 64 <600000000>;
190 opp-microvolt = <1000000>;
193 opp-hz = /bits/ 64 <816000000>;
194 opp-microvolt = <1000000>;
197 opp-hz = /bits/ 64 <1008000000>;
198 opp-microvolt = <1000000>;
201 opp-hz = /bits/ 64 <1200000000>;
202 opp-microvolt = <1000000>;
207 compatible = "arm,armv8-timer";
208 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
215 compatible = "fixed-clock";
217 clock-frequency = <24000000>;
218 clock-output-names = "xin24m";
222 compatible = "arm,amba-bus";
223 #address-cells = <2>;
227 dmac_bus: dma-controller@ff6d0000 {
228 compatible = "arm,pl330", "arm,primecell";
229 reg = <0x0 0xff6d0000 0x0 0x4000>;
230 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&cru ACLK_DMAC0_PERILP>;
234 clock-names = "apb_pclk";
237 dmac_peri: dma-controller@ff6e0000 {
238 compatible = "arm,pl330", "arm,primecell";
239 reg = <0x0 0xff6e0000 0x0 0x4000>;
240 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&cru ACLK_DMAC1_PERILP>;
244 clock-names = "apb_pclk";
249 compatible = "rockchip,rk3399-emmc-phy";
250 reg-offset = <0xf780>;
252 rockchip,grf = <&grf>;
256 sdio0: dwmmc@fe310000 {
257 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
258 reg = <0x0 0xfe310000 0x0 0x4000>;
259 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
260 clock-freq-min-max = <400000 150000000>;
261 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
262 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
263 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
264 fifo-depth = <0x100>;
268 sdmmc: dwmmc@fe320000 {
269 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
270 reg = <0x0 0xfe320000 0x0 0x4000>;
271 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
272 clock-freq-min-max = <400000 150000000>;
273 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
274 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
275 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
276 fifo-depth = <0x100>;
280 sdhci: sdhci@fe330000 {
281 compatible = "arasan,sdhci-5.1";
282 reg = <0x0 0xfe330000 0x0 0x10000>;
283 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
285 clock-names = "clk_xin", "clk_ahb";
287 phy-names = "phy_arasan";
291 usb_host0_echi: usb@fe380000 {
292 compatible = "generic-ehci";
293 reg = <0x0 0xfe380000 0x0 0x20000>;
294 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&cru HCLK_HOST0>;
296 clock-names = "hclk_host0";
300 usb_host0_ohci: usb@fe3a0000 {
301 compatible = "generic-ohci";
302 reg = <0x0 0xfe3a0000 0x0 0x20000>;
303 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cru HCLK_HOST0>;
305 clock-names = "hclk_host0";
309 usb_host1_echi: usb@fe3c0000 {
310 compatible = "generic-ehci";
311 reg = <0x0 0xfe3c0000 0x0 0x20000>;
312 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&cru HCLK_HOST1>;
314 clock-names = "hclk_host1";
318 usb_host1_ohci: usb@fe3e0000 {
319 compatible = "generic-ohci";
320 reg = <0x0 0xfe3e0000 0x0 0x20000>;
321 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&cru HCLK_HOST1>;
323 clock-names = "hclk_host1";
327 gic: interrupt-controller@fee00000 {
328 compatible = "arm,gic-v3";
329 #interrupt-cells = <3>;
330 #address-cells = <2>;
333 interrupt-controller;
335 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
336 <0x0 0xfef00000 0 0xc0000>, /* GICR */
337 <0x0 0xfff00000 0 0x10000>, /* GICC */
338 <0x0 0xfff10000 0 0x10000>, /* GICH */
339 <0x0 0xfff20000 0 0x10000>; /* GICV */
340 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
341 its: interrupt-controller@fee20000 {
342 compatible = "arm,gic-v3-its";
344 reg = <0x0 0xfee20000 0x0 0x20000>;
348 saradc: saradc@ff100000 {
349 compatible = "rockchip,rk3399-saradc";
350 reg = <0x0 0xff100000 0x0 0x100>;
351 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
352 #io-channel-cells = <1>;
353 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
354 clock-names = "saradc", "apb_pclk";
359 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
360 reg = <0x0 0xff3c0000 0x0 0x1000>;
361 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
362 clock-names = "i2c", "i2c_sclk";
363 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&i2c0_xfer>;
366 #address-cells = <1>;
372 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
373 reg = <0x0 0xff110000 0x0 0x1000>;
374 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
375 clock-names = "i2c", "i2c_sclk";
376 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c1_xfer>;
379 #address-cells = <1>;
385 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
386 reg = <0x0 0xff120000 0x0 0x1000>;
387 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
388 clock-names = "i2c", "i2c_sclk";
389 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&i2c2_xfer>;
392 #address-cells = <1>;
398 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
399 reg = <0x0 0xff130000 0x0 0x1000>;
400 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
401 clock-names = "i2c", "i2c_sclk";
402 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&i2c3_xfer>;
405 #address-cells = <1>;
411 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
412 reg = <0x0 0xff140000 0x0 0x1000>;
413 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
414 clock-names = "i2c", "i2c_sclk";
415 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&i2c5_xfer>;
418 #address-cells = <1>;
424 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
425 reg = <0x0 0xff150000 0x0 0x1000>;
426 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
427 clock-names = "i2c", "i2c_sclk";
428 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&i2c6_xfer>;
431 #address-cells = <1>;
437 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
438 reg = <0x0 0xff160000 0x0 0x1000>;
439 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
440 clock-names = "i2c", "i2c_sclk";
441 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&i2c7_xfer>;
444 #address-cells = <1>;
449 uart0: serial@ff180000 {
450 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
451 reg = <0x0 0xff180000 0x0 0x100>;
452 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
453 clock-names = "baudclk", "apb_pclk";
454 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
460 uart1: serial@ff190000 {
461 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
462 reg = <0x0 0xff190000 0x0 0x100>;
463 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
464 clock-names = "baudclk", "apb_pclk";
465 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
471 uart2: serial@ff1a0000 {
472 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
473 reg = <0x0 0xff1a0000 0x0 0x100>;
474 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
475 clock-names = "baudclk", "apb_pclk";
476 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
482 uart3: serial@ff1b0000 {
483 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
484 reg = <0x0 0xff1b0000 0x0 0x100>;
485 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
486 clock-names = "baudclk", "apb_pclk";
487 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
494 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
495 reg = <0x0 0xff1c0000 0x0 0x1000>;
496 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
497 clock-names = "spiclk", "apb_pclk";
498 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
501 #address-cells = <1>;
507 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
508 reg = <0x0 0xff1d0000 0x0 0x1000>;
509 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
510 clock-names = "spiclk", "apb_pclk";
511 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
514 #address-cells = <1>;
520 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
521 reg = <0x0 0xff1e0000 0x0 0x1000>;
522 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
523 clock-names = "spiclk", "apb_pclk";
524 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
527 #address-cells = <1>;
533 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
534 reg = <0x0 0xff1f0000 0x0 0x1000>;
535 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
536 clock-names = "spiclk", "apb_pclk";
537 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
540 #address-cells = <1>;
546 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
547 reg = <0x0 0xff200000 0x0 0x1000>;
548 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
549 clock-names = "spiclk", "apb_pclk";
550 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
553 #address-cells = <1>;
559 #include "rk3368-thermal.dtsi"
562 tsadc: tsadc@ff260000 {
563 compatible = "rockchip,rk3399-tsadc";
564 reg = <0x0 0xff260000 0x0 0x100>;
565 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
567 clock-names = "tsadc", "apb_pclk";
568 resets = <&cru SRST_TSADC>;
569 reset-names = "tsadc-apb";
570 pinctrl-names = "init", "default", "sleep";
571 pinctrl-0 = <&otp_gpio>;
572 pinctrl-1 = <&otp_out>;
573 pinctrl-2 = <&otp_gpio>;
574 #thermal-sensor-cells = <1>;
575 rockchip,hw-tshut-temp = <95000>;
579 pmu: power-management@ff31000 {
580 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
581 reg = <0x0 0xff310000 0x0 0x1000>;
583 power: power-controller {
585 compatible = "rockchip,rk3399-power-controller";
586 #power-domain-cells = <1>;
587 #address-cells = <1>;
591 reg = <RK3399_PD_CENTER>;
592 #address-cells = <1>;
596 reg = <RK3399_PD_VDU>;
599 reg = <RK3399_PD_VCODEC>;
602 reg = <RK3399_PD_IEP>;
605 reg = <RK3399_PD_RGA>;
609 reg = <RK3399_PD_VIO>;
610 #address-cells = <1>;
614 reg = <RK3399_PD_ISP0>;
617 reg = <RK3399_PD_ISP1>;
620 reg = <RK3399_PD_HDCP>;
623 reg = <RK3399_PD_VO>;
624 #address-cells = <1>;
628 reg = <RK3399_PD_VOPB>;
631 reg = <RK3399_PD_VOPL>;
636 reg = <RK3399_PD_GPU>;
641 pmugrf: syscon@ff320000 {
642 compatible = "rockchip,rk3399-pmugrf", "syscon";
643 reg = <0x0 0xff320000 0x0 0x1000>;
647 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
648 reg = <0x0 0xff350000 0x0 0x1000>;
649 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
650 clock-names = "spiclk", "apb_pclk";
651 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
654 #address-cells = <1>;
659 uart4: serial@ff370000 {
660 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
661 reg = <0x0 0xff370000 0x0 0x100>;
662 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
663 clock-names = "baudclk", "apb_pclk";
664 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
671 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
672 reg = <0x0 0xff3d0000 0x0 0x1000>;
673 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
674 clock-names = "i2c", "i2c_sclk";
675 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&i2c4_xfer>;
678 #address-cells = <1>;
684 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
685 reg = <0x0 0xff3e0000 0x0 0x1000>;
686 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
687 clock-names = "i2c", "i2c_sclk";
688 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&i2c8_xfer>;
691 #address-cells = <1>;
697 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
698 reg = <0x0 0xff420000 0x0 0x10>;
700 pinctrl-names = "default";
701 pinctrl-0 = <&pwm0_pin>;
702 clocks = <&cru PCLK_RKPWM_PMU>;
708 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
709 reg = <0x0 0xff420010 0x0 0x10>;
711 pinctrl-names = "default";
712 pinctrl-0 = <&pwm1_pin>;
713 clocks = <&cru PCLK_RKPWM_PMU>;
719 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
720 reg = <0x0 0xff420020 0x0 0x10>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&pwm2_pin>;
724 clocks = <&cru PCLK_RKPWM_PMU>;
730 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
731 reg = <0x0 0xff420030 0x0 0x10>;
733 pinctrl-names = "default";
734 pinctrl-0 = <&pwm3a_pin>;
735 clocks = <&cru PCLK_RKPWM_PMU>;
740 pmucru: pmu-clock-controller@ff750000 {
741 compatible = "rockchip,rk3399-pmucru";
742 reg = <0x0 0xff750000 0x0 0x1000>;
743 rockchip,grf = <&pmugrf>;
748 cru: clock-controller@ff760000 {
749 compatible = "rockchip,rk3399-cru";
750 reg = <0x0 0xff760000 0x0 0x1000>;
751 rockchip,grf = <&grf>;
756 grf: syscon@ff770000 {
757 compatible = "rockchip,rk3399-grf", "syscon";
758 reg = <0x0 0xff770000 0x0 0x10000>;
761 spdif: spdif@ff870000 {
762 compatible = "rockchip,rk3399-spdif";
763 reg = <0x0 0xff870000 0x0 0x1000>;
764 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
765 dmas = <&dmac_bus 7>;
767 clock-names = "hclk", "mclk";
768 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&spdif_bus>;
775 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
776 reg = <0x0 0xff880000 0x0 0x1000>;
777 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
778 #address-cells = <1>;
780 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
781 dma-names = "tx", "rx";
782 clock-names = "i2s_hclk", "i2s_clk";
783 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&i2s0_8ch_bus>;
790 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
791 reg = <0x0 0xff890000 0x0 0x1000>;
792 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
793 #address-cells = <1>;
795 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
796 dma-names = "tx", "rx";
797 clock-names = "i2s_hclk", "i2s_clk";
798 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
799 pinctrl-names = "default";
800 pinctrl-0 = <&i2s1_2ch_bus>;
805 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
806 reg = <0x0 0xff8a0000 0x0 0x1000>;
807 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
808 #address-cells = <1>;
810 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
811 dma-names = "tx", "rx";
812 clock-names = "i2s_hclk", "i2s_clk";
813 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
818 compatible = "rockchip,rk3399-pinctrl";
819 rockchip,grf = <&grf>;
820 rockchip,pmu = <&pmugrf>;
821 #address-cells = <0x2>;
825 gpio0: gpio0@ff720000 {
826 compatible = "rockchip,gpio-bank";
827 reg = <0x0 0xff720000 0x0 0x100>;
829 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
834 interrupt-controller;
835 #interrupt-cells = <0x2>;
838 gpio1: gpio1@ff730000 {
839 compatible = "rockchip,gpio-bank";
840 reg = <0x0 0xff730000 0x0 0x100>;
842 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
847 interrupt-controller;
848 #interrupt-cells = <0x2>;
851 gpio2: gpio2@ff780000 {
852 compatible = "rockchip,gpio-bank";
853 reg = <0x0 0xff780000 0x0 0x100>;
855 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-controller;
861 #interrupt-cells = <0x2>;
864 gpio3: gpio3@ff788000 {
865 compatible = "rockchip,gpio-bank";
866 reg = <0x0 0xff788000 0x0 0x100>;
868 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
873 interrupt-controller;
874 #interrupt-cells = <0x2>;
877 gpio4: gpio4@ff790000 {
878 compatible = "rockchip,gpio-bank";
879 reg = <0x0 0xff790000 0x0 0x100>;
881 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
886 interrupt-controller;
887 #interrupt-cells = <0x2>;
890 pcfg_pull_up: pcfg-pull-up {
894 pcfg_pull_down: pcfg-pull-down {
898 pcfg_pull_none: pcfg-pull-none {
902 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
904 drive-strength = <12>;
907 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
909 drive-strength = <8>;
912 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
914 drive-strength = <4>;
917 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
919 drive-strength = <2>;
922 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
924 drive-strength = <12>;
930 <0 5 RK_FUNC_1 &pcfg_pull_up>;
935 rgmii_pins: rgmii-pins {
937 <3 11 RK_FUNC_1 &pcfg_pull_none>,
938 <3 13 RK_FUNC_1 &pcfg_pull_none>,
939 <3 8 RK_FUNC_1 &pcfg_pull_none>,
940 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
941 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
942 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
943 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
944 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
945 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
946 <3 6 RK_FUNC_1 &pcfg_pull_none>,
947 <3 7 RK_FUNC_1 &pcfg_pull_none>,
948 <3 2 RK_FUNC_1 &pcfg_pull_none>,
949 <3 3 RK_FUNC_1 &pcfg_pull_none>,
950 <3 14 RK_FUNC_1 &pcfg_pull_none>,
951 <3 9 RK_FUNC_1 &pcfg_pull_none>;
954 rmii_pins: rmii-pins {
956 <3 11 RK_FUNC_1 &pcfg_pull_none>,
957 <3 13 RK_FUNC_1 &pcfg_pull_none>,
958 <3 8 RK_FUNC_1 &pcfg_pull_none>,
959 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
960 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
961 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
962 <3 6 RK_FUNC_1 &pcfg_pull_none>,
963 <3 7 RK_FUNC_1 &pcfg_pull_none>,
964 <3 9 RK_FUNC_1 &pcfg_pull_none>,
965 <3 10 RK_FUNC_1 &pcfg_pull_none>;
970 i2c0_xfer: i2c0-xfer {
972 <1 15 RK_FUNC_2 &pcfg_pull_none>,
973 <1 16 RK_FUNC_2 &pcfg_pull_none>;
978 i2c1_xfer: i2c1-xfer {
980 <4 2 RK_FUNC_1 &pcfg_pull_none>,
981 <4 1 RK_FUNC_1 &pcfg_pull_none>;
986 i2c2_xfer: i2c2-xfer {
988 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
989 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
994 i2c3_xfer: i2c3-xfer {
996 <4 17 RK_FUNC_1 &pcfg_pull_none>,
997 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1002 i2c4_xfer: i2c4-xfer {
1004 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1005 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1010 i2c5_xfer: i2c5-xfer {
1012 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1013 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1018 i2c6_xfer: i2c6-xfer {
1020 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1021 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1026 i2c7_xfer: i2c7-xfer {
1028 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1029 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1034 i2c8_xfer: i2c8-xfer {
1036 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1037 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1042 i2s0_8ch_bus: i2s0-8ch-bus {
1044 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1045 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1046 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1047 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1048 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1049 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1050 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1051 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1052 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1057 i2s1_2ch_bus: i2s1-2ch-bus {
1059 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1060 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1061 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1062 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1063 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1068 sdio0_bus1: sdio0-bus1 {
1070 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1073 sdio0_bus4: sdio0-bus4 {
1075 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1076 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1077 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1078 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1081 sdio0_cmd: sdio0-cmd {
1083 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1086 sdio0_clk: sdio0-clk {
1088 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1091 sdio0_cd: sdio0-cd {
1093 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1096 sdio0_pwr: sdio0-pwr {
1098 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1101 sdio0_bkpwr: sdio0-bkpwr {
1103 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1106 sdio0_wp: sdio0-wp {
1108 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1111 sdio0_int: sdio0-int {
1113 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1118 sdmmc_bus1: sdmmc-bus1 {
1120 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1123 sdmmc_bus4: sdmmc-bus4 {
1125 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1126 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1127 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1128 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1131 sdmmc_clk: sdmmc-clk {
1133 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1136 sdmmc_cmd: sdmmc-cmd {
1138 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1141 sdmmc_cd: sdmcc-cd {
1143 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1146 sdmmc_wp: sdmmc-wp {
1148 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1153 spdif_bus: spdif-bus {
1155 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1160 spi0_clk: spi0-clk {
1162 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1164 spi0_cs0: spi0-cs0 {
1166 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1168 spi0_cs1: spi0-cs1 {
1170 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1174 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1178 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1183 spi1_clk: spi1-clk {
1185 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1187 spi1_cs0: spi1-cs0 {
1189 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1193 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1197 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1202 spi2_clk: spi2-clk {
1204 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1206 spi2_cs0: spi2-cs0 {
1208 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1212 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1216 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1221 spi3_clk: spi3-clk {
1223 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1225 spi3_cs0: spi3-cs0 {
1227 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1231 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1235 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1240 spi4_clk: spi4-clk {
1242 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1244 spi4_cs0: spi4-cs0 {
1246 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1250 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1254 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1259 spi5_clk: spi5-clk {
1261 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1263 spi5_cs0: spi5-cs0 {
1265 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1269 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1273 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1278 otp_gpio: otp-gpio {
1279 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1283 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1288 uart0_xfer: uart0-xfer {
1290 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1291 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1294 uart0_cts: uart0-cts {
1296 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1299 uart0_rts: uart0-rts {
1301 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1306 uart1_xfer: uart1-xfer {
1308 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1309 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1314 uart2a_xfer: uart2a-xfer {
1316 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1317 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1322 uart2b_xfer: uart2b-xfer {
1324 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1325 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1330 uart2c_xfer: uart2c-xfer {
1332 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1333 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1338 uart3_xfer: uart3-xfer {
1340 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1341 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1344 uart3_cts: uart3-cts {
1346 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1349 uart3_rts: uart3-rts {
1351 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1356 uart4_xfer: uart4-xfer {
1358 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1359 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1364 uarthdcp_xfer: uarthdcp-xfer {
1366 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1367 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1372 pwm0_pin: pwm0-pin {
1374 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1377 vop0_pwm_pin: vop0-pwm-pin {
1379 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1384 pwm1_pin: pwm1-pin {
1386 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1389 vop1_pwm_pin: vop1-pwm-pin {
1391 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1396 pwm2_pin: pwm2-pin {
1398 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1403 pwm3a_pin: pwm3a-pin {
1405 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1410 pwm3b_pin: pwm3b-pin {
1412 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1417 pmic_int_l: pmic-int-l {
1419 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;