2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3399";
55 interrupt-parent = <&gic>;
77 compatible = "arm,psci-1.0";
113 compatible = "arm,cortex-a53", "arm,armv8";
115 enable-method = "psci";
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <121>;
118 clocks = <&cru ARMCLKL>;
119 cpu-idle-states = <&cpu_sleep>;
120 operating-points-v2 = <&cluster0_opp>;
121 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 cpu-idle-states = <&cpu_sleep>;
131 operating-points-v2 = <&cluster0_opp>;
132 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 enable-method = "psci";
140 clocks = <&cru ARMCLKL>;
141 cpu-idle-states = <&cpu_sleep>;
142 operating-points-v2 = <&cluster0_opp>;
143 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 cpu-idle-states = <&cpu_sleep>;
153 operating-points-v2 = <&cluster0_opp>;
154 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
159 compatible = "arm,cortex-a72", "arm,armv8";
161 enable-method = "psci";
162 #cooling-cells = <2>; /* min followed by max */
163 dynamic-power-coefficient = <1068>;
164 clocks = <&cru ARMCLKB>;
165 cpu-idle-states = <&cpu_sleep>;
166 operating-points-v2 = <&cluster1_opp>;
167 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
172 compatible = "arm,cortex-a72", "arm,armv8";
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 cpu-idle-states = <&cpu_sleep>;
177 operating-points-v2 = <&cluster1_opp>;
178 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
182 entry-method = "psci";
183 cpu_sleep: cpu-sleep-0 {
184 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x0010000>;
187 entry-latency-us = <350>;
188 exit-latency-us = <600>;
189 min-residency-us = <1150>;
193 /include/ "rk3399-sched-energy.dtsi"
197 cluster0_opp: opp_table0 {
198 compatible = "operating-points-v2";
202 opp-hz = /bits/ 64 <408000000>;
203 opp-microvolt = <800000>;
204 clock-latency-ns = <40000>;
207 opp-hz = /bits/ 64 <600000000>;
208 opp-microvolt = <800000>;
211 opp-hz = /bits/ 64 <816000000>;
212 opp-microvolt = <800000>;
215 opp-hz = /bits/ 64 <1008000000>;
216 opp-microvolt = <875000>;
219 opp-hz = /bits/ 64 <1200000000>;
220 opp-microvolt = <925000>;
223 opp-hz = /bits/ 64 <1416000000>;
224 opp-microvolt = <1025000>;
228 cluster1_opp: opp_table1 {
229 compatible = "operating-points-v2";
233 opp-hz = /bits/ 64 <408000000>;
234 opp-microvolt = <800000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <600000000>;
239 opp-microvolt = <800000>;
242 opp-hz = /bits/ 64 <816000000>;
243 opp-microvolt = <800000>;
246 opp-hz = /bits/ 64 <1008000000>;
247 opp-microvolt = <850000>;
250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <925000>;
256 compatible = "arm,armv8-timer";
257 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
258 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
259 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
260 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
264 compatible = "arm,armv8-pmuv3";
265 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
269 compatible = "fixed-clock";
271 clock-frequency = <24000000>;
272 clock-output-names = "xin24m";
276 compatible = "arm,amba-bus";
277 #address-cells = <2>;
281 dmac_bus: dma-controller@ff6d0000 {
282 compatible = "arm,pl330", "arm,primecell";
283 reg = <0x0 0xff6d0000 0x0 0x4000>;
284 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cru ACLK_DMAC0_PERILP>;
288 clock-names = "apb_pclk";
289 peripherals-req-type-burst;
292 dmac_peri: dma-controller@ff6e0000 {
293 compatible = "arm,pl330", "arm,primecell";
294 reg = <0x0 0xff6e0000 0x0 0x4000>;
295 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&cru ACLK_DMAC1_PERILP>;
299 clock-names = "apb_pclk";
300 peripherals-req-type-burst;
305 compatible = "rockchip,rk3399-gmac";
306 reg = <0x0 0xfe300000 0x0 0x10000>;
307 rockchip,grf = <&grf>;
308 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-names = "macirq";
310 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
311 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
312 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
314 clock-names = "stmmaceth", "mac_clk_rx",
315 "mac_clk_tx", "clk_mac_ref",
316 "clk_mac_refout", "aclk_mac",
318 resets = <&cru SRST_A_GMAC>;
319 reset-names = "stmmaceth";
324 compatible = "rockchip,rk3399-emmc-phy";
325 reg-offset = <0xf780>;
327 rockchip,grf = <&grf>;
328 ctrl-base = <0xfe330000>;
332 sdio0: dwmmc@fe310000 {
333 compatible = "rockchip,rk3399-dw-mshc",
334 "rockchip,rk3288-dw-mshc";
335 reg = <0x0 0xfe310000 0x0 0x4000>;
336 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
337 clock-freq-min-max = <400000 150000000>;
338 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
339 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
340 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
341 fifo-depth = <0x100>;
345 sdmmc: dwmmc@fe320000 {
346 compatible = "rockchip,rk3399-dw-mshc",
347 "rockchip,rk3288-dw-mshc";
348 reg = <0x0 0xfe320000 0x0 0x4000>;
349 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
350 clock-freq-min-max = <400000 150000000>;
351 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
352 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
353 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
354 fifo-depth = <0x100>;
358 sdhci: sdhci@fe330000 {
359 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
360 reg = <0x0 0xfe330000 0x0 0x10000>;
361 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
363 clock-names = "clk_xin", "clk_ahb";
364 assigned-clocks = <&cru SCLK_EMMC>;
365 assigned-clock-parents = <&cru PLL_CPLL>;
366 assigned-clock-rates = <200000000>;
368 phy-names = "phy_arasan";
373 compatible = "rockchip,rk3399-usb-phy";
374 rockchip,grf = <&grf>;
375 #address-cells = <1>;
378 usb2phy0: usb2-phy0 {
384 usb2phy1: usb2-phy1 {
391 usb_host0_ehci: usb@fe380000 {
392 compatible = "generic-ehci";
393 reg = <0x0 0xfe380000 0x0 0x20000>;
394 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
396 clock-names = "hclk_host0", "hclk_host0_arb";
398 phy-names = "usb2_phy0";
402 usb_host0_ohci: usb@fe3a0000 {
403 compatible = "generic-ohci";
404 reg = <0x0 0xfe3a0000 0x0 0x20000>;
405 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
407 clock-names = "hclk_host0", "hclk_host0_arb";
411 usb_host1_ehci: usb@fe3c0000 {
412 compatible = "generic-ehci";
413 reg = <0x0 0xfe3c0000 0x0 0x20000>;
414 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
416 clock-names = "hclk_host1", "hclk_host1_arb";
418 phy-names = "usb2_phy1";
422 usb_host1_ohci: usb@fe3e0000 {
423 compatible = "generic-ohci";
424 reg = <0x0 0xfe3e0000 0x0 0x20000>;
425 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
427 clock-names = "hclk_host1", "hclk_host1_arb";
431 usbdrd3_0: usb@fe800000 {
432 compatible = "rockchip,dwc3";
433 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
434 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
435 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
436 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
437 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
438 "aclk_usb3", "aclk_usb3_grf";
439 #address-cells = <2>;
443 usbdrd_dwc3_0: dwc3@fe800000 {
444 compatible = "snps,dwc3";
445 reg = <0x0 0xfe800000 0x0 0x100000>;
446 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
448 snps,dis_enblslpm_quirk;
449 snps,phyif_utmi_16_bits;
450 snps,dis_u2_freeclk_exists_quirk;
451 snps,dis_del_phy_power_chg_quirk;
452 snps,xhci_slow_suspend_quirk;
457 usbdrd3_1: usb@fe900000 {
458 compatible = "rockchip,dwc3";
459 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
460 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
461 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
462 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
463 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
464 "aclk_usb3", "aclk_usb3_grf";
465 #address-cells = <2>;
469 usbdrd_dwc3_1: dwc3@fe900000 {
470 compatible = "snps,dwc3";
471 reg = <0x0 0xfe900000 0x0 0x100000>;
472 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
474 snps,dis_enblslpm_quirk;
475 snps,phyif_utmi_16_bits;
476 snps,dis_u2_freeclk_exists_quirk;
477 snps,dis_del_phy_power_chg_quirk;
478 snps,xhci_slow_suspend_quirk;
483 gic: interrupt-controller@fee00000 {
484 compatible = "arm,gic-v3";
485 #interrupt-cells = <3>;
486 #address-cells = <2>;
489 interrupt-controller;
491 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
492 <0x0 0xfef00000 0 0xc0000>, /* GICR */
493 <0x0 0xfff00000 0 0x10000>, /* GICC */
494 <0x0 0xfff10000 0 0x10000>, /* GICH */
495 <0x0 0xfff20000 0 0x10000>; /* GICV */
496 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
497 its: interrupt-controller@fee20000 {
498 compatible = "arm,gic-v3-its";
500 reg = <0x0 0xfee20000 0x0 0x20000>;
504 saradc: saradc@ff100000 {
505 compatible = "rockchip,rk3399-saradc";
506 reg = <0x0 0xff100000 0x0 0x100>;
507 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
508 #io-channel-cells = <1>;
509 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
510 clock-names = "saradc", "apb_pclk";
515 compatible = "rockchip,rk3399-i2c";
516 reg = <0x0 0xff3c0000 0x0 0x1000>;
517 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
518 clock-names = "i2c", "pclk";
519 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c0_xfer>;
522 #address-cells = <1>;
528 compatible = "rockchip,rk3399-i2c";
529 reg = <0x0 0xff110000 0x0 0x1000>;
530 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
531 clock-names = "i2c", "pclk";
532 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c1_xfer>;
535 #address-cells = <1>;
541 compatible = "rockchip,rk3399-i2c";
542 reg = <0x0 0xff120000 0x0 0x1000>;
543 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
544 clock-names = "i2c", "pclk";
545 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c2_xfer>;
548 #address-cells = <1>;
554 compatible = "rockchip,rk3399-i2c";
555 reg = <0x0 0xff130000 0x0 0x1000>;
556 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
557 clock-names = "i2c", "pclk";
558 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c3_xfer>;
561 #address-cells = <1>;
567 compatible = "rockchip,rk3399-i2c";
568 reg = <0x0 0xff140000 0x0 0x1000>;
569 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
570 clock-names = "i2c", "pclk";
571 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c5_xfer>;
574 #address-cells = <1>;
580 compatible = "rockchip,rk3399-i2c";
581 reg = <0x0 0xff150000 0x0 0x1000>;
582 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
583 clock-names = "i2c", "pclk";
584 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c6_xfer>;
587 #address-cells = <1>;
593 compatible = "rockchip,rk3399-i2c";
594 reg = <0x0 0xff160000 0x0 0x1000>;
595 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
596 clock-names = "i2c", "pclk";
597 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&i2c7_xfer>;
600 #address-cells = <1>;
605 uart0: serial@ff180000 {
606 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
607 reg = <0x0 0xff180000 0x0 0x100>;
608 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
609 clock-names = "baudclk", "apb_pclk";
610 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
618 uart1: serial@ff190000 {
619 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
620 reg = <0x0 0xff190000 0x0 0x100>;
621 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
622 clock-names = "baudclk", "apb_pclk";
623 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&uart1_xfer>;
631 uart2: serial@ff1a0000 {
632 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
633 reg = <0x0 0xff1a0000 0x0 0x100>;
634 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
635 clock-names = "baudclk", "apb_pclk";
636 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&uart2c_xfer>;
644 uart3: serial@ff1b0000 {
645 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
646 reg = <0x0 0xff1b0000 0x0 0x100>;
647 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
648 clock-names = "baudclk", "apb_pclk";
649 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
658 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
659 reg = <0x0 0xff1c0000 0x0 0x1000>;
660 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
661 clock-names = "spiclk", "apb_pclk";
662 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
665 #address-cells = <1>;
671 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
672 reg = <0x0 0xff1d0000 0x0 0x1000>;
673 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
674 clock-names = "spiclk", "apb_pclk";
675 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
678 #address-cells = <1>;
684 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
685 reg = <0x0 0xff1e0000 0x0 0x1000>;
686 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
687 clock-names = "spiclk", "apb_pclk";
688 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
691 #address-cells = <1>;
697 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
698 reg = <0x0 0xff1f0000 0x0 0x1000>;
699 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
700 clock-names = "spiclk", "apb_pclk";
701 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
704 #address-cells = <1>;
710 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
711 reg = <0x0 0xff200000 0x0 0x1000>;
712 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
713 clock-names = "spiclk", "apb_pclk";
714 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
717 #address-cells = <1>;
723 soc_thermal: soc-thermal {
724 polling-delay-passive = <20>; /* milliseconds */
725 polling-delay = <1000>; /* milliseconds */
726 sustainable-power = <1600>; /* milliwatts */
728 thermal-sensors = <&tsadc 0>;
731 threshold: trip-point@0 {
732 temperature = <70000>; /* millicelsius */
733 hysteresis = <2000>; /* millicelsius */
736 target: trip-point@1 {
737 temperature = <85000>; /* millicelsius */
738 hysteresis = <2000>; /* millicelsius */
742 temperature = <95000>; /* millicelsius */
743 hysteresis = <2000>; /* millicelsius */
752 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
753 contribution = <10240>;
758 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
759 contribution = <1024>;
764 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
765 contribution = <10240>;
770 gpu_thermal: gpu-thermal {
771 polling-delay-passive = <100>; /* milliseconds */
772 polling-delay = <1000>; /* milliseconds */
774 thermal-sensors = <&tsadc 1>;
778 tsadc: tsadc@ff260000 {
779 compatible = "rockchip,rk3399-tsadc";
780 reg = <0x0 0xff260000 0x0 0x100>;
781 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
782 rockchip,grf = <&grf>;
783 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
784 clock-names = "tsadc", "apb_pclk";
785 assigned-clocks = <&cru SCLK_TSADC>;
786 assigned-clock-rates = <750000>;
787 resets = <&cru SRST_TSADC>;
788 reset-names = "tsadc-apb";
789 pinctrl-names = "init", "default", "sleep";
790 pinctrl-0 = <&otp_gpio>;
791 pinctrl-1 = <&otp_out>;
792 pinctrl-2 = <&otp_gpio>;
793 #thermal-sensor-cells = <1>;
794 rockchip,hw-tshut-temp = <95000>;
798 qos_gpu: qos_gpu@ffae0000 {
799 compatible = "syscon";
800 reg = <0x0 0xffae0000 0x0 0x20>;
802 qos_video_m0: qos_video_m0@ffab8000 {
803 compatible = "syscon";
804 reg = <0x0 0xffab8000 0x0 0x20>;
806 qos_video_m1_r: qos_video_m1_r@ffac0000 {
807 compatible = "syscon";
808 reg = <0x0 0xffac0000 0x0 0x20>;
810 qos_video_m1_w: qos_video_m1_w@ffac0080 {
811 compatible = "syscon";
812 reg = <0x0 0xffac0080 0x0 0x20>;
814 qos_rga_r: qos_rga_r@ffab0000 {
815 compatible = "syscon";
816 reg = <0x0 0xffab0000 0x0 0x20>;
818 qos_rga_w: qos_rga_w@ffab0080 {
819 compatible = "syscon";
820 reg = <0x0 0xffab0080 0x0 0x20>;
822 qos_iep: qos_iep@ffa98000 {
823 compatible = "syscon";
824 reg = <0x0 0xffa98000 0x0 0x20>;
826 qos_vop_big_r: qos_vop_big_r@ffac8000 {
827 compatible = "syscon";
828 reg = <0x0 0xffac8000 0x0 0x20>;
830 qos_vop_big_w: qos_vop_big_w@ffac8080 {
831 compatible = "syscon";
832 reg = <0x0 0xffac8080 0x0 0x20>;
834 qos_vop_little: qos_vop_little@ffad0000 {
835 compatible = "syscon";
836 reg = <0x0 0xffad0000 0x0 0x20>;
838 qos_isp0_m0: qos_isp0_m0@ffaa0000 {
839 compatible = "syscon";
840 reg = <0x0 0xffaa0000 0x0 0x20>;
842 qos_isp0_m1: qos_isp0_m1@ffaa0080 {
843 compatible = "syscon";
844 reg = <0x0 0xffaa0080 0x0 0x20>;
846 qos_isp1_m0: qos_isp1_m0@ffaa8000 {
847 compatible = "syscon";
848 reg = <0x0 0xffaa8000 0x0 0x20>;
850 qos_isp1_m1: qos_isp1_m1@ffaa8080 {
851 compatible = "syscon";
852 reg = <0x0 0xffaa8080 0x0 0x20>;
854 qos_hdcp: qos_hdcp@ffa90000 {
855 compatible = "syscon";
856 reg = <0x0 0xffa90000 0x0 0x20>;
859 pmu: power-management@ff310000 {
860 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
861 reg = <0x0 0xff310000 0x0 0x1000>;
863 power: power-controller {
865 compatible = "rockchip,rk3399-power-controller";
866 #power-domain-cells = <1>;
867 #address-cells = <1>;
872 reg = <RK3399_PD_VDU>;
873 clocks = <&cru ACLK_VDU>,
875 pm_qos = <&qos_video_m1_r>,
879 reg = <RK3399_PD_VCODEC>;
880 clocks = <&cru ACLK_VCODEC>,
882 pm_qos = <&qos_video_m0>;
885 reg = <RK3399_PD_IEP>;
886 clocks = <&cru ACLK_IEP>,
891 reg = <RK3399_PD_RGA>;
892 clocks = <&cru ACLK_RGA>,
894 pm_qos = <&qos_rga_r>,
898 reg = <RK3399_PD_VIO>;
899 #address-cells = <1>;
903 reg = <RK3399_PD_ISP0>;
904 clocks = <&cru ACLK_ISP0>,
906 pm_qos = <&qos_isp0_m0>,
910 reg = <RK3399_PD_ISP1>;
911 clocks = <&cru ACLK_ISP1>,
913 pm_qos = <&qos_isp1_m0>,
917 reg = <RK3399_PD_HDCP>;
918 clocks = <&cru ACLK_HDCP>,
921 pm_qos = <&qos_hdcp>;
924 reg = <RK3399_PD_VO>;
925 #address-cells = <1>;
929 reg = <RK3399_PD_VOPB>;
930 clocks = <&cru ACLK_VOP0>,
932 pm_qos = <&qos_vop_big_r>,
936 reg = <RK3399_PD_VOPL>;
937 clocks = <&cru ACLK_VOP1>,
939 pm_qos = <&qos_vop_little>;
944 reg = <RK3399_PD_GPU>;
945 clocks = <&cru ACLK_GPU>;
951 pmugrf: syscon@ff320000 {
952 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
953 reg = <0x0 0xff320000 0x0 0x1000>;
956 compatible = "syscon-reboot-mode";
958 mode-normal = <BOOT_NORMAL>;
959 mode-recovery = <BOOT_RECOVERY>;
960 mode-bootloader = <BOOT_FASTBOOT>;
961 mode-loader = <BOOT_LOADER>;
966 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
967 reg = <0x0 0xff350000 0x0 0x1000>;
968 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
969 clock-names = "spiclk", "apb_pclk";
970 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
971 pinctrl-names = "default";
972 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
973 #address-cells = <1>;
978 uart4: serial@ff370000 {
979 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
980 reg = <0x0 0xff370000 0x0 0x100>;
981 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
982 clock-names = "baudclk", "apb_pclk";
983 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
986 pinctrl-names = "default";
987 pinctrl-0 = <&uart4_xfer>;
992 compatible = "rockchip,rk3399-i2c";
993 reg = <0x0 0xff3d0000 0x0 0x1000>;
994 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
995 clock-names = "i2c", "pclk";
996 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
997 pinctrl-names = "default";
998 pinctrl-0 = <&i2c4_xfer>;
999 #address-cells = <1>;
1001 status = "disabled";
1004 i2c8: i2c@ff3e0000 {
1005 compatible = "rockchip,rk3399-i2c";
1006 reg = <0x0 0xff3e0000 0x0 0x1000>;
1007 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1008 clock-names = "i2c", "pclk";
1009 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1010 pinctrl-names = "default";
1011 pinctrl-0 = <&i2c8_xfer>;
1012 #address-cells = <1>;
1014 status = "disabled";
1017 pcie0: pcie@f8000000 {
1018 compatible = "rockchip,rk3399-pcie";
1019 #address-cells = <3>;
1021 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1022 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1023 clock-names = "aclk_pcie", "aclk_perf_pcie",
1024 "hclk_pcie", "clk_pciephy_ref";
1025 bus-range = <0x0 0x1>;
1026 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1029 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1030 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1031 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1032 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1033 < 0x0 0xfd000000 0x0 0x1000000 >;
1034 reg-name = "axi-base", "apb-base";
1035 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1036 <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1037 <&cru SRST_PCIE_PIPE>;
1038 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1039 "mgmt-sticky-rst", "pipe-rst";
1040 rockchip,grf = <&grf>;
1041 pcie-conf = <0xe220>;
1042 pcie-status = <0xe2a4>;
1043 pcie-laneoff = <0xe214>;
1044 msi-parent = <&its>;
1045 #interrupt-cells = <1>;
1046 interrupt-map-mask = <0 0 0 7>;
1047 interrupt-map = <0 0 0 1 &pcie0 1>,
1051 status = "disabled";
1052 pcie_intc: interrupt-controller {
1053 interrupt-controller;
1054 #address-cells = <0>;
1055 #interrupt-cells = <1>;
1059 pwm0: pwm@ff420000 {
1060 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1061 reg = <0x0 0xff420000 0x0 0x10>;
1063 pinctrl-names = "default";
1064 pinctrl-0 = <&pwm0_pin>;
1065 clocks = <&pmucru PCLK_RKPWM_PMU>;
1066 clock-names = "pwm";
1067 status = "disabled";
1070 pwm1: pwm@ff420010 {
1071 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1072 reg = <0x0 0xff420010 0x0 0x10>;
1074 pinctrl-names = "default";
1075 pinctrl-0 = <&pwm1_pin>;
1076 clocks = <&pmucru PCLK_RKPWM_PMU>;
1077 clock-names = "pwm";
1078 status = "disabled";
1081 pwm2: pwm@ff420020 {
1082 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1083 reg = <0x0 0xff420020 0x0 0x10>;
1085 pinctrl-names = "default";
1086 pinctrl-0 = <&pwm2_pin>;
1087 clocks = <&pmucru PCLK_RKPWM_PMU>;
1088 clock-names = "pwm";
1089 status = "disabled";
1092 pwm3: pwm@ff420030 {
1093 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1094 reg = <0x0 0xff420030 0x0 0x10>;
1096 pinctrl-names = "default";
1097 pinctrl-0 = <&pwm3a_pin>;
1098 clocks = <&pmucru PCLK_RKPWM_PMU>;
1099 clock-names = "pwm";
1100 status = "disabled";
1104 compatible = "rockchip,rk3399-rga";
1105 reg = <0x0 0xff680000 0x0 0x10000>;
1106 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1107 interrupt-names = "rga";
1108 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1109 clock-names = "aclk", "hclk", "sclk";
1110 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1111 reset-names = "core", "axi", "ahb";
1112 status = "disabled";
1115 pmucru: pmu-clock-controller@ff750000 {
1116 compatible = "rockchip,rk3399-pmucru";
1117 reg = <0x0 0xff750000 0x0 0x1000>;
1120 assigned-clocks = <&pmucru PLL_PPLL>;
1121 assigned-clock-rates = <676000000>;
1124 cru: clock-controller@ff760000 {
1125 compatible = "rockchip,rk3399-cru";
1126 reg = <0x0 0xff760000 0x0 0x1000>;
1130 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1131 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1132 <&cru ARMCLKL>, <&cru ARMCLKB>,
1133 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1135 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1137 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1138 <&cru PCLK_PERILP0>,
1139 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1140 assigned-clock-rates =
1141 <400000000>, <200000000>,
1142 <400000000>, <200000000>,
1143 <816000000>, <816000000>,
1144 <594000000>, <800000000>,
1146 <150000000>, <75000000>,
1148 <100000000>, <100000000>,
1150 <100000000>, <50000000>;
1153 grf: syscon@ff770000 {
1154 compatible = "rockchip,rk3399-grf", "syscon";
1155 reg = <0x0 0xff770000 0x0 0x10000>;
1159 compatible = "snps,dw-wdt";
1160 reg = <0x0 0xff840000 0x0 0x100>;
1161 clocks = <&cru PCLK_WDT>;
1162 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1165 rktimer: rktimer@ff850000 {
1166 compatible = "rockchip,rk3399-timer";
1167 reg = <0x0 0xff850000 0x0 0x1000>;
1168 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1170 clock-names = "pclk", "timer";
1173 spdif: spdif@ff870000 {
1174 compatible = "rockchip,rk3399-spdif";
1175 reg = <0x0 0xff870000 0x0 0x1000>;
1176 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1177 dmas = <&dmac_bus 7>;
1179 clock-names = "mclk", "hclk";
1180 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1181 pinctrl-names = "default";
1182 pinctrl-0 = <&spdif_bus>;
1183 status = "disabled";
1186 i2s0: i2s@ff880000 {
1187 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1188 reg = <0x0 0xff880000 0x0 0x1000>;
1189 rockchip,grf = <&grf>;
1190 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1191 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1192 dma-names = "tx", "rx";
1193 clock-names = "i2s_clk", "i2s_hclk";
1194 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&i2s0_8ch_bus>;
1197 status = "disabled";
1200 i2s1: i2s@ff890000 {
1201 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1202 reg = <0x0 0xff890000 0x0 0x1000>;
1203 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1204 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1205 dma-names = "tx", "rx";
1206 clock-names = "i2s_clk", "i2s_hclk";
1207 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1208 pinctrl-names = "default";
1209 pinctrl-0 = <&i2s1_2ch_bus>;
1210 status = "disabled";
1213 i2s2: i2s@ff8a0000 {
1214 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1215 reg = <0x0 0xff8a0000 0x0 0x1000>;
1216 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1217 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1218 dma-names = "tx", "rx";
1219 clock-names = "i2s_clk", "i2s_hclk";
1220 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1221 status = "disabled";
1225 compatible = "arm,malit860",
1230 reg = <0x0 0xff9a0000 0x0 0x10000>;
1232 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupt-names = "GPU", "JOB", "MMU";
1237 clocks = <&cru ACLK_GPU>;
1238 clock-names = "clk_mali";
1239 #cooling-cells = <2>; /* min followed by max */
1240 operating-points-v2 = <&gpu_opp_table>;
1241 power-domains = <&power RK3399_PD_GPU>;
1242 power-off-delay-ms = <200>;
1243 status = "disabled";
1246 compatible = "arm,mali-simple-power-model";
1249 static-power = <300>;
1250 dynamic-power = <1780>;
1251 ts = <32000 4700 (-80) 2>;
1252 thermal-zone = "gpu-thermal";
1256 gpu_opp_table: gpu_opp_table {
1257 compatible = "operating-points-v2";
1261 opp-hz = /bits/ 64 <200000000>;
1262 opp-microvolt = <900000>;
1265 opp-hz = /bits/ 64 <300000000>;
1266 opp-microvolt = <900000>;
1269 opp-hz = /bits/ 64 <400000000>;
1270 opp-microvolt = <900000>;
1275 vopl: vop@ff8f0000 {
1276 compatible = "rockchip,rk3399-vop-lit";
1277 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1278 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1280 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1281 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1282 reset-names = "axi", "ahb", "dclk";
1283 power-domains = <&power RK3399_PD_VOPL>;
1284 iommus = <&vopl_mmu>;
1285 status = "disabled";
1288 #address-cells = <1>;
1291 vopl_out_mipi: endpoint@0 {
1293 remote-endpoint = <&mipi_in_vopl>;
1296 vopl_out_edp: endpoint@1 {
1298 remote-endpoint = <&edp_in_vopl>;
1303 vopl_mmu: iommu@ff8f3f00 {
1304 compatible = "rockchip,iommu";
1305 reg = <0x0 0xff8f3f00 0x0 0x100>;
1306 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1307 interrupt-names = "vopl_mmu";
1309 status = "disabled";
1312 vopb: vop@ff900000 {
1313 compatible = "rockchip,rk3399-vop-big";
1314 reg = <0x0 0xff900000 0x0 0x3efc>;
1315 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1316 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1317 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1318 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1319 reset-names = "axi", "ahb", "dclk";
1320 power-domains = <&power RK3399_PD_VOPB>;
1321 iommus = <&vopb_mmu>;
1322 status = "disabled";
1325 #address-cells = <1>;
1328 vopb_out_edp: endpoint@0 {
1330 remote-endpoint = <&edp_in_vopb>;
1333 vopb_out_mipi: endpoint@1 {
1335 remote-endpoint = <&mipi_in_vopb>;
1340 vopb_mmu: iommu@ff903f00 {
1341 compatible = "rockchip,iommu";
1342 reg = <0x0 0xff903f00 0x0 0x100>;
1343 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1344 interrupt-names = "vopb_mmu";
1346 status = "disabled";
1349 mipi_dsi: mipi@ff960000 {
1350 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1351 reg = <0x0 0xff960000 0x0 0x8000>;
1352 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1353 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1354 <&cru SCLK_DPHY_TX0_CFG>;
1355 clock-names = "ref", "pclk", "phy_cfg";
1356 power-domains = <&power RK3399_PD_VIO>;
1357 rockchip,grf = <&grf>;
1358 #address-cells = <1>;
1360 status = "disabled";
1363 #address-cells = <1>;
1368 #address-cells = <1>;
1371 mipi_in_vopb: endpoint@0 {
1373 remote-endpoint = <&vopb_out_mipi>;
1375 mipi_in_vopl: endpoint@1 {
1377 remote-endpoint = <&vopl_out_mipi>;
1384 compatible = "rockchip,rk3399-edp";
1385 reg = <0x0 0xff970000 0x0 0x8000>;
1386 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1387 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1388 clock-names = "dp", "pclk";
1389 resets = <&cru SRST_P_EDP_CTRL>;
1391 rockchip,grf = <&grf>;
1392 status = "disabled";
1393 pinctrl-names = "default";
1394 pinctrl-0 = <&edp_hpd>;
1397 #address-cells = <1>;
1402 #address-cells = <1>;
1405 edp_in_vopb: endpoint@0 {
1407 remote-endpoint = <&vopb_out_edp>;
1410 edp_in_vopl: endpoint@1 {
1412 remote-endpoint = <&vopl_out_edp>;
1418 display_subsystem: display-subsystem {
1419 compatible = "rockchip,display-subsystem";
1420 ports = <&vopl_out>, <&vopb_out>;
1421 status = "disabled";
1425 compatible = "rockchip,rk3399-pinctrl";
1426 rockchip,grf = <&grf>;
1427 rockchip,pmu = <&pmugrf>;
1428 #address-cells = <0x2>;
1429 #size-cells = <0x2>;
1432 gpio0: gpio0@ff720000 {
1433 compatible = "rockchip,gpio-bank";
1434 reg = <0x0 0xff720000 0x0 0x100>;
1435 clocks = <&pmucru PCLK_GPIO0_PMU>;
1436 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1439 #gpio-cells = <0x2>;
1441 interrupt-controller;
1442 #interrupt-cells = <0x2>;
1445 gpio1: gpio1@ff730000 {
1446 compatible = "rockchip,gpio-bank";
1447 reg = <0x0 0xff730000 0x0 0x100>;
1448 clocks = <&pmucru PCLK_GPIO1_PMU>;
1449 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1452 #gpio-cells = <0x2>;
1454 interrupt-controller;
1455 #interrupt-cells = <0x2>;
1458 gpio2: gpio2@ff780000 {
1459 compatible = "rockchip,gpio-bank";
1460 reg = <0x0 0xff780000 0x0 0x100>;
1461 clocks = <&cru PCLK_GPIO2>;
1462 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1465 #gpio-cells = <0x2>;
1467 interrupt-controller;
1468 #interrupt-cells = <0x2>;
1471 gpio3: gpio3@ff788000 {
1472 compatible = "rockchip,gpio-bank";
1473 reg = <0x0 0xff788000 0x0 0x100>;
1474 clocks = <&cru PCLK_GPIO3>;
1475 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1478 #gpio-cells = <0x2>;
1480 interrupt-controller;
1481 #interrupt-cells = <0x2>;
1484 gpio4: gpio4@ff790000 {
1485 compatible = "rockchip,gpio-bank";
1486 reg = <0x0 0xff790000 0x0 0x100>;
1487 clocks = <&cru PCLK_GPIO4>;
1488 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1491 #gpio-cells = <0x2>;
1493 interrupt-controller;
1494 #interrupt-cells = <0x2>;
1497 pcfg_pull_up: pcfg-pull-up {
1501 pcfg_pull_down: pcfg-pull-down {
1505 pcfg_pull_none: pcfg-pull-none {
1509 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1511 drive-strength = <12>;
1514 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1516 drive-strength = <8>;
1519 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1521 drive-strength = <4>;
1524 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1526 drive-strength = <2>;
1529 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1531 drive-strength = <12>;
1534 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1536 drive-strength = <13>;
1540 emmc_pwr: emmc-pwr {
1542 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1547 rgmii_pins: rgmii-pins {
1550 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1552 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1554 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1556 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1558 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1560 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1562 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1564 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1566 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1568 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1570 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1572 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1574 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1576 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1578 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1581 rmii_pins: rmii-pins {
1584 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1586 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1588 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1590 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1592 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1594 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1596 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1598 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1600 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1602 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1607 i2c0_xfer: i2c0-xfer {
1609 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1610 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1615 i2c1_xfer: i2c1-xfer {
1617 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1618 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1623 i2c2_xfer: i2c2-xfer {
1625 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1626 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1631 i2c3_xfer: i2c3-xfer {
1633 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1634 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1637 i2c3_gpio: i2c3_gpio {
1639 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1640 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1646 i2c4_xfer: i2c4-xfer {
1648 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1649 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1654 i2c5_xfer: i2c5-xfer {
1656 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1657 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1662 i2c6_xfer: i2c6-xfer {
1664 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1665 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1670 i2c7_xfer: i2c7-xfer {
1672 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1673 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1678 i2c8_xfer: i2c8-xfer {
1680 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1681 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1686 i2s0_8ch_bus: i2s0-8ch-bus {
1688 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1689 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1690 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1691 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1692 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1693 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1694 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1695 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1696 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1701 i2s1_2ch_bus: i2s1-2ch-bus {
1703 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1704 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1705 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1706 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1707 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1712 sdio0_bus1: sdio0-bus1 {
1714 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1717 sdio0_bus4: sdio0-bus4 {
1719 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1720 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1721 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1722 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1725 sdio0_cmd: sdio0-cmd {
1727 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1730 sdio0_clk: sdio0-clk {
1732 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1735 sdio0_cd: sdio0-cd {
1737 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1740 sdio0_pwr: sdio0-pwr {
1742 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1745 sdio0_bkpwr: sdio0-bkpwr {
1747 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1750 sdio0_wp: sdio0-wp {
1752 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1755 sdio0_int: sdio0-int {
1757 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1762 sdmmc_bus1: sdmmc-bus1 {
1764 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1767 sdmmc_bus4: sdmmc-bus4 {
1769 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1770 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1771 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1772 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1775 sdmmc_clk: sdmmc-clk {
1777 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1780 sdmmc_cmd: sdmmc-cmd {
1782 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1785 sdmmc_cd: sdmcc-cd {
1787 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1790 sdmmc_wp: sdmmc-wp {
1792 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1797 spdif_bus: spdif-bus {
1799 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1802 spdif_bus_1: spdif-bus-1 {
1804 <3 16 RK_FUNC_3 &pcfg_pull_none>;
1809 spi0_clk: spi0-clk {
1811 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1813 spi0_cs0: spi0-cs0 {
1815 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1817 spi0_cs1: spi0-cs1 {
1819 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1823 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1827 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1832 spi1_clk: spi1-clk {
1834 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1836 spi1_cs0: spi1-cs0 {
1838 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1842 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1846 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1851 spi2_clk: spi2-clk {
1853 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1855 spi2_cs0: spi2-cs0 {
1857 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1861 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1865 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1870 spi3_clk: spi3-clk {
1872 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1874 spi3_cs0: spi3-cs0 {
1876 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1880 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1884 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1889 spi4_clk: spi4-clk {
1891 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1893 spi4_cs0: spi4-cs0 {
1895 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1899 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1903 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1908 spi5_clk: spi5-clk {
1910 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1912 spi5_cs0: spi5-cs0 {
1914 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1918 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1922 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1927 otp_gpio: otp-gpio {
1928 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1932 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1937 uart0_xfer: uart0-xfer {
1939 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1940 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1943 uart0_cts: uart0-cts {
1945 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1948 uart0_rts: uart0-rts {
1950 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1955 uart1_xfer: uart1-xfer {
1957 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1958 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1963 uart2a_xfer: uart2a-xfer {
1965 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1966 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1971 uart2b_xfer: uart2b-xfer {
1973 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1974 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1979 uart2c_xfer: uart2c-xfer {
1981 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1982 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1987 uart3_xfer: uart3-xfer {
1989 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1990 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1993 uart3_cts: uart3-cts {
1995 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1998 uart3_rts: uart3-rts {
2000 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2005 uart4_xfer: uart4-xfer {
2007 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2008 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2013 uarthdcp_xfer: uarthdcp-xfer {
2015 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2016 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2021 pwm0_pin: pwm0-pin {
2023 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2026 vop0_pwm_pin: vop0-pwm-pin {
2028 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2033 pwm1_pin: pwm1-pin {
2035 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2038 vop1_pwm_pin: vop1-pwm-pin {
2040 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2045 pwm2_pin: pwm2-pin {
2047 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2052 pwm3a_pin: pwm3a-pin {
2054 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2059 pwm3b_pin: pwm3b-pin {
2061 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2068 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2073 hdmi_i2c_xfer: hdmi-i2c-xfer {
2075 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2076 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2079 hdmi_cec: hdmi-cec {
2081 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2086 pcie_clkreqn: pci-clkreqn {
2088 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2091 pcie_clkreqnb: pci-clkreqnb {
2093 <4 24 RK_FUNC_1 &pcfg_pull_none>;