2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
52 #include "rk3399-dram-default-timing.dtsi"
55 compatible = "rockchip,rk3399";
57 interrupt-parent = <&gic>;
79 compatible = "arm,psci-1.0";
115 compatible = "arm,cortex-a53", "arm,armv8";
117 enable-method = "psci";
118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <100>;
120 clocks = <&cru ARMCLKL>;
121 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
135 compatible = "arm,cortex-a53", "arm,armv8";
137 enable-method = "psci";
138 clocks = <&cru ARMCLKL>;
139 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 compatible = "arm,cortex-a53", "arm,armv8";
146 enable-method = "psci";
147 clocks = <&cru ARMCLKL>;
148 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
153 compatible = "arm,cortex-a72", "arm,armv8";
155 enable-method = "psci";
156 #cooling-cells = <2>; /* min followed by max */
157 dynamic-power-coefficient = <436>;
158 clocks = <&cru ARMCLKB>;
159 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
164 compatible = "arm,cortex-a72", "arm,armv8";
166 enable-method = "psci";
167 clocks = <&cru ARMCLKB>;
168 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
172 entry-method = "psci";
174 CPU_SLEEP: cpu-sleep {
175 compatible = "arm,idle-state";
177 arm,psci-suspend-param = <0x0010000>;
178 entry-latency-us = <120>;
179 exit-latency-us = <250>;
180 min-residency-us = <900>;
183 CLUSTER_SLEEP: cluster-sleep {
184 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x1010000>;
187 entry-latency-us = <400>;
188 exit-latency-us = <500>;
189 min-residency-us = <2000>;
197 min-volt = <800000>; /* uV */
198 min-freq = <408000>; /* KHz */
199 leakage-adjust-volt = <
203 nvmem-cells = <&cpul_leakage>;
204 nvmem-cell-names = "cpu_leakage";
208 min-volt = <800000>; /* uV */
209 min-freq = <408000>; /* KHz */
210 leakage-adjust-volt = <
214 nvmem-cells = <&cpub_leakage>;
215 nvmem-cell-names = "cpu_leakage";
220 compatible = "arm,armv8-timer";
221 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
222 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
223 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
224 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
228 compatible = "arm,cortex-a53-pmu";
229 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
233 compatible = "arm,cortex-a72-pmu";
234 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
238 compatible = "fixed-clock";
240 clock-frequency = <24000000>;
241 clock-output-names = "xin24m";
245 compatible = "arm,amba-bus";
246 #address-cells = <2>;
250 dmac_bus: dma-controller@ff6d0000 {
251 compatible = "arm,pl330", "arm,primecell";
252 reg = <0x0 0xff6d0000 0x0 0x4000>;
253 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
254 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
256 clocks = <&cru ACLK_DMAC0_PERILP>;
257 clock-names = "apb_pclk";
258 peripherals-req-type-burst;
261 dmac_peri: dma-controller@ff6e0000 {
262 compatible = "arm,pl330", "arm,primecell";
263 reg = <0x0 0xff6e0000 0x0 0x4000>;
264 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
265 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
267 clocks = <&cru ACLK_DMAC1_PERILP>;
268 clock-names = "apb_pclk";
269 peripherals-req-type-burst;
274 compatible = "rockchip,rk3399-gmac";
275 reg = <0x0 0xfe300000 0x0 0x10000>;
276 rockchip,grf = <&grf>;
277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
278 interrupt-names = "macirq";
279 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
280 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
281 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
283 clock-names = "stmmaceth", "mac_clk_rx",
284 "mac_clk_tx", "clk_mac_ref",
285 "clk_mac_refout", "aclk_mac",
287 resets = <&cru SRST_A_GMAC>;
288 reset-names = "stmmaceth";
289 power-domains = <&power RK3399_PD_GMAC>;
293 sdio0: dwmmc@fe310000 {
294 compatible = "rockchip,rk3399-dw-mshc",
295 "rockchip,rk3288-dw-mshc";
296 reg = <0x0 0xfe310000 0x0 0x4000>;
297 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
298 clock-freq-min-max = <400000 150000000>;
299 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
300 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
302 fifo-depth = <0x100>;
303 power-domains = <&power RK3399_PD_SDIOAUDIO>;
307 sdmmc: dwmmc@fe320000 {
308 compatible = "rockchip,rk3399-dw-mshc",
309 "rockchip,rk3288-dw-mshc";
310 reg = <0x0 0xfe320000 0x0 0x4000>;
311 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
312 clock-freq-min-max = <400000 150000000>;
313 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
314 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
315 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
316 fifo-depth = <0x100>;
317 power-domains = <&power RK3399_PD_SD>;
321 sdhci: sdhci@fe330000 {
322 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
323 reg = <0x0 0xfe330000 0x0 0x10000>;
324 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
325 arasan,soc-ctl-syscon = <&grf>;
326 assigned-clocks = <&cru SCLK_EMMC>;
327 assigned-clock-rates = <200000000>;
328 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
329 clock-names = "clk_xin", "clk_ahb";
330 clock-output-names = "emmc_cardclock";
333 phy-names = "phy_arasan";
334 power-domains = <&power RK3399_PD_EMMC>;
338 usb_host0_ehci: usb@fe380000 {
339 compatible = "generic-ehci";
340 reg = <0x0 0xfe380000 0x0 0x20000>;
341 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
342 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
343 <&cru SCLK_USBPHY0_480M_SRC>;
344 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
345 phys = <&u2phy0_host>;
347 power-domains = <&power RK3399_PD_PERIHP>;
351 usb_host0_ohci: usb@fe3a0000 {
352 compatible = "generic-ohci";
353 reg = <0x0 0xfe3a0000 0x0 0x20000>;
354 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
355 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
356 <&cru SCLK_USBPHY0_480M_SRC>;
357 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
358 phys = <&u2phy0_host>;
360 power-domains = <&power RK3399_PD_PERIHP>;
364 usb_host1_ehci: usb@fe3c0000 {
365 compatible = "generic-ehci";
366 reg = <0x0 0xfe3c0000 0x0 0x20000>;
367 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
368 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
369 <&cru SCLK_USBPHY1_480M_SRC>;
370 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
371 phys = <&u2phy1_host>;
373 power-domains = <&power RK3399_PD_PERIHP>;
377 usb_host1_ohci: usb@fe3e0000 {
378 compatible = "generic-ohci";
379 reg = <0x0 0xfe3e0000 0x0 0x20000>;
380 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
381 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
382 <&cru SCLK_USBPHY1_480M_SRC>;
383 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
384 phys = <&u2phy1_host>;
386 power-domains = <&power RK3399_PD_PERIHP>;
390 usbdrd3_0: usb@fe800000 {
391 compatible = "rockchip,rk3399-dwc3";
392 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
393 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
394 clock-names = "ref_clk", "suspend_clk",
395 "bus_clk", "grf_clk";
396 power-domains = <&power RK3399_PD_USB3>;
397 resets = <&cru SRST_A_USB3_OTG0>;
398 reset-names = "usb3-otg";
399 #address-cells = <2>;
403 usbdrd_dwc3_0: dwc3@fe800000 {
404 compatible = "snps,dwc3";
405 reg = <0x0 0xfe800000 0x0 0x100000>;
406 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
408 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
409 phy-names = "usb2-phy", "usb3-phy";
410 phy_type = "utmi_wide";
411 snps,dis_enblslpm_quirk;
412 snps,dis-u2-freeclk-exists-quirk;
413 snps,dis_u2_susphy_quirk;
414 snps,dis-del-phy-power-chg-quirk;
415 snps,xhci-slow-suspend-quirk;
420 usbdrd3_1: usb@fe900000 {
421 compatible = "rockchip,rk3399-dwc3";
422 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
423 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
424 clock-names = "ref_clk", "suspend_clk",
425 "bus_clk", "grf_clk";
426 power-domains = <&power RK3399_PD_USB3>;
427 resets = <&cru SRST_A_USB3_OTG1>;
428 reset-names = "usb3-otg";
429 #address-cells = <2>;
433 usbdrd_dwc3_1: dwc3@fe900000 {
434 compatible = "snps,dwc3";
435 reg = <0x0 0xfe900000 0x0 0x100000>;
436 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
438 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
439 phy-names = "usb2-phy", "usb3-phy";
440 phy_type = "utmi_wide";
441 snps,dis_enblslpm_quirk;
442 snps,dis-u2-freeclk-exists-quirk;
443 snps,dis_u2_susphy_quirk;
444 snps,dis-del-phy-power-chg-quirk;
445 snps,xhci-slow-suspend-quirk;
450 gic: interrupt-controller@fee00000 {
451 compatible = "arm,gic-v3";
452 #interrupt-cells = <4>;
453 #address-cells = <2>;
456 interrupt-controller;
458 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
459 <0x0 0xfef00000 0 0xc0000>, /* GICR */
460 <0x0 0xfff00000 0 0x10000>, /* GICC */
461 <0x0 0xfff10000 0 0x10000>, /* GICH */
462 <0x0 0xfff20000 0 0x10000>; /* GICV */
463 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
464 its: interrupt-controller@fee20000 {
465 compatible = "arm,gic-v3-its";
467 reg = <0x0 0xfee20000 0x0 0x20000>;
471 part0: interrupt-partition-0 {
472 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
475 part1: interrupt-partition-1 {
476 affinity = <&cpu_b0 &cpu_b1>;
481 saradc: saradc@ff100000 {
482 compatible = "rockchip,rk3399-saradc";
483 reg = <0x0 0xff100000 0x0 0x100>;
484 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
485 #io-channel-cells = <1>;
486 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
487 clock-names = "saradc", "apb_pclk";
488 resets = <&cru SRST_P_SARADC>;
489 reset-names = "saradc-apb";
494 compatible = "rockchip,rk3399-i2c";
495 reg = <0x0 0xff3c0000 0x0 0x1000>;
496 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
497 clock-names = "i2c", "pclk";
498 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&i2c0_xfer>;
501 #address-cells = <1>;
507 compatible = "rockchip,rk3399-i2c";
508 reg = <0x0 0xff110000 0x0 0x1000>;
509 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
510 clock-names = "i2c", "pclk";
511 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&i2c1_xfer>;
514 #address-cells = <1>;
520 compatible = "rockchip,rk3399-i2c";
521 reg = <0x0 0xff120000 0x0 0x1000>;
522 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
523 clock-names = "i2c", "pclk";
524 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&i2c2_xfer>;
527 #address-cells = <1>;
533 compatible = "rockchip,rk3399-i2c";
534 reg = <0x0 0xff130000 0x0 0x1000>;
535 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
536 clock-names = "i2c", "pclk";
537 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c3_xfer>;
540 #address-cells = <1>;
546 compatible = "rockchip,rk3399-i2c";
547 reg = <0x0 0xff140000 0x0 0x1000>;
548 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
549 clock-names = "i2c", "pclk";
550 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c5_xfer>;
553 #address-cells = <1>;
559 compatible = "rockchip,rk3399-i2c";
560 reg = <0x0 0xff150000 0x0 0x1000>;
561 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
562 clock-names = "i2c", "pclk";
563 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c6_xfer>;
566 #address-cells = <1>;
572 compatible = "rockchip,rk3399-i2c";
573 reg = <0x0 0xff160000 0x0 0x1000>;
574 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
575 clock-names = "i2c", "pclk";
576 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&i2c7_xfer>;
579 #address-cells = <1>;
584 uart0: serial@ff180000 {
585 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
586 reg = <0x0 0xff180000 0x0 0x100>;
587 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
588 clock-names = "baudclk", "apb_pclk";
589 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
597 uart1: serial@ff190000 {
598 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
599 reg = <0x0 0xff190000 0x0 0x100>;
600 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
601 clock-names = "baudclk", "apb_pclk";
602 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&uart1_xfer>;
610 uart2: serial@ff1a0000 {
611 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
612 reg = <0x0 0xff1a0000 0x0 0x100>;
613 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
614 clock-names = "baudclk", "apb_pclk";
615 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&uart2c_xfer>;
623 uart3: serial@ff1b0000 {
624 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
625 reg = <0x0 0xff1b0000 0x0 0x100>;
626 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
627 clock-names = "baudclk", "apb_pclk";
628 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
637 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
638 reg = <0x0 0xff1c0000 0x0 0x1000>;
639 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
640 clock-names = "spiclk", "apb_pclk";
641 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
644 #address-cells = <1>;
650 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
651 reg = <0x0 0xff1d0000 0x0 0x1000>;
652 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
653 clock-names = "spiclk", "apb_pclk";
654 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
657 #address-cells = <1>;
663 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
664 reg = <0x0 0xff1e0000 0x0 0x1000>;
665 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
666 clock-names = "spiclk", "apb_pclk";
667 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
670 #address-cells = <1>;
676 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
677 reg = <0x0 0xff1f0000 0x0 0x1000>;
678 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
679 clock-names = "spiclk", "apb_pclk";
680 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
681 pinctrl-names = "default";
682 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
683 #address-cells = <1>;
689 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
690 reg = <0x0 0xff200000 0x0 0x1000>;
691 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
692 clock-names = "spiclk", "apb_pclk";
693 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
694 pinctrl-names = "default";
695 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
696 #address-cells = <1>;
702 soc_thermal: soc-thermal {
703 polling-delay-passive = <20>; /* milliseconds */
704 polling-delay = <1000>; /* milliseconds */
705 sustainable-power = <1000>; /* milliwatts */
707 thermal-sensors = <&tsadc 0>;
710 threshold: trip-point@0 {
711 temperature = <70000>; /* millicelsius */
712 hysteresis = <2000>; /* millicelsius */
715 target: trip-point@1 {
716 temperature = <85000>; /* millicelsius */
717 hysteresis = <2000>; /* millicelsius */
721 temperature = <95000>; /* millicelsius */
722 hysteresis = <2000>; /* millicelsius */
731 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
732 contribution = <4096>;
737 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
738 contribution = <1024>;
743 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
744 contribution = <4096>;
749 gpu_thermal: gpu-thermal {
750 polling-delay-passive = <100>; /* milliseconds */
751 polling-delay = <1000>; /* milliseconds */
753 thermal-sensors = <&tsadc 1>;
757 tsadc: tsadc@ff260000 {
758 compatible = "rockchip,rk3399-tsadc";
759 reg = <0x0 0xff260000 0x0 0x100>;
760 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
761 rockchip,grf = <&grf>;
762 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
763 clock-names = "tsadc", "apb_pclk";
764 assigned-clocks = <&cru SCLK_TSADC>;
765 assigned-clock-rates = <750000>;
766 resets = <&cru SRST_TSADC>;
767 reset-names = "tsadc-apb";
768 pinctrl-names = "init", "default", "sleep";
769 pinctrl-0 = <&otp_gpio>;
770 pinctrl-1 = <&otp_out>;
771 pinctrl-2 = <&otp_gpio>;
772 #thermal-sensor-cells = <1>;
773 rockchip,hw-tshut-temp = <95000>;
777 qos_emmc: qos@ffa58000 {
778 compatible = "syscon";
779 reg = <0x0 0xffa58000 0x0 0x20>;
782 qos_gmac: qos@ffa5c000 {
783 compatible = "syscon";
784 reg = <0x0 0xffa5c000 0x0 0x20>;
787 qos_pcie: qos@ffa60080 {
788 compatible = "syscon";
789 reg = <0x0 0xffa60080 0x0 0x20>;
792 qos_usb_host0: qos@ffa60100 {
793 compatible = "syscon";
794 reg = <0x0 0xffa60100 0x0 0x20>;
797 qos_usb_host1: qos@ffa60180 {
798 compatible = "syscon";
799 reg = <0x0 0xffa60180 0x0 0x20>;
802 qos_usb_otg0: qos@ffa70000 {
803 compatible = "syscon";
804 reg = <0x0 0xffa70000 0x0 0x20>;
807 qos_usb_otg1: qos@ffa70080 {
808 compatible = "syscon";
809 reg = <0x0 0xffa70080 0x0 0x20>;
812 qos_sd: qos@ffa74000 {
813 compatible = "syscon";
814 reg = <0x0 0xffa74000 0x0 0x20>;
817 qos_sdioaudio: qos@ffa76000 {
818 compatible = "syscon";
819 reg = <0x0 0xffa76000 0x0 0x20>;
822 qos_hdcp: qos@ffa90000 {
823 compatible = "syscon";
824 reg = <0x0 0xffa90000 0x0 0x20>;
827 qos_iep: qos@ffa98000 {
828 compatible = "syscon";
829 reg = <0x0 0xffa98000 0x0 0x20>;
832 qos_isp0_m0: qos@ffaa0000 {
833 compatible = "syscon";
834 reg = <0x0 0xffaa0000 0x0 0x20>;
837 qos_isp0_m1: qos@ffaa0080 {
838 compatible = "syscon";
839 reg = <0x0 0xffaa0080 0x0 0x20>;
842 qos_isp1_m0: qos@ffaa8000 {
843 compatible = "syscon";
844 reg = <0x0 0xffaa8000 0x0 0x20>;
847 qos_isp1_m1: qos@ffaa8080 {
848 compatible = "syscon";
849 reg = <0x0 0xffaa8080 0x0 0x20>;
852 qos_rga_r: qos@ffab0000 {
853 compatible = "syscon";
854 reg = <0x0 0xffab0000 0x0 0x20>;
857 qos_rga_w: qos@ffab0080 {
858 compatible = "syscon";
859 reg = <0x0 0xffab0080 0x0 0x20>;
862 qos_video_m0: qos@ffab8000 {
863 compatible = "syscon";
864 reg = <0x0 0xffab8000 0x0 0x20>;
867 qos_video_m1_r: qos@ffac0000 {
868 compatible = "syscon";
869 reg = <0x0 0xffac0000 0x0 0x20>;
872 qos_video_m1_w: qos@ffac0080 {
873 compatible = "syscon";
874 reg = <0x0 0xffac0080 0x0 0x20>;
877 qos_vop_big_r: qos@ffac8000 {
878 compatible = "syscon";
879 reg = <0x0 0xffac8000 0x0 0x20>;
882 qos_vop_big_w: qos@ffac8080 {
883 compatible = "syscon";
884 reg = <0x0 0xffac8080 0x0 0x20>;
887 qos_vop_little: qos@ffad0000 {
888 compatible = "syscon";
889 reg = <0x0 0xffad0000 0x0 0x20>;
892 qos_perihp: qos@ffad8080 {
893 compatible = "syscon";
894 reg = <0x0 0xffad8080 0x0 0x20>;
897 qos_gpu: qos@ffae0000 {
898 compatible = "syscon";
899 reg = <0x0 0xffae0000 0x0 0x20>;
902 pmu: power-management@ff310000 {
903 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
904 reg = <0x0 0xff310000 0x0 0x1000>;
907 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
908 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
909 * Some of the power domains are grouped together for every
911 * The detail contents as below.
913 power: power-controller {
914 compatible = "rockchip,rk3399-power-controller";
915 #power-domain-cells = <1>;
916 #address-cells = <1>;
919 /* These power domains are grouped by VD_CENTER */
920 pd_iep@RK3399_PD_IEP {
921 reg = <RK3399_PD_IEP>;
922 clocks = <&cru ACLK_IEP>,
926 pd_rga@RK3399_PD_RGA {
927 reg = <RK3399_PD_RGA>;
928 clocks = <&cru ACLK_RGA>,
930 pm_qos = <&qos_rga_r>,
933 pd_vcodec@RK3399_PD_VCODEC {
934 reg = <RK3399_PD_VCODEC>;
935 clocks = <&cru ACLK_VCODEC>,
937 pm_qos = <&qos_video_m0>;
939 pd_vdu@RK3399_PD_VDU {
940 reg = <RK3399_PD_VDU>;
941 clocks = <&cru ACLK_VDU>,
943 pm_qos = <&qos_video_m1_r>,
947 /* These power domains are grouped by VD_GPU */
948 pd_gpu@RK3399_PD_GPU {
949 reg = <RK3399_PD_GPU>;
950 clocks = <&cru ACLK_GPU>;
954 /* These power domains are grouped by VD_LOGIC */
955 pd_edp@RK3399_PD_EDP {
956 reg = <RK3399_PD_EDP>;
957 clocks = <&cru PCLK_EDP_CTRL>;
959 pd_emmc@RK3399_PD_EMMC {
960 reg = <RK3399_PD_EMMC>;
961 clocks = <&cru ACLK_EMMC>;
962 pm_qos = <&qos_emmc>;
964 pd_gmac@RK3399_PD_GMAC {
965 reg = <RK3399_PD_GMAC>;
966 clocks = <&cru ACLK_GMAC>,
968 pm_qos = <&qos_gmac>;
970 pd_perihp@RK3399_PD_PERIHP {
971 reg = <RK3399_PD_PERIHP>;
972 #address-cells = <1>;
974 clocks = <&cru ACLK_PERIHP>;
975 pm_qos = <&qos_perihp>,
981 reg = <RK3399_PD_SD>;
982 clocks = <&cru HCLK_SDMMC>,
987 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
988 reg = <RK3399_PD_SDIOAUDIO>;
989 clocks = <&cru HCLK_SDIO>;
990 pm_qos = <&qos_sdioaudio>;
992 pd_usb3@RK3399_PD_USB3 {
993 reg = <RK3399_PD_USB3>;
994 clocks = <&cru ACLK_USB3>;
995 pm_qos = <&qos_usb_otg0>,
998 pd_vio@RK3399_PD_VIO {
999 reg = <RK3399_PD_VIO>;
1000 #address-cells = <1>;
1003 pd_hdcp@RK3399_PD_HDCP {
1004 reg = <RK3399_PD_HDCP>;
1005 clocks = <&cru ACLK_HDCP>,
1008 pm_qos = <&qos_hdcp>;
1010 pd_isp0@RK3399_PD_ISP0 {
1011 reg = <RK3399_PD_ISP0>;
1012 clocks = <&cru ACLK_ISP0>,
1014 pm_qos = <&qos_isp0_m0>,
1017 pd_isp1@RK3399_PD_ISP1 {
1018 reg = <RK3399_PD_ISP1>;
1019 clocks = <&cru ACLK_ISP1>,
1021 pm_qos = <&qos_isp1_m0>,
1024 pd_tcpc0@RK3399_PD_TCPC0 {
1025 reg = <RK3399_PD_TCPD0>;
1026 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1027 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1029 pd_tcpc1@RK3399_PD_TCPC1 {
1030 reg = <RK3399_PD_TCPD1>;
1031 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1032 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1034 pd_vo@RK3399_PD_VO {
1035 reg = <RK3399_PD_VO>;
1036 #address-cells = <1>;
1039 pd_vopb@RK3399_PD_VOPB {
1040 reg = <RK3399_PD_VOPB>;
1041 clocks = <&cru ACLK_VOP0>,
1043 pm_qos = <&qos_vop_big_r>,
1046 pd_vopl@RK3399_PD_VOPL {
1047 reg = <RK3399_PD_VOPL>;
1048 clocks = <&cru ACLK_VOP1>,
1050 pm_qos = <&qos_vop_little>;
1057 pmugrf: syscon@ff320000 {
1058 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1059 reg = <0x0 0xff320000 0x0 0x1000>;
1062 compatible = "syscon-reboot-mode";
1064 mode-bootloader = <BOOT_LOADER>;
1065 mode-charge = <BOOT_CHARGING>;
1066 mode-fastboot = <BOOT_FASTBOOT>;
1067 mode-loader = <BOOT_LOADER>;
1068 mode-normal = <BOOT_NORMAL>;
1069 mode-recovery = <BOOT_RECOVERY>;
1070 mode-ums = <BOOT_UMS>;
1073 pmu_pvtm: pmu-pvtm {
1074 compatible = "rockchip,rk3399-pmu-pvtm";
1075 clocks = <&pmucru SCLK_PVTM_PMU>;
1076 clock-names = "pmu";
1077 status = "disabled";
1081 spi3: spi@ff350000 {
1082 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1083 reg = <0x0 0xff350000 0x0 0x1000>;
1084 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1085 clock-names = "spiclk", "apb_pclk";
1086 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1087 pinctrl-names = "default";
1088 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1089 #address-cells = <1>;
1091 status = "disabled";
1094 uart4: serial@ff370000 {
1095 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1096 reg = <0x0 0xff370000 0x0 0x100>;
1097 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1098 clock-names = "baudclk", "apb_pclk";
1099 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&uart4_xfer>;
1104 status = "disabled";
1107 i2c4: i2c@ff3d0000 {
1108 compatible = "rockchip,rk3399-i2c";
1109 reg = <0x0 0xff3d0000 0x0 0x1000>;
1110 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1111 clock-names = "i2c", "pclk";
1112 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1113 pinctrl-names = "default";
1114 pinctrl-0 = <&i2c4_xfer>;
1115 #address-cells = <1>;
1117 status = "disabled";
1120 i2c8: i2c@ff3e0000 {
1121 compatible = "rockchip,rk3399-i2c";
1122 reg = <0x0 0xff3e0000 0x0 0x1000>;
1123 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1124 clock-names = "i2c", "pclk";
1125 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1126 pinctrl-names = "default";
1127 pinctrl-0 = <&i2c8_xfer>;
1128 #address-cells = <1>;
1130 status = "disabled";
1133 pcie_phy: phy@e220 {
1134 compatible = "rockchip,rk3399-pcie-phy";
1136 rockchip,grf = <&grf>;
1137 clocks = <&cru SCLK_PCIEPHY_REF>;
1138 clock-names = "refclk";
1139 resets = <&cru SRST_PCIEPHY>;
1140 reset-names = "phy";
1141 status = "disabled";
1144 pcie0: pcie@f8000000 {
1145 compatible = "rockchip,rk3399-pcie";
1146 #address-cells = <3>;
1148 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1149 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1150 clock-names = "aclk", "aclk-perf",
1152 bus-range = <0x0 0x1>;
1153 msi-map = <0x0 &its 0x0 0x1000>;
1154 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1155 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1156 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1157 interrupt-names = "sys", "legacy", "client";
1158 #interrupt-cells = <1>;
1159 interrupt-map-mask = <0 0 0 7>;
1160 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1161 <0 0 0 2 &pcie0_intc 1>,
1162 <0 0 0 3 &pcie0_intc 2>,
1163 <0 0 0 4 &pcie0_intc 3>;
1165 phy-names = "pcie-phy";
1166 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1167 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1168 reg = <0x0 0xf8000000 0x0 0x2000000>,
1169 <0x0 0xfd000000 0x0 0x1000000>;
1170 reg-names = "axi-base", "apb-base";
1171 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1172 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1173 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1175 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1176 "pm", "pclk", "aclk";
1177 status = "disabled";
1178 pcie0_intc: interrupt-controller {
1179 interrupt-controller;
1180 #address-cells = <0>;
1181 #interrupt-cells = <1>;
1185 pwm0: pwm@ff420000 {
1186 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1187 reg = <0x0 0xff420000 0x0 0x10>;
1189 pinctrl-names = "default";
1190 pinctrl-0 = <&pwm0_pin>;
1191 clocks = <&pmucru PCLK_RKPWM_PMU>;
1192 clock-names = "pwm";
1193 status = "disabled";
1196 pwm1: pwm@ff420010 {
1197 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1198 reg = <0x0 0xff420010 0x0 0x10>;
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&pwm1_pin>;
1202 clocks = <&pmucru PCLK_RKPWM_PMU>;
1203 clock-names = "pwm";
1204 status = "disabled";
1207 pwm2: pwm@ff420020 {
1208 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1209 reg = <0x0 0xff420020 0x0 0x10>;
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&pwm2_pin>;
1213 clocks = <&pmucru PCLK_RKPWM_PMU>;
1214 clock-names = "pwm";
1215 status = "disabled";
1218 pwm3: pwm@ff420030 {
1219 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1220 reg = <0x0 0xff420030 0x0 0x10>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&pwm3a_pin>;
1224 clocks = <&pmucru PCLK_RKPWM_PMU>;
1225 clock-names = "pwm";
1226 status = "disabled";
1230 reg = <0x00 0xff630000 0x00 0x4000>;
1231 compatible = "rockchip,rk3399-dfi";
1232 rockchip,pmu = <&pmugrf>;
1233 clocks = <&cru PCLK_DDR_MON>;
1234 clock-names = "pclk_ddr_mon";
1235 status = "disabled";
1239 compatible = "rockchip,rk3399-dmc";
1240 devfreq-events = <&dfi>;
1241 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1242 clocks = <&cru SCLK_DDRCLK>;
1243 clock-names = "dmc_clk";
1244 ddr_timing = <&ddr_timing>;
1245 status = "disabled";
1249 compatible = "rockchip,rk3399-rga";
1250 reg = <0x0 0xff680000 0x0 0x10000>;
1251 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1252 interrupt-names = "rga";
1253 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1254 clock-names = "aclk", "hclk", "sclk";
1255 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1256 reset-names = "core", "axi", "ahb";
1257 power-domains = <&power RK3399_PD_RGA>;
1258 status = "disabled";
1261 efuse0: efuse@ff690000 {
1262 compatible = "rockchip,rk3399-efuse";
1263 reg = <0x0 0xff690000 0x0 0x80>;
1264 #address-cells = <1>;
1266 clocks = <&cru PCLK_EFUSE1024NS>;
1267 clock-names = "pclk_efuse";
1270 cpul_leakage: cpul-leakage {
1273 cpub_leakage: cpub-leakage {
1276 gpu_leakage: gpu-leakage {
1279 center_leakage: center-leakage {
1282 logic_leakage: logic-leakage {
1285 wafer_info: wafer-info {
1290 pmucru: pmu-clock-controller@ff750000 {
1291 compatible = "rockchip,rk3399-pmucru";
1292 reg = <0x0 0xff750000 0x0 0x1000>;
1295 assigned-clocks = <&pmucru PLL_PPLL>;
1296 assigned-clock-rates = <676000000>;
1299 cru: clock-controller@ff760000 {
1300 compatible = "rockchip,rk3399-cru";
1301 reg = <0x0 0xff760000 0x0 0x1000>;
1305 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1306 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1307 <&cru ARMCLKL>, <&cru ARMCLKB>,
1308 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1309 <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1310 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1312 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1313 <&cru PCLK_PERILP0>,
1314 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1315 assigned-clock-rates =
1316 <400000000>, <200000000>,
1317 <400000000>, <200000000>,
1318 <816000000>, <816000000>,
1319 <594000000>, <800000000>,
1320 <200000000>, <1000000000>,
1321 <150000000>, <75000000>,
1323 <100000000>, <100000000>,
1325 <100000000>, <50000000>;
1328 grf: syscon@ff770000 {
1329 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1330 reg = <0x0 0xff770000 0x0 0x10000>;
1331 #address-cells = <1>;
1334 emmc_phy: phy@f780 {
1335 compatible = "rockchip,rk3399-emmc-phy";
1336 reg = <0xf780 0x24>;
1338 clock-names = "emmcclk";
1340 status = "disabled";
1343 u2phy0: usb2-phy@e450 {
1344 compatible = "rockchip,rk3399-usb2phy";
1345 reg = <0xe450 0x10>;
1346 clocks = <&cru SCLK_USB2PHY0_REF>;
1347 clock-names = "phyclk";
1349 clock-output-names = "clk_usbphy0_480m";
1350 status = "disabled";
1352 u2phy0_otg: otg-port {
1354 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1355 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1356 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1357 interrupt-names = "otg-bvalid", "otg-id",
1359 status = "disabled";
1362 u2phy0_host: host-port {
1364 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1365 interrupt-names = "linestate";
1366 status = "disabled";
1370 u2phy1: usb2-phy@e460 {
1371 compatible = "rockchip,rk3399-usb2phy";
1372 reg = <0xe460 0x10>;
1373 clocks = <&cru SCLK_USB2PHY1_REF>;
1374 clock-names = "phyclk";
1376 clock-output-names = "clk_usbphy1_480m";
1377 status = "disabled";
1379 u2phy1_otg: otg-port {
1381 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1382 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1383 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1384 interrupt-names = "otg-bvalid", "otg-id",
1386 status = "disabled";
1389 u2phy1_host: host-port {
1391 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1392 interrupt-names = "linestate";
1393 status = "disabled";
1398 compatible = "rockchip,rk3399-pvtm";
1399 clocks = <&cru SCLK_PVTM_CORE_L>,
1400 <&cru SCLK_PVTM_CORE_B>,
1401 <&cru SCLK_PVTM_GPU>,
1402 <&cru SCLK_PVTM_DDR>;
1403 clock-names = "core_l", "core_b", "gpu", "ddr";
1404 status = "disabled";
1408 tcphy0: phy@ff7c0000 {
1409 compatible = "rockchip,rk3399-typec-phy";
1410 reg = <0x0 0xff7c0000 0x0 0x40000>;
1411 rockchip,grf = <&grf>;
1413 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1414 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1415 clock-names = "tcpdcore", "tcpdphy-ref";
1416 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1417 assigned-clock-rates = <50000000>;
1418 power-domains = <&power RK3399_PD_TCPD0>;
1419 resets = <&cru SRST_UPHY0>,
1420 <&cru SRST_UPHY0_PIPE_L00>,
1421 <&cru SRST_P_UPHY0_TCPHY>;
1422 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1423 rockchip,typec-conn-dir = <0xe580 0 16>;
1424 rockchip,usb3tousb2-en = <0xe580 3 19>;
1425 rockchip,usb3-host-disable = <0x2434 0 16>;
1426 rockchip,usb3-host-port = <0x2434 12 28>;
1427 rockchip,external-psm = <0xe588 14 30>;
1428 rockchip,pipe-status = <0xe5c0 0 0>;
1429 rockchip,uphy-dp-sel = <0x6268 19 19>;
1430 status = "disabled";
1432 tcphy0_dp: dp-port {
1436 tcphy0_usb3: usb3-port {
1441 tcphy1: phy@ff800000 {
1442 compatible = "rockchip,rk3399-typec-phy";
1443 reg = <0x0 0xff800000 0x0 0x40000>;
1444 rockchip,grf = <&grf>;
1446 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1447 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1448 clock-names = "tcpdcore", "tcpdphy-ref";
1449 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1450 assigned-clock-rates = <50000000>;
1451 power-domains = <&power RK3399_PD_TCPD1>;
1452 resets = <&cru SRST_UPHY1>,
1453 <&cru SRST_UPHY1_PIPE_L00>,
1454 <&cru SRST_P_UPHY1_TCPHY>;
1455 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1456 rockchip,typec-conn-dir = <0xe58c 0 16>;
1457 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1458 rockchip,usb3-host-disable = <0x2444 0 16>;
1459 rockchip,usb3-host-port = <0x2444 12 28>;
1460 rockchip,external-psm = <0xe594 14 30>;
1461 rockchip,pipe-status = <0xe5c0 16 16>;
1462 rockchip,uphy-dp-sel = <0x6268 3 19>;
1463 status = "disabled";
1465 tcphy1_dp: dp-port {
1469 tcphy1_usb3: usb3-port {
1475 compatible = "snps,dw-wdt";
1476 reg = <0x0 0xff848000 0x0 0x100>;
1477 clocks = <&cru PCLK_WDT>;
1478 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1481 rktimer: rktimer@ff850000 {
1482 compatible = "rockchip,rk3399-timer";
1483 reg = <0x0 0xff850000 0x0 0x1000>;
1484 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1485 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1486 clock-names = "pclk", "timer";
1489 spdif: spdif@ff870000 {
1490 compatible = "rockchip,rk3399-spdif";
1491 reg = <0x0 0xff870000 0x0 0x1000>;
1492 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1493 dmas = <&dmac_bus 7>;
1495 clock-names = "mclk", "hclk";
1496 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1497 pinctrl-names = "default";
1498 pinctrl-0 = <&spdif_bus>;
1499 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1500 status = "disabled";
1503 i2s0: i2s@ff880000 {
1504 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1505 reg = <0x0 0xff880000 0x0 0x1000>;
1506 rockchip,grf = <&grf>;
1507 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1508 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1509 dma-names = "tx", "rx";
1510 clock-names = "i2s_clk", "i2s_hclk";
1511 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1512 pinctrl-names = "default";
1513 pinctrl-0 = <&i2s0_8ch_bus>;
1514 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1515 status = "disabled";
1518 i2s1: i2s@ff890000 {
1519 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1520 reg = <0x0 0xff890000 0x0 0x1000>;
1521 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1522 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1523 dma-names = "tx", "rx";
1524 clock-names = "i2s_clk", "i2s_hclk";
1525 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1526 pinctrl-names = "default";
1527 pinctrl-0 = <&i2s1_2ch_bus>;
1528 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1529 status = "disabled";
1532 i2s2: i2s@ff8a0000 {
1533 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1534 reg = <0x0 0xff8a0000 0x0 0x1000>;
1535 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1536 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1537 dma-names = "tx", "rx";
1538 clock-names = "i2s_clk", "i2s_hclk";
1539 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1540 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1541 status = "disabled";
1545 compatible = "arm,malit860",
1550 reg = <0x0 0xff9a0000 0x0 0x10000>;
1552 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1553 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1554 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1555 interrupt-names = "GPU", "JOB", "MMU";
1557 clocks = <&cru ACLK_GPU>;
1558 clock-names = "clk_mali";
1559 #cooling-cells = <2>; /* min followed by max */
1560 power-domains = <&power RK3399_PD_GPU>;
1561 power-off-delay-ms = <200>;
1562 status = "disabled";
1564 gpu_power_model: power_model {
1565 compatible = "arm,mali-simple-power-model";
1568 static-power = <300>;
1569 dynamic-power = <396>;
1570 ts = <32000 4700 (-80) 2>;
1571 thermal-zone = "gpu-thermal";
1575 vopl: vop@ff8f0000 {
1576 compatible = "rockchip,rk3399-vop-lit";
1577 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1578 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1579 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1580 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1581 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1582 reset-names = "axi", "ahb", "dclk";
1583 power-domains = <&power RK3399_PD_VOPL>;
1584 iommus = <&vopl_mmu>;
1585 status = "disabled";
1588 #address-cells = <1>;
1591 vopl_out_mipi: endpoint@0 {
1593 remote-endpoint = <&mipi_in_vopl>;
1596 vopl_out_edp: endpoint@1 {
1598 remote-endpoint = <&edp_in_vopl>;
1601 vopl_out_hdmi: endpoint@2 {
1603 remote-endpoint = <&hdmi_in_vopl>;
1608 vop1_pwm: voppwm@ff8f01a0 {
1609 compatible = "rockchip,vop-pwm";
1610 reg = <0x0 0xff8f01a0 0x0 0x10>;
1612 pinctrl-names = "default";
1613 pinctrl-0 = <&vop1_pwm_pin>;
1614 clocks = <&cru SCLK_VOP1_PWM>;
1615 clock-names = "pwm";
1616 status = "disabled";
1619 vopl_mmu: iommu@ff8f3f00 {
1620 compatible = "rockchip,iommu";
1621 reg = <0x0 0xff8f3f00 0x0 0x100>;
1622 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1623 interrupt-names = "vopl_mmu";
1625 status = "disabled";
1628 vopb: vop@ff900000 {
1629 compatible = "rockchip,rk3399-vop-big";
1630 reg = <0x0 0xff900000 0x0 0x3efc>;
1631 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1632 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1633 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1634 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1635 reset-names = "axi", "ahb", "dclk";
1636 power-domains = <&power RK3399_PD_VOPB>;
1637 iommus = <&vopb_mmu>;
1638 status = "disabled";
1641 #address-cells = <1>;
1644 vopb_out_edp: endpoint@0 {
1646 remote-endpoint = <&edp_in_vopb>;
1649 vopb_out_mipi: endpoint@1 {
1651 remote-endpoint = <&mipi_in_vopb>;
1654 vopb_out_hdmi: endpoint@2 {
1656 remote-endpoint = <&hdmi_in_vopb>;
1661 vop0_pwm: voppwm@ff9001a0 {
1662 compatible = "rockchip,vop-pwm";
1663 reg = <0x0 0xff9001a0 0x0 0x10>;
1665 pinctrl-names = "default";
1666 pinctrl-0 = <&vop0_pwm_pin>;
1667 clocks = <&cru SCLK_VOP0_PWM>;
1668 clock-names = "pwm";
1669 status = "disabled";
1672 vopb_mmu: iommu@ff903f00 {
1673 compatible = "rockchip,iommu";
1674 reg = <0x0 0xff903f00 0x0 0x100>;
1675 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1676 interrupt-names = "vopb_mmu";
1678 status = "disabled";
1681 isp0_mmu: iommu@ff914000 {
1682 compatible = "rockchip,iommu";
1683 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1684 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1685 interrupt-names = "isp0_mmu";
1687 status = "disabled";
1690 isp1_mmu: iommu@ff924000 {
1691 compatible = "rockchip,iommu";
1692 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1693 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1694 interrupt-names = "isp1_mmu";
1696 status = "disabled";
1699 hdmi: hdmi@ff940000 {
1700 compatible = "rockchip,rk3399-dw-hdmi";
1701 reg = <0x0 0xff940000 0x0 0x20000>;
1703 rockchip,grf = <&grf>;
1704 power-domains = <&power RK3399_PD_HDCP>;
1705 pinctrl-names = "default";
1706 pinctrl-0 = <&hdmi_i2c_xfer>;
1707 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1708 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1709 clock-names = "iahb", "isfr", "vpll", "grf";
1710 status = "disabled";
1714 #address-cells = <1>;
1716 hdmi_in_vopb: endpoint@0 {
1718 remote-endpoint = <&vopb_out_hdmi>;
1720 hdmi_in_vopl: endpoint@1 {
1722 remote-endpoint = <&vopl_out_hdmi>;
1728 mipi_dsi: mipi@ff960000 {
1729 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1730 reg = <0x0 0xff960000 0x0 0x8000>;
1731 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1732 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1733 <&cru SCLK_DPHY_TX0_CFG>;
1734 clock-names = "ref", "pclk", "phy_cfg";
1735 power-domains = <&power RK3399_PD_VIO>;
1736 rockchip,grf = <&grf>;
1737 #address-cells = <1>;
1739 status = "disabled";
1742 #address-cells = <1>;
1747 #address-cells = <1>;
1750 mipi_in_vopb: endpoint@0 {
1752 remote-endpoint = <&vopb_out_mipi>;
1754 mipi_in_vopl: endpoint@1 {
1756 remote-endpoint = <&vopl_out_mipi>;
1763 compatible = "rockchip,rk3399-edp";
1764 reg = <0x0 0xff970000 0x0 0x8000>;
1765 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1766 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1767 clock-names = "dp", "pclk";
1768 power-domains = <&power RK3399_PD_EDP>;
1769 resets = <&cru SRST_P_EDP_CTRL>;
1771 rockchip,grf = <&grf>;
1772 status = "disabled";
1773 pinctrl-names = "default";
1774 pinctrl-0 = <&edp_hpd>;
1777 #address-cells = <1>;
1782 #address-cells = <1>;
1785 edp_in_vopb: endpoint@0 {
1787 remote-endpoint = <&vopb_out_edp>;
1790 edp_in_vopl: endpoint@1 {
1792 remote-endpoint = <&vopl_out_edp>;
1798 display_subsystem: display-subsystem {
1799 compatible = "rockchip,display-subsystem";
1800 ports = <&vopl_out>, <&vopb_out>;
1801 status = "disabled";
1805 compatible = "rockchip,rk3399-pinctrl";
1806 rockchip,grf = <&grf>;
1807 rockchip,pmu = <&pmugrf>;
1808 #address-cells = <0x2>;
1809 #size-cells = <0x2>;
1812 gpio0: gpio0@ff720000 {
1813 compatible = "rockchip,gpio-bank";
1814 reg = <0x0 0xff720000 0x0 0x100>;
1815 clocks = <&pmucru PCLK_GPIO0_PMU>;
1816 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1819 #gpio-cells = <0x2>;
1821 interrupt-controller;
1822 #interrupt-cells = <0x2>;
1825 gpio1: gpio1@ff730000 {
1826 compatible = "rockchip,gpio-bank";
1827 reg = <0x0 0xff730000 0x0 0x100>;
1828 clocks = <&pmucru PCLK_GPIO1_PMU>;
1829 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1832 #gpio-cells = <0x2>;
1834 interrupt-controller;
1835 #interrupt-cells = <0x2>;
1838 gpio2: gpio2@ff780000 {
1839 compatible = "rockchip,gpio-bank";
1840 reg = <0x0 0xff780000 0x0 0x100>;
1841 clocks = <&cru PCLK_GPIO2>;
1842 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1845 #gpio-cells = <0x2>;
1847 interrupt-controller;
1848 #interrupt-cells = <0x2>;
1851 gpio3: gpio3@ff788000 {
1852 compatible = "rockchip,gpio-bank";
1853 reg = <0x0 0xff788000 0x0 0x100>;
1854 clocks = <&cru PCLK_GPIO3>;
1855 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1858 #gpio-cells = <0x2>;
1860 interrupt-controller;
1861 #interrupt-cells = <0x2>;
1864 gpio4: gpio4@ff790000 {
1865 compatible = "rockchip,gpio-bank";
1866 reg = <0x0 0xff790000 0x0 0x100>;
1867 clocks = <&cru PCLK_GPIO4>;
1868 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1871 #gpio-cells = <0x2>;
1873 interrupt-controller;
1874 #interrupt-cells = <0x2>;
1877 pcfg_pull_up: pcfg-pull-up {
1881 pcfg_pull_down: pcfg-pull-down {
1885 pcfg_pull_none: pcfg-pull-none {
1889 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1891 drive-strength = <20>;
1894 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1896 drive-strength = <20>;
1899 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1901 drive-strength = <18>;
1904 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1906 drive-strength = <12>;
1909 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1911 drive-strength = <8>;
1914 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1916 drive-strength = <4>;
1919 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1921 drive-strength = <2>;
1924 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1926 drive-strength = <12>;
1929 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1931 drive-strength = <13>;
1934 pcfg_output_high: pcfg-output-high {
1938 pcfg_output_low: pcfg-output-low {
1942 pcfg_input: pcfg-input {
1947 emmc_pwr: emmc-pwr {
1949 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1954 rgmii_pins: rgmii-pins {
1957 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1959 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1961 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1963 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1965 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1967 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1969 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1971 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1973 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1975 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1977 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1979 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1981 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1983 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1985 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1988 rmii_pins: rmii-pins {
1991 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1993 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1995 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1997 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1999 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2001 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2003 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2005 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2007 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2009 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2014 i2c0_xfer: i2c0-xfer {
2016 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2017 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2022 i2c1_xfer: i2c1-xfer {
2024 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2025 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2030 i2c2_xfer: i2c2-xfer {
2032 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2033 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2038 i2c3_xfer: i2c3-xfer {
2040 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2041 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2044 i2c3_gpio: i2c3_gpio {
2046 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2047 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2053 i2c4_xfer: i2c4-xfer {
2055 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2056 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2061 i2c5_xfer: i2c5-xfer {
2063 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2064 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2069 i2c6_xfer: i2c6-xfer {
2071 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2072 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2077 i2c7_xfer: i2c7-xfer {
2079 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2080 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2085 i2c8_xfer: i2c8-xfer {
2087 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2088 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2093 i2s0_8ch_bus: i2s0-8ch-bus {
2095 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2096 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2097 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2098 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2099 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2100 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2101 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2102 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2103 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2108 i2s1_2ch_bus: i2s1-2ch-bus {
2110 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2111 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2112 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2113 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2114 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2119 sdio0_bus1: sdio0-bus1 {
2121 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2124 sdio0_bus4: sdio0-bus4 {
2126 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2127 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2128 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2129 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2132 sdio0_cmd: sdio0-cmd {
2134 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2137 sdio0_clk: sdio0-clk {
2139 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2142 sdio0_cd: sdio0-cd {
2144 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2147 sdio0_pwr: sdio0-pwr {
2149 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2152 sdio0_bkpwr: sdio0-bkpwr {
2154 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2157 sdio0_wp: sdio0-wp {
2159 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2162 sdio0_int: sdio0-int {
2164 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2169 sdmmc_bus1: sdmmc-bus1 {
2171 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2174 sdmmc_bus4: sdmmc-bus4 {
2176 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2177 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2178 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2179 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2182 sdmmc_clk: sdmmc-clk {
2184 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2187 sdmmc_cmd: sdmmc-cmd {
2189 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2192 sdmmc_cd: sdmcc-cd {
2194 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2197 sdmmc_wp: sdmmc-wp {
2199 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2204 spdif_bus: spdif-bus {
2206 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2209 spdif_bus_1: spdif-bus-1 {
2211 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2216 spi0_clk: spi0-clk {
2218 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2220 spi0_cs0: spi0-cs0 {
2222 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2224 spi0_cs1: spi0-cs1 {
2226 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2230 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2234 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2239 spi1_clk: spi1-clk {
2241 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2243 spi1_cs0: spi1-cs0 {
2245 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2249 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2253 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2258 spi2_clk: spi2-clk {
2260 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2262 spi2_cs0: spi2-cs0 {
2264 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2268 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2272 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2277 spi3_clk: spi3-clk {
2279 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2281 spi3_cs0: spi3-cs0 {
2283 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2287 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2291 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2296 spi4_clk: spi4-clk {
2298 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2300 spi4_cs0: spi4-cs0 {
2302 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2306 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2310 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2315 spi5_clk: spi5-clk {
2317 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2319 spi5_cs0: spi5-cs0 {
2321 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2325 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2329 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2334 otp_gpio: otp-gpio {
2335 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2339 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2344 uart0_xfer: uart0-xfer {
2346 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2347 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2350 uart0_cts: uart0-cts {
2352 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2355 uart0_rts: uart0-rts {
2357 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2362 uart1_xfer: uart1-xfer {
2364 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2365 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2370 uart2a_xfer: uart2a-xfer {
2372 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2373 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2378 uart2b_xfer: uart2b-xfer {
2380 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2381 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2386 uart2c_xfer: uart2c-xfer {
2388 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2389 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2394 uart3_xfer: uart3-xfer {
2396 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2397 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2400 uart3_cts: uart3-cts {
2402 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2405 uart3_rts: uart3-rts {
2407 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2412 uart4_xfer: uart4-xfer {
2414 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2415 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2420 uarthdcp_xfer: uarthdcp-xfer {
2422 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2423 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2428 pwm0_pin: pwm0-pin {
2430 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2433 vop0_pwm_pin: vop0-pwm-pin {
2435 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2440 pwm1_pin: pwm1-pin {
2442 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2445 vop1_pwm_pin: vop1-pwm-pin {
2447 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2452 pwm2_pin: pwm2-pin {
2454 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2459 pwm3a_pin: pwm3a-pin {
2461 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2466 pwm3b_pin: pwm3b-pin {
2468 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2475 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2480 hdmi_i2c_xfer: hdmi-i2c-xfer {
2482 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2483 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2486 hdmi_cec: hdmi-cec {
2488 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2493 pcie_clkreqn: pci-clkreqn {
2495 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2498 pcie_clkreqnb: pci-clkreqnb {
2500 <4 24 RK_FUNC_1 &pcfg_pull_none>;