2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
105 compatible = "arm,cortex-a53", "arm,armv8";
108 #cooling-cells = <2>; /* min followed by max */
109 clocks = <&cru ARMCLKL>;
110 operating-points-v2 = <&cluster0_opp>;
115 compatible = "arm,cortex-a53", "arm,armv8";
117 clocks = <&cru ARMCLKL>;
118 operating-points-v2 = <&cluster0_opp>;
123 compatible = "arm,cortex-a53", "arm,armv8";
125 clocks = <&cru ARMCLKL>;
126 operating-points-v2 = <&cluster0_opp>;
131 compatible = "arm,cortex-a53", "arm,armv8";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
139 compatible = "arm,cortex-a72", "arm,armv8";
142 #cooling-cells = <2>; /* min followed by max */
143 clocks = <&cru ARMCLKB>;
144 operating-points-v2 = <&cluster1_opp>;
149 compatible = "arm,cortex-a72", "arm,armv8";
151 clocks = <&cru ARMCLKB>;
152 operating-points-v2 = <&cluster1_opp>;
156 cluster0_opp: opp_table0 {
157 compatible = "operating-points-v2";
161 opp-hz = /bits/ 64 <408000000>;
162 opp-microvolt = <1000000>;
163 clock-latency-ns = <40000>;
166 opp-hz = /bits/ 64 <600000000>;
167 opp-microvolt = <1000000>;
170 opp-hz = /bits/ 64 <816000000>;
171 opp-microvolt = <1000000>;
174 opp-hz = /bits/ 64 <1008000000>;
175 opp-microvolt = <1000000>;
179 cluster1_opp: opp_table1 {
180 compatible = "operating-points-v2";
184 opp-hz = /bits/ 64 <408000000>;
185 opp-microvolt = <1000000>;
186 clock-latency-ns = <40000>;
189 opp-hz = /bits/ 64 <600000000>;
190 opp-microvolt = <1000000>;
193 opp-hz = /bits/ 64 <816000000>;
194 opp-microvolt = <1000000>;
197 opp-hz = /bits/ 64 <1008000000>;
198 opp-microvolt = <1000000>;
201 opp-hz = /bits/ 64 <1200000000>;
202 opp-microvolt = <1000000>;
207 compatible = "arm,armv8-timer";
208 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
209 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
210 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
211 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
215 compatible = "arm,cortex-a53-pmu";
216 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
217 interrupt-affinity = <&cpu_l0>,
224 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
225 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
226 interrupt-affinity = <&cpu_b0>,
231 compatible = "fixed-clock";
233 clock-frequency = <24000000>;
234 clock-output-names = "xin24m";
238 compatible = "arm,amba-bus";
239 #address-cells = <2>;
243 dmac_bus: dma-controller@ff6d0000 {
244 compatible = "arm,pl330", "arm,primecell";
245 reg = <0x0 0xff6d0000 0x0 0x4000>;
246 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&cru ACLK_DMAC0_PERILP>;
250 clock-names = "apb_pclk";
253 dmac_peri: dma-controller@ff6e0000 {
254 compatible = "arm,pl330", "arm,primecell";
255 reg = <0x0 0xff6e0000 0x0 0x4000>;
256 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&cru ACLK_DMAC1_PERILP>;
260 clock-names = "apb_pclk";
265 compatible = "rockchip,rk3399-emmc-phy";
266 reg-offset = <0xf780>;
268 rockchip,grf = <&grf>;
272 sdio0: dwmmc@fe310000 {
273 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
274 reg = <0x0 0xfe310000 0x0 0x4000>;
275 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
276 clock-freq-min-max = <400000 150000000>;
277 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
278 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
279 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
280 fifo-depth = <0x100>;
284 sdmmc: dwmmc@fe320000 {
285 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
286 reg = <0x0 0xfe320000 0x0 0x4000>;
287 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
288 clock-freq-min-max = <400000 150000000>;
289 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
290 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
291 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
292 fifo-depth = <0x100>;
296 sdhci: sdhci@fe330000 {
297 compatible = "arasan,sdhci-5.1";
298 reg = <0x0 0xfe330000 0x0 0x10000>;
299 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
301 clock-names = "clk_xin", "clk_ahb";
303 phy-names = "phy_arasan";
307 usb_host0_echi: usb@fe380000 {
308 compatible = "generic-ehci";
309 reg = <0x0 0xfe380000 0x0 0x20000>;
310 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&cru HCLK_HOST0>;
312 clock-names = "hclk_host0";
316 usb_host0_ohci: usb@fe3a0000 {
317 compatible = "generic-ohci";
318 reg = <0x0 0xfe3a0000 0x0 0x20000>;
319 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&cru HCLK_HOST0>;
321 clock-names = "hclk_host0";
325 usb_host1_echi: usb@fe3c0000 {
326 compatible = "generic-ehci";
327 reg = <0x0 0xfe3c0000 0x0 0x20000>;
328 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&cru HCLK_HOST1>;
330 clock-names = "hclk_host1";
334 usb_host1_ohci: usb@fe3e0000 {
335 compatible = "generic-ohci";
336 reg = <0x0 0xfe3e0000 0x0 0x20000>;
337 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cru HCLK_HOST1>;
339 clock-names = "hclk_host1";
343 gic: interrupt-controller@fee00000 {
344 compatible = "arm,gic-v3";
345 #interrupt-cells = <3>;
346 #address-cells = <2>;
349 interrupt-controller;
351 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
352 <0x0 0xfef00000 0 0xc0000>, /* GICR */
353 <0x0 0xfff00000 0 0x10000>, /* GICC */
354 <0x0 0xfff10000 0 0x10000>, /* GICH */
355 <0x0 0xfff20000 0 0x10000>; /* GICV */
356 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
357 its: interrupt-controller@fee20000 {
358 compatible = "arm,gic-v3-its";
360 reg = <0x0 0xfee20000 0x0 0x20000>;
364 saradc: saradc@ff100000 {
365 compatible = "rockchip,rk3399-saradc";
366 reg = <0x0 0xff100000 0x0 0x100>;
367 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
368 #io-channel-cells = <1>;
369 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
370 clock-names = "saradc", "apb_pclk";
375 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
376 reg = <0x0 0xff3c0000 0x0 0x1000>;
377 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
378 clock-names = "i2c", "i2c_sclk";
379 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c0_xfer>;
382 #address-cells = <1>;
388 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
389 reg = <0x0 0xff110000 0x0 0x1000>;
390 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
391 clock-names = "i2c", "i2c_sclk";
392 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c1_xfer>;
395 #address-cells = <1>;
401 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
402 reg = <0x0 0xff120000 0x0 0x1000>;
403 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
404 clock-names = "i2c", "i2c_sclk";
405 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c2_xfer>;
408 #address-cells = <1>;
414 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
415 reg = <0x0 0xff130000 0x0 0x1000>;
416 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
417 clock-names = "i2c", "i2c_sclk";
418 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2c3_xfer>;
421 #address-cells = <1>;
427 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
428 reg = <0x0 0xff140000 0x0 0x1000>;
429 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
430 clock-names = "i2c", "i2c_sclk";
431 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&i2c5_xfer>;
434 #address-cells = <1>;
440 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
441 reg = <0x0 0xff150000 0x0 0x1000>;
442 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
443 clock-names = "i2c", "i2c_sclk";
444 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&i2c6_xfer>;
447 #address-cells = <1>;
453 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
454 reg = <0x0 0xff160000 0x0 0x1000>;
455 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
456 clock-names = "i2c", "i2c_sclk";
457 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&i2c7_xfer>;
460 #address-cells = <1>;
465 uart0: serial@ff180000 {
466 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
467 reg = <0x0 0xff180000 0x0 0x100>;
468 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
469 clock-names = "baudclk", "apb_pclk";
470 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
476 uart1: serial@ff190000 {
477 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
478 reg = <0x0 0xff190000 0x0 0x100>;
479 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
480 clock-names = "baudclk", "apb_pclk";
481 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
487 uart2: serial@ff1a0000 {
488 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
489 reg = <0x0 0xff1a0000 0x0 0x100>;
490 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
491 clock-names = "baudclk", "apb_pclk";
492 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
498 uart3: serial@ff1b0000 {
499 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
500 reg = <0x0 0xff1b0000 0x0 0x100>;
501 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
502 clock-names = "baudclk", "apb_pclk";
503 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
510 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
511 reg = <0x0 0xff1c0000 0x0 0x1000>;
512 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
513 clock-names = "spiclk", "apb_pclk";
514 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
517 #address-cells = <1>;
523 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
524 reg = <0x0 0xff1d0000 0x0 0x1000>;
525 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
526 clock-names = "spiclk", "apb_pclk";
527 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
530 #address-cells = <1>;
536 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
537 reg = <0x0 0xff1e0000 0x0 0x1000>;
538 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
539 clock-names = "spiclk", "apb_pclk";
540 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
543 #address-cells = <1>;
549 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
550 reg = <0x0 0xff1f0000 0x0 0x1000>;
551 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
552 clock-names = "spiclk", "apb_pclk";
553 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
556 #address-cells = <1>;
562 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
563 reg = <0x0 0xff200000 0x0 0x1000>;
564 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
565 clock-names = "spiclk", "apb_pclk";
566 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
569 #address-cells = <1>;
575 #include "rk3368-thermal.dtsi"
578 tsadc: tsadc@ff260000 {
579 compatible = "rockchip,rk3399-tsadc";
580 reg = <0x0 0xff260000 0x0 0x100>;
581 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
583 clock-names = "tsadc", "apb_pclk";
584 resets = <&cru SRST_TSADC>;
585 reset-names = "tsadc-apb";
586 pinctrl-names = "init", "default", "sleep";
587 pinctrl-0 = <&otp_gpio>;
588 pinctrl-1 = <&otp_out>;
589 pinctrl-2 = <&otp_gpio>;
590 #thermal-sensor-cells = <1>;
591 rockchip,hw-tshut-temp = <95000>;
595 pmu: power-management@ff31000 {
596 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
597 reg = <0x0 0xff310000 0x0 0x1000>;
599 power: power-controller {
601 compatible = "rockchip,rk3399-power-controller";
602 #power-domain-cells = <1>;
603 #address-cells = <1>;
607 reg = <RK3399_PD_CENTER>;
608 #address-cells = <1>;
612 reg = <RK3399_PD_VDU>;
615 reg = <RK3399_PD_VCODEC>;
618 reg = <RK3399_PD_IEP>;
621 reg = <RK3399_PD_RGA>;
625 reg = <RK3399_PD_VIO>;
626 #address-cells = <1>;
630 reg = <RK3399_PD_ISP0>;
633 reg = <RK3399_PD_ISP1>;
636 reg = <RK3399_PD_HDCP>;
639 reg = <RK3399_PD_VO>;
640 #address-cells = <1>;
644 reg = <RK3399_PD_VOPB>;
647 reg = <RK3399_PD_VOPL>;
652 reg = <RK3399_PD_GPU>;
657 pmugrf: syscon@ff320000 {
658 compatible = "rockchip,rk3399-pmugrf", "syscon";
659 reg = <0x0 0xff320000 0x0 0x1000>;
663 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
664 reg = <0x0 0xff350000 0x0 0x1000>;
665 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
666 clock-names = "spiclk", "apb_pclk";
667 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
670 #address-cells = <1>;
675 uart4: serial@ff370000 {
676 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
677 reg = <0x0 0xff370000 0x0 0x100>;
678 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
679 clock-names = "baudclk", "apb_pclk";
680 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
687 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
688 reg = <0x0 0xff3d0000 0x0 0x1000>;
689 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
690 clock-names = "i2c", "i2c_sclk";
691 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
692 pinctrl-names = "default";
693 pinctrl-0 = <&i2c4_xfer>;
694 #address-cells = <1>;
700 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
701 reg = <0x0 0xff3e0000 0x0 0x1000>;
702 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
703 clock-names = "i2c", "i2c_sclk";
704 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
705 pinctrl-names = "default";
706 pinctrl-0 = <&i2c8_xfer>;
707 #address-cells = <1>;
713 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
714 reg = <0x0 0xff420000 0x0 0x10>;
716 pinctrl-names = "default";
717 pinctrl-0 = <&pwm0_pin>;
718 clocks = <&cru PCLK_RKPWM_PMU>;
724 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
725 reg = <0x0 0xff420010 0x0 0x10>;
727 pinctrl-names = "default";
728 pinctrl-0 = <&pwm1_pin>;
729 clocks = <&cru PCLK_RKPWM_PMU>;
735 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
736 reg = <0x0 0xff420020 0x0 0x10>;
738 pinctrl-names = "default";
739 pinctrl-0 = <&pwm2_pin>;
740 clocks = <&cru PCLK_RKPWM_PMU>;
746 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
747 reg = <0x0 0xff420030 0x0 0x10>;
749 pinctrl-names = "default";
750 pinctrl-0 = <&pwm3a_pin>;
751 clocks = <&cru PCLK_RKPWM_PMU>;
756 pmucru: pmu-clock-controller@ff750000 {
757 compatible = "rockchip,rk3399-pmucru";
758 reg = <0x0 0xff750000 0x0 0x1000>;
759 rockchip,grf = <&pmugrf>;
764 cru: clock-controller@ff760000 {
765 compatible = "rockchip,rk3399-cru";
766 reg = <0x0 0xff760000 0x0 0x1000>;
767 rockchip,grf = <&grf>;
772 grf: syscon@ff770000 {
773 compatible = "rockchip,rk3399-grf", "syscon";
774 reg = <0x0 0xff770000 0x0 0x10000>;
777 wdt0: watchdog@ff840000 {
778 compatible = "snps,dw-wdt";
779 reg = <0x0 0xff840000 0x0 0x100>;
780 clocks = <&cru PCLK_WDT>;
781 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
785 spdif: spdif@ff870000 {
786 compatible = "rockchip,rk3399-spdif";
787 reg = <0x0 0xff870000 0x0 0x1000>;
788 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
789 dmas = <&dmac_bus 7>;
791 clock-names = "hclk", "mclk";
792 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
793 pinctrl-names = "default";
794 pinctrl-0 = <&spdif_bus>;
799 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
800 reg = <0x0 0xff880000 0x0 0x1000>;
801 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
802 #address-cells = <1>;
804 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
805 dma-names = "tx", "rx";
806 clock-names = "i2s_hclk", "i2s_clk";
807 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
808 pinctrl-names = "default";
809 pinctrl-0 = <&i2s0_8ch_bus>;
814 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
815 reg = <0x0 0xff890000 0x0 0x1000>;
816 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
817 #address-cells = <1>;
819 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
820 dma-names = "tx", "rx";
821 clock-names = "i2s_hclk", "i2s_clk";
822 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
823 pinctrl-names = "default";
824 pinctrl-0 = <&i2s1_2ch_bus>;
829 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
830 reg = <0x0 0xff8a0000 0x0 0x1000>;
831 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
832 #address-cells = <1>;
834 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
835 dma-names = "tx", "rx";
836 clock-names = "i2s_hclk", "i2s_clk";
837 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
842 compatible = "rockchip,rk3399-pinctrl";
843 rockchip,grf = <&grf>;
844 rockchip,pmu = <&pmugrf>;
845 #address-cells = <0x2>;
849 gpio0: gpio0@ff720000 {
850 compatible = "rockchip,gpio-bank";
851 reg = <0x0 0xff720000 0x0 0x100>;
853 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
858 interrupt-controller;
859 #interrupt-cells = <0x2>;
862 gpio1: gpio1@ff730000 {
863 compatible = "rockchip,gpio-bank";
864 reg = <0x0 0xff730000 0x0 0x100>;
866 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
871 interrupt-controller;
872 #interrupt-cells = <0x2>;
875 gpio2: gpio2@ff780000 {
876 compatible = "rockchip,gpio-bank";
877 reg = <0x0 0xff780000 0x0 0x100>;
879 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
884 interrupt-controller;
885 #interrupt-cells = <0x2>;
888 gpio3: gpio3@ff788000 {
889 compatible = "rockchip,gpio-bank";
890 reg = <0x0 0xff788000 0x0 0x100>;
892 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
897 interrupt-controller;
898 #interrupt-cells = <0x2>;
901 gpio4: gpio4@ff790000 {
902 compatible = "rockchip,gpio-bank";
903 reg = <0x0 0xff790000 0x0 0x100>;
905 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
910 interrupt-controller;
911 #interrupt-cells = <0x2>;
914 pcfg_pull_up: pcfg-pull-up {
918 pcfg_pull_down: pcfg-pull-down {
922 pcfg_pull_none: pcfg-pull-none {
926 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
928 drive-strength = <12>;
931 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
933 drive-strength = <8>;
936 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
938 drive-strength = <4>;
941 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
943 drive-strength = <2>;
946 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
948 drive-strength = <12>;
954 <0 5 RK_FUNC_1 &pcfg_pull_up>;
959 rgmii_pins: rgmii-pins {
961 <3 11 RK_FUNC_1 &pcfg_pull_none>,
962 <3 13 RK_FUNC_1 &pcfg_pull_none>,
963 <3 8 RK_FUNC_1 &pcfg_pull_none>,
964 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
965 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
966 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
967 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
968 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
969 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
970 <3 6 RK_FUNC_1 &pcfg_pull_none>,
971 <3 7 RK_FUNC_1 &pcfg_pull_none>,
972 <3 2 RK_FUNC_1 &pcfg_pull_none>,
973 <3 3 RK_FUNC_1 &pcfg_pull_none>,
974 <3 14 RK_FUNC_1 &pcfg_pull_none>,
975 <3 9 RK_FUNC_1 &pcfg_pull_none>;
978 rmii_pins: rmii-pins {
980 <3 11 RK_FUNC_1 &pcfg_pull_none>,
981 <3 13 RK_FUNC_1 &pcfg_pull_none>,
982 <3 8 RK_FUNC_1 &pcfg_pull_none>,
983 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
984 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
985 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
986 <3 6 RK_FUNC_1 &pcfg_pull_none>,
987 <3 7 RK_FUNC_1 &pcfg_pull_none>,
988 <3 9 RK_FUNC_1 &pcfg_pull_none>,
989 <3 10 RK_FUNC_1 &pcfg_pull_none>;
994 i2c0_xfer: i2c0-xfer {
996 <1 15 RK_FUNC_2 &pcfg_pull_none>,
997 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1002 i2c1_xfer: i2c1-xfer {
1004 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1005 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1010 i2c2_xfer: i2c2-xfer {
1012 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1013 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1018 i2c3_xfer: i2c3-xfer {
1020 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1021 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1026 i2c4_xfer: i2c4-xfer {
1028 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1029 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1034 i2c5_xfer: i2c5-xfer {
1036 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1037 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1042 i2c6_xfer: i2c6-xfer {
1044 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1045 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1050 i2c7_xfer: i2c7-xfer {
1052 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1053 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1058 i2c8_xfer: i2c8-xfer {
1060 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1061 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1066 i2s0_8ch_bus: i2s0-8ch-bus {
1068 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1069 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1070 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1071 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1072 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1073 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1074 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1075 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1076 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1081 i2s1_2ch_bus: i2s1-2ch-bus {
1083 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1084 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1085 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1086 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1087 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1092 sdio0_bus1: sdio0-bus1 {
1094 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1097 sdio0_bus4: sdio0-bus4 {
1099 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1100 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1101 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1102 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1105 sdio0_cmd: sdio0-cmd {
1107 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1110 sdio0_clk: sdio0-clk {
1112 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1115 sdio0_cd: sdio0-cd {
1117 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1120 sdio0_pwr: sdio0-pwr {
1122 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1125 sdio0_bkpwr: sdio0-bkpwr {
1127 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1130 sdio0_wp: sdio0-wp {
1132 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1135 sdio0_int: sdio0-int {
1137 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1142 sdmmc_bus1: sdmmc-bus1 {
1144 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1147 sdmmc_bus4: sdmmc-bus4 {
1149 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1150 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1151 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1152 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1155 sdmmc_clk: sdmmc-clk {
1157 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1160 sdmmc_cmd: sdmmc-cmd {
1162 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1165 sdmmc_cd: sdmcc-cd {
1167 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1170 sdmmc_wp: sdmmc-wp {
1172 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1177 spdif_bus: spdif-bus {
1179 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1184 spi0_clk: spi0-clk {
1186 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1188 spi0_cs0: spi0-cs0 {
1190 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1192 spi0_cs1: spi0-cs1 {
1194 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1198 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1202 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1207 spi1_clk: spi1-clk {
1209 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1211 spi1_cs0: spi1-cs0 {
1213 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1217 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1221 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1226 spi2_clk: spi2-clk {
1228 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1230 spi2_cs0: spi2-cs0 {
1232 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1236 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1240 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1245 spi3_clk: spi3-clk {
1247 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1249 spi3_cs0: spi3-cs0 {
1251 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1255 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1259 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1264 spi4_clk: spi4-clk {
1266 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1268 spi4_cs0: spi4-cs0 {
1270 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1274 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1278 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1283 spi5_clk: spi5-clk {
1285 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1287 spi5_cs0: spi5-cs0 {
1289 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1293 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1297 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1302 otp_gpio: otp-gpio {
1303 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1307 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1312 uart0_xfer: uart0-xfer {
1314 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1315 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1318 uart0_cts: uart0-cts {
1320 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1323 uart0_rts: uart0-rts {
1325 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1330 uart1_xfer: uart1-xfer {
1332 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1333 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1338 uart2a_xfer: uart2a-xfer {
1340 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1341 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1346 uart2b_xfer: uart2b-xfer {
1348 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1349 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1354 uart2c_xfer: uart2c-xfer {
1356 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1357 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1362 uart3_xfer: uart3-xfer {
1364 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1365 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1368 uart3_cts: uart3-cts {
1370 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1373 uart3_rts: uart3-rts {
1375 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1380 uart4_xfer: uart4-xfer {
1382 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1383 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1388 uarthdcp_xfer: uarthdcp-xfer {
1390 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1391 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1396 pwm0_pin: pwm0-pin {
1398 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1401 vop0_pwm_pin: vop0-pwm-pin {
1403 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1408 pwm1_pin: pwm1-pin {
1410 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1413 vop1_pwm_pin: vop1-pwm-pin {
1415 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1420 pwm2_pin: pwm2-pin {
1422 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1427 pwm3a_pin: pwm3a-pin {
1429 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1434 pwm3b_pin: pwm3b-pin {
1436 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1441 pmic_int_l: pmic-int-l {
1443 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;