arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         operating-points-v2 = <&cluster0_opp>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         operating-points-v2 = <&cluster0_opp>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164         };
 165
 166         cluster0_opp: opp_table0 {
 167                 compatible = "operating-points-v2";
 168                 opp-shared;
 169
 170                 opp00 {
 171                         opp-hz = /bits/ 64 <408000000>;
 172                         opp-microvolt = <900000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp01 {
 176                         opp-hz = /bits/ 64 <600000000>;
 177                         opp-microvolt = <900000>;
 178                 };
 179                 opp02 {
 180                         opp-hz = /bits/ 64 <816000000>;
 181                         opp-microvolt = <900000>;
 182                 };
 183                 opp03 {
 184                         opp-hz = /bits/ 64 <1008000000>;
 185                         opp-microvolt = <900000>;
 186                 };
 187         };
 188
 189         cluster1_opp: opp_table1 {
 190                 compatible = "operating-points-v2";
 191                 opp-shared;
 192
 193                 opp00 {
 194                         opp-hz = /bits/ 64 <408000000>;
 195                         opp-microvolt = <900000>;
 196                         clock-latency-ns = <40000>;
 197                 };
 198                 opp01 {
 199                         opp-hz = /bits/ 64 <600000000>;
 200                         opp-microvolt = <900000>;
 201                 };
 202                 opp02 {
 203                         opp-hz = /bits/ 64 <816000000>;
 204                         opp-microvolt = <900000>;
 205                 };
 206                 opp03 {
 207                         opp-hz = /bits/ 64 <1008000000>;
 208                         opp-microvolt = <900000>;
 209                 };
 210                 opp04 {
 211                         opp-hz = /bits/ 64 <1200000000>;
 212                         opp-microvolt = <900000>;
 213                 };
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 222         };
 223
 224         arm-pmu {
 225                 compatible = "arm,armv8-pmuv3";
 226                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 227         };
 228
 229         xin24m: xin24m {
 230                 compatible = "fixed-clock";
 231                 #clock-cells = <0>;
 232                 clock-frequency = <24000000>;
 233                 clock-output-names = "xin24m";
 234         };
 235
 236         amba {
 237                 compatible = "arm,amba-bus";
 238                 #address-cells = <2>;
 239                 #size-cells = <2>;
 240                 ranges;
 241
 242                 dmac_bus: dma-controller@ff6d0000 {
 243                         compatible = "arm,pl330", "arm,primecell";
 244                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 245                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 247                         #dma-cells = <1>;
 248                         clocks = <&cru ACLK_DMAC0_PERILP>;
 249                         clock-names = "apb_pclk";
 250                 };
 251
 252                 dmac_peri: dma-controller@ff6e0000 {
 253                         compatible = "arm,pl330", "arm,primecell";
 254                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 255                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 256                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 257                         #dma-cells = <1>;
 258                         clocks = <&cru ACLK_DMAC1_PERILP>;
 259                         clock-names = "apb_pclk";
 260                 };
 261         };
 262
 263         gmac: eth@fe300000 {
 264                 compatible = "rockchip,rk3399-gmac";
 265                 reg = <0x0 0xfe300000 0x0 0x10000>;
 266                 rockchip,grf = <&grf>;
 267                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 268                 interrupt-names = "macirq";
 269                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 270                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 271                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 272                          <&cru PCLK_GMAC>;
 273                 clock-names = "stmmaceth", "mac_clk_rx",
 274                               "mac_clk_tx", "clk_mac_ref",
 275                               "clk_mac_refout", "aclk_mac",
 276                               "pclk_mac";
 277                 resets = <&cru SRST_A_GMAC>;
 278                 reset-names = "stmmaceth";
 279                 status = "disabled";
 280         };
 281
 282         emmc_phy: phy {
 283                 compatible = "rockchip,rk3399-emmc-phy";
 284                 reg-offset = <0xf780>;
 285                 #phy-cells = <0>;
 286                 rockchip,grf = <&grf>;
 287                 status = "disabled";
 288         };
 289
 290         sdio0: dwmmc@fe310000 {
 291                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 292                 reg = <0x0 0xfe310000 0x0 0x4000>;
 293                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 294                 clock-freq-min-max = <400000 150000000>;
 295                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 296                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 297                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 298                 fifo-depth = <0x100>;
 299                 status = "disabled";
 300         };
 301
 302         sdmmc: dwmmc@fe320000 {
 303                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 304                 reg = <0x0 0xfe320000 0x0 0x4000>;
 305                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 306                 clock-freq-min-max = <400000 150000000>;
 307                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 308                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 309                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 310                 fifo-depth = <0x100>;
 311                 status = "disabled";
 312         };
 313
 314         sdhci: sdhci@fe330000 {
 315                 compatible = "arasan,sdhci-5.1";
 316                 reg = <0x0 0xfe330000 0x0 0x10000>;
 317                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 319                 clock-names = "clk_xin", "clk_ahb";
 320                 phys = <&emmc_phy>;
 321                 phy-names = "phy_arasan";
 322                 status = "disabled";
 323         };
 324
 325         usb2phy: usb2phy {
 326                 compatible = "rockchip,rk3399-usb-phy";
 327                 rockchip,grf = <&grf>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330
 331                 usb2phy0: usb2-phy0 {
 332                         #phy-cells = <0>;
 333                         #clock-cells = <0>;
 334                         reg = <0xe458>;
 335                 };
 336
 337                 usb2phy1: usb2-phy1 {
 338                         #phy-cells = <0>;
 339                         #clock-cells = <0>;
 340                         reg = <0xe468>;
 341                 };
 342         };
 343
 344         usb_host0_echi: usb@fe380000 {
 345                 compatible = "generic-ehci";
 346                 reg = <0x0 0xfe380000 0x0 0x20000>;
 347                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 349                 clock-names = "hclk_host0", "hclk_host0_arb";
 350                 phys = <&usb2phy0>;
 351                 phy-names = "usb2_phy0";
 352                 status = "disabled";
 353         };
 354
 355         usb_host0_ohci: usb@fe3a0000 {
 356                 compatible = "generic-ohci";
 357                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 358                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 359                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 360                 clock-names = "hclk_host0", "hclk_host0_arb";
 361                 status = "disabled";
 362         };
 363
 364         usb_host1_echi: usb@fe3c0000 {
 365                 compatible = "generic-ehci";
 366                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 367                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 368                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 369                 clock-names = "hclk_host1", "hclk_host1_arb";
 370                 phys = <&usb2phy1>;
 371                 phy-names = "usb2_phy1";
 372                 status = "disabled";
 373         };
 374
 375         usb_host1_ohci: usb@fe3e0000 {
 376                 compatible = "generic-ohci";
 377                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 378                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 379                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 380                 clock-names = "hclk_host1", "hclk_host1_arb";
 381                 status = "disabled";
 382         };
 383
 384         usbdrd3_0: usb@fe800000 {
 385                 compatible = "rockchip,dwc3";
 386                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 387                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 388                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 389                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 390                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 391                               "aclk_usb3", "aclk_usb3_grf";
 392                 #address-cells = <2>;
 393                 #size-cells = <2>;
 394                 ranges;
 395                 status = "disabled";
 396                 usbdrd_dwc3_0: dwc3 {
 397                         compatible = "snps,dwc3";
 398                         reg = <0x0 0xfe800000 0x0 0x100000>;
 399                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 400                         dr_mode = "otg";
 401                         tx-fifo-resize;
 402                         snps,dis_enblslpm_quirk;
 403                         snps,phyif_utmi_16_bits;
 404                         snps,dis_u2_freeclk_exists_quirk;
 405                         snps,dis_del_phy_power_chg_quirk;
 406                         status = "disabled";
 407                 };
 408         };
 409
 410         usbdrd3_1: usb@fe900000 {
 411                 compatible = "rockchip,dwc3";
 412                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 413                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 414                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 415                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 416                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 417                               "aclk_usb3", "aclk_usb3_grf";
 418                 #address-cells = <2>;
 419                 #size-cells = <2>;
 420                 ranges;
 421                 status = "disabled";
 422                 usbdrd_dwc3_1: dwc3 {
 423                         compatible = "snps,dwc3";
 424                         reg = <0x0 0xfe900000 0x0 0x100000>;
 425                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 426                         dr_mode = "otg";
 427                         tx-fifo-resize;
 428                         snps,dis_enblslpm_quirk;
 429                         snps,phyif_utmi_16_bits;
 430                         snps,dis_u2_freeclk_exists_quirk;
 431                         snps,dis_del_phy_power_chg_quirk;
 432                         status = "disabled";
 433                 };
 434         };
 435
 436         gic: interrupt-controller@fee00000 {
 437                 compatible = "arm,gic-v3";
 438                 #interrupt-cells = <3>;
 439                 #address-cells = <2>;
 440                 #size-cells = <2>;
 441                 ranges;
 442                 interrupt-controller;
 443
 444                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 445                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 446                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 447                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 448                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 449                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 450                 its: interrupt-controller@fee20000 {
 451                         compatible = "arm,gic-v3-its";
 452                         msi-controller;
 453                         reg = <0x0 0xfee20000 0x0 0x20000>;
 454                 };
 455         };
 456
 457         saradc: saradc@ff100000 {
 458                 compatible = "rockchip,rk3399-saradc";
 459                 reg = <0x0 0xff100000 0x0 0x100>;
 460                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 461                 #io-channel-cells = <1>;
 462                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 463                 clock-names = "saradc", "apb_pclk";
 464                 status = "disabled";
 465         };
 466
 467         i2c0: i2c@ff3c0000 {
 468                 compatible = "rockchip,rk3399-i2c";
 469                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 470                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 471                 clock-names = "i2c", "pclk";
 472                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&i2c0_xfer>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 status = "disabled";
 478         };
 479
 480         i2c1: i2c@ff110000 {
 481                 compatible = "rockchip,rk3399-i2c";
 482                 reg = <0x0 0xff110000 0x0 0x1000>;
 483                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 484                 clock-names = "i2c", "pclk";
 485                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&i2c1_xfer>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 status = "disabled";
 491         };
 492
 493         i2c2: i2c@ff120000 {
 494                 compatible = "rockchip,rk3399-i2c";
 495                 reg = <0x0 0xff120000 0x0 0x1000>;
 496                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 497                 clock-names = "i2c", "pclk";
 498                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c2_xfer>;
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503                 status = "disabled";
 504         };
 505
 506         i2c3: i2c@ff130000 {
 507                 compatible = "rockchip,rk3399-i2c";
 508                 reg = <0x0 0xff130000 0x0 0x1000>;
 509                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 510                 clock-names = "i2c", "pclk";
 511                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2c3_xfer>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 status = "disabled";
 517         };
 518
 519         i2c5: i2c@ff140000 {
 520                 compatible = "rockchip,rk3399-i2c";
 521                 reg = <0x0 0xff140000 0x0 0x1000>;
 522                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 523                 clock-names = "i2c", "pclk";
 524                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 525                 pinctrl-names = "default";
 526                 pinctrl-0 = <&i2c5_xfer>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 status = "disabled";
 530         };
 531
 532         i2c6: i2c@ff150000 {
 533                 compatible = "rockchip,rk3399-i2c";
 534                 reg = <0x0 0xff150000 0x0 0x1000>;
 535                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 536                 clock-names = "i2c", "pclk";
 537                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&i2c6_xfer>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 status = "disabled";
 543         };
 544
 545         i2c7: i2c@ff160000 {
 546                 compatible = "rockchip,rk3399-i2c";
 547                 reg = <0x0 0xff160000 0x0 0x1000>;
 548                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 549                 clock-names = "i2c", "pclk";
 550                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&i2c7_xfer>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         uart0: serial@ff180000 {
 559                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 560                 reg = <0x0 0xff180000 0x0 0x100>;
 561                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 562                 clock-names = "baudclk", "apb_pclk";
 563                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 564                 reg-shift = <2>;
 565                 reg-io-width = <4>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 568                 status = "disabled";
 569         };
 570
 571         uart1: serial@ff190000 {
 572                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 573                 reg = <0x0 0xff190000 0x0 0x100>;
 574                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 575                 clock-names = "baudclk", "apb_pclk";
 576                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 577                 reg-shift = <2>;
 578                 reg-io-width = <4>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&uart1_xfer>;
 581                 status = "disabled";
 582         };
 583
 584         uart2: serial@ff1a0000 {
 585                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 586                 reg = <0x0 0xff1a0000 0x0 0x100>;
 587                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 588                 clock-names = "baudclk", "apb_pclk";
 589                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 590                 reg-shift = <2>;
 591                 reg-io-width = <4>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&uart2c_xfer>;
 594                 status = "disabled";
 595         };
 596
 597         uart3: serial@ff1b0000 {
 598                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 599                 reg = <0x0 0xff1b0000 0x0 0x100>;
 600                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 601                 clock-names = "baudclk", "apb_pclk";
 602                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 603                 reg-shift = <2>;
 604                 reg-io-width = <4>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 607                 status = "disabled";
 608         };
 609
 610         spi0: spi@ff1c0000 {
 611                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 612                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 613                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 614                 clock-names = "spiclk", "apb_pclk";
 615                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 status = "disabled";
 621         };
 622
 623         spi1: spi@ff1d0000 {
 624                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 625                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 626                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 627                 clock-names = "spiclk", "apb_pclk";
 628                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 629                 pinctrl-names = "default";
 630                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 status = "disabled";
 634         };
 635
 636         spi2: spi@ff1e0000 {
 637                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 638                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 639                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 640                 clock-names = "spiclk", "apb_pclk";
 641                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 642                 pinctrl-names = "default";
 643                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 644                 #address-cells = <1>;
 645                 #size-cells = <0>;
 646                 status = "disabled";
 647         };
 648
 649         spi4: spi@ff1f0000 {
 650                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 651                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 652                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 653                 clock-names = "spiclk", "apb_pclk";
 654                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 657                 #address-cells = <1>;
 658                 #size-cells = <0>;
 659                 status = "disabled";
 660         };
 661
 662         spi5: spi@ff200000 {
 663                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 664                 reg = <0x0 0xff200000 0x0 0x1000>;
 665                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 666                 clock-names = "spiclk", "apb_pclk";
 667                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 status = "disabled";
 673         };
 674
 675         thermal-zones {
 676                 cpu {
 677                         polling-delay-passive = <100>; /* milliseconds */
 678                         polling-delay = <1000>; /* milliseconds */
 679
 680                         thermal-sensors = <&tsadc 0>;
 681
 682                         trips {
 683                                 cpu_alert0: cpu_alert0 {
 684                                         temperature = <70000>; /* millicelsius */
 685                                         hysteresis = <2000>; /* millicelsius */
 686                                         type = "passive";
 687                                 };
 688                                 cpu_alert1: cpu_alert1 {
 689                                         temperature = <75000>; /* millicelsius */
 690                                         hysteresis = <2000>; /* millicelsius */
 691                                         type = "passive";
 692                                 };
 693                                 cpu_crit: cpu_crit {
 694                                         temperature = <95000>; /* millicelsius */
 695                                         hysteresis = <2000>; /* millicelsius */
 696                                         type = "critical";
 697                                 };
 698                         };
 699
 700                         cooling-maps {
 701                                 map0 {
 702                                         trip = <&cpu_alert0>;
 703                                         cooling-device =
 704                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 705                                 };
 706                                 map1 {
 707                                         trip = <&cpu_alert1>;
 708                                         cooling-device =
 709                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 710                                 };
 711                         };
 712                 };
 713
 714                 gpu {
 715                         polling-delay-passive = <100>; /* milliseconds */
 716                         polling-delay = <1000>; /* milliseconds */
 717
 718                         thermal-sensors = <&tsadc 1>;
 719
 720                         trips {
 721                                 gpu_alert0: gpu_alert0 {
 722                                         temperature = <75000>; /* millicelsius */
 723                                         hysteresis = <2000>; /* millicelsius */
 724                                         type = "passive";
 725                                 };
 726                                 gpu_crit: gpu_crit {
 727                                         temperature = <950000>; /* millicelsius */
 728                                         hysteresis = <2000>; /* millicelsius */
 729                                         type = "critical";
 730                                 };
 731                         };
 732
 733                         cooling-maps {
 734                                 map0 {
 735                                         trip = <&gpu_alert0>;
 736                                         cooling-device =
 737                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 738                                 };
 739                         };
 740                 };
 741         };
 742
 743         tsadc: tsadc@ff260000 {
 744                 compatible = "rockchip,rk3399-tsadc";
 745                 reg = <0x0 0xff260000 0x0 0x100>;
 746                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 747                 rockchip,grf = <&grf>;
 748                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 749                 clock-names = "tsadc", "apb_pclk";
 750                 assigned-clocks = <&cru SCLK_TSADC>;
 751                 assigned-clock-rates = <750000>;
 752                 resets = <&cru SRST_TSADC>;
 753                 reset-names = "tsadc-apb";
 754                 pinctrl-names = "init", "default", "sleep";
 755                 pinctrl-0 = <&otp_gpio>;
 756                 pinctrl-1 = <&otp_out>;
 757                 pinctrl-2 = <&otp_gpio>;
 758                 #thermal-sensor-cells = <1>;
 759                 rockchip,hw-tshut-temp = <95000>;
 760                 status = "disabled";
 761         };
 762
 763         pmu: power-management@ff31000 {
 764                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 765                 reg = <0x0 0xff310000 0x0 0x1000>;
 766
 767                 power: power-controller {
 768                         status = "disabled";
 769                         compatible = "rockchip,rk3399-power-controller";
 770                         #power-domain-cells = <1>;
 771                         #address-cells = <1>;
 772                         #size-cells = <0>;
 773
 774                         pd_center {
 775                                 reg = <RK3399_PD_CENTER>;
 776                                 #address-cells = <1>;
 777                                 #size-cells = <0>;
 778
 779                                 pd_vdu {
 780                                         reg = <RK3399_PD_VDU>;
 781                                 };
 782                                 pd_vcodec {
 783                                         reg = <RK3399_PD_VCODEC>;
 784                                 };
 785                                 pd_iep {
 786                                         reg = <RK3399_PD_IEP>;
 787                                 };
 788                                 pd_rga {
 789                                         reg = <RK3399_PD_RGA>;
 790                                 };
 791                         };
 792                         pd_vio {
 793                                 reg = <RK3399_PD_VIO>;
 794                                 #address-cells = <1>;
 795                                 #size-cells = <0>;
 796
 797                                 pd_isp0 {
 798                                         reg = <RK3399_PD_ISP0>;
 799                                 };
 800                                 pd_isp1 {
 801                                         reg = <RK3399_PD_ISP1>;
 802                                 };
 803                                 pd_hdcp {
 804                                         reg = <RK3399_PD_HDCP>;
 805                                 };
 806                                 pd_vo {
 807                                         reg = <RK3399_PD_VO>;
 808                                         #address-cells = <1>;
 809                                         #size-cells = <0>;
 810
 811                                         pd_vopb {
 812                                                 reg = <RK3399_PD_VOPB>;
 813                                         };
 814                                         pd_vopl {
 815                                                 reg = <RK3399_PD_VOPL>;
 816                                         };
 817                                 };
 818                         };
 819                         pd_gpu {
 820                                 reg = <RK3399_PD_GPU>;
 821                         };
 822                 };
 823         };
 824
 825         pmugrf: syscon@ff320000 {
 826                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 827                 reg = <0x0 0xff320000 0x0 0x1000>;
 828         };
 829
 830         spi3: spi@ff350000 {
 831                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 832                 reg = <0x0 0xff350000 0x0 0x1000>;
 833                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 834                 clock-names = "spiclk", "apb_pclk";
 835                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 836                 pinctrl-names = "default";
 837                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 838                 #address-cells = <1>;
 839                 #size-cells = <0>;
 840                 status = "disabled";
 841         };
 842
 843         uart4: serial@ff370000 {
 844                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 845                 reg = <0x0 0xff370000 0x0 0x100>;
 846                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 847                 clock-names = "baudclk", "apb_pclk";
 848                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 849                 reg-shift = <2>;
 850                 reg-io-width = <4>;
 851                 pinctrl-names = "default";
 852                 pinctrl-0 = <&uart4_xfer>;
 853                 status = "disabled";
 854         };
 855
 856         i2c4: i2c@ff3d0000 {
 857                 compatible = "rockchip,rk3399-i2c";
 858                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 859                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 860                 clock-names = "i2c", "pclk";
 861                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 862                 pinctrl-names = "default";
 863                 pinctrl-0 = <&i2c4_xfer>;
 864                 #address-cells = <1>;
 865                 #size-cells = <0>;
 866                 status = "disabled";
 867         };
 868
 869         i2c8: i2c@ff3e0000 {
 870                 compatible = "rockchip,rk3399-i2c";
 871                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 872                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 873                 clock-names = "i2c", "pclk";
 874                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 875                 pinctrl-names = "default";
 876                 pinctrl-0 = <&i2c8_xfer>;
 877                 #address-cells = <1>;
 878                 #size-cells = <0>;
 879                 status = "disabled";
 880         };
 881
 882         pwm0: pwm@ff420000 {
 883                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 884                 reg = <0x0 0xff420000 0x0 0x10>;
 885                 #pwm-cells = <3>;
 886                 pinctrl-names = "default";
 887                 pinctrl-0 = <&pwm0_pin>;
 888                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 889                 clock-names = "pwm";
 890                 status = "disabled";
 891         };
 892
 893         pwm1: pwm@ff420010 {
 894                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 895                 reg = <0x0 0xff420010 0x0 0x10>;
 896                 #pwm-cells = <3>;
 897                 pinctrl-names = "default";
 898                 pinctrl-0 = <&pwm1_pin>;
 899                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 900                 clock-names = "pwm";
 901                 status = "disabled";
 902         };
 903
 904         pwm2: pwm@ff420020 {
 905                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 906                 reg = <0x0 0xff420020 0x0 0x10>;
 907                 #pwm-cells = <3>;
 908                 pinctrl-names = "default";
 909                 pinctrl-0 = <&pwm2_pin>;
 910                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 911                 clock-names = "pwm";
 912                 status = "disabled";
 913         };
 914
 915         pwm3: pwm@ff420030 {
 916                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 917                 reg = <0x0 0xff420030 0x0 0x10>;
 918                 #pwm-cells = <3>;
 919                 pinctrl-names = "default";
 920                 pinctrl-0 = <&pwm3a_pin>;
 921                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 922                 clock-names = "pwm";
 923                 status = "disabled";
 924         };
 925
 926         pmucru: pmu-clock-controller@ff750000 {
 927                 compatible = "rockchip,rk3399-pmucru";
 928                 reg = <0x0 0xff750000 0x0 0x1000>;
 929                 #clock-cells = <1>;
 930                 #reset-cells = <1>;
 931                 assigned-clocks = <&pmucru PLL_PPLL>;
 932                 assigned-clock-rates = <676000000>;
 933         };
 934
 935         cru: clock-controller@ff760000 {
 936                 compatible = "rockchip,rk3399-cru";
 937                 reg = <0x0 0xff760000 0x0 0x1000>;
 938                 #clock-cells = <1>;
 939                 #reset-cells = <1>;
 940                 assigned-clocks =
 941                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
 942                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
 943                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 944                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 945                         <&cru PLL_NPLL>,
 946                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 947                         <&cru PCLK_PERIHP>,
 948                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 949                         <&cru PCLK_PERILP0>,
 950                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 951                 assigned-clock-rates =
 952                          <400000000>,  <200000000>,
 953                          <400000000>,  <200000000>,
 954                          <816000000>, <1008000000>,
 955                          <594000000>,  <800000000>,
 956                         <1000000000>,
 957                          <150000000>,   <75000000>,
 958                           <37500000>,
 959                          <100000000>,  <100000000>,
 960                           <50000000>,
 961                          <100000000>,   <50000000>;
 962         };
 963
 964         grf: syscon@ff770000 {
 965                 compatible = "rockchip,rk3399-grf", "syscon";
 966                 reg = <0x0 0xff770000 0x0 0x10000>;
 967         };
 968
 969         wdt0: watchdog@ff840000 {
 970                 compatible = "snps,dw-wdt";
 971                 reg = <0x0 0xff840000 0x0 0x100>;
 972                 clocks = <&cru PCLK_WDT>;
 973                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 974                 status = "disabled";
 975         };
 976
 977         spdif: spdif@ff870000 {
 978                 compatible = "rockchip,rk3399-spdif";
 979                 reg = <0x0 0xff870000 0x0 0x1000>;
 980                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 981                 dmas = <&dmac_bus 7>;
 982                 dma-names = "tx";
 983                 clock-names = "mclk", "hclk";
 984                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 985                 pinctrl-names = "default";
 986                 pinctrl-0 = <&spdif_bus>;
 987                 status = "disabled";
 988         };
 989
 990         i2s0: i2s@ff880000 {
 991                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 992                 reg = <0x0 0xff880000 0x0 0x1000>;
 993                 rockchip,grf = <&grf>;
 994                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 995                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 996                 dma-names = "tx", "rx";
 997                 clock-names = "i2s_clk", "i2s_hclk";
 998                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
 999                 pinctrl-names = "default";
1000                 pinctrl-0 = <&i2s0_8ch_bus>;
1001                 status = "disabled";
1002         };
1003
1004         i2s1: i2s@ff890000 {
1005                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1006                 reg = <0x0 0xff890000 0x0 0x1000>;
1007                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1008                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1009                 dma-names = "tx", "rx";
1010                 clock-names = "i2s_clk", "i2s_hclk";
1011                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1012                 pinctrl-names = "default";
1013                 pinctrl-0 = <&i2s1_2ch_bus>;
1014                 status = "disabled";
1015         };
1016
1017         i2s2: i2s@ff8a0000 {
1018                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1019                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1020                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1021                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1022                 dma-names = "tx", "rx";
1023                 clock-names = "i2s_clk", "i2s_hclk";
1024                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1025                 status = "disabled";
1026         };
1027
1028         gpu: gpu@ff9a0000 {
1029                 compatible = "arm,malit860",
1030                              "arm,malit86x",
1031                              "arm,malit8xx",
1032                              "arm,mali-midgard";
1033
1034                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1035
1036                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1037                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1038                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1039                 interrupt-names = "GPU", "JOB", "MMU";
1040
1041                 clocks = <&cru ACLK_GPU>;
1042                 clock-names = "clk_mali";
1043                 #cooling-cells = <2>; /* min followed by max */
1044                 operating-points-v2 = <&gpu_opp_table>;
1045                 status = "disabled";
1046         };
1047
1048         gpu_opp_table: gpu_opp_table {
1049                 compatible = "operating-points-v2";
1050                 opp-shared;
1051
1052                 opp00 {
1053                         opp-hz = /bits/ 64 <200000000>;
1054                         opp-microvolt = <900000>;
1055                 };
1056                 opp01 {
1057                         opp-hz = /bits/ 64 <300000000>;
1058                         opp-microvolt = <900000>;
1059                 };
1060                 opp02 {
1061                         opp-hz = /bits/ 64 <400000000>;
1062                         opp-microvolt = <900000>;
1063                 };
1064                 opp03 {
1065                         opp-hz = /bits/ 64 <500000000>;
1066                         opp-microvolt = <900000>;
1067                 };
1068         };
1069
1070         vopl: vop@ff8f0000 {
1071                 compatible = "rockchip,rk3399-vop-lit";
1072                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1073                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1074                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1075                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1076                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1077                 reset-names = "axi", "ahb", "dclk";
1078                 iommus = <&vopl_mmu>;
1079                 status = "disabled";
1080
1081                 vopl_out: port {
1082                         #address-cells = <1>;
1083                         #size-cells = <0>;
1084
1085                         vopl_out_mipi: endpoint@0 {
1086                                 reg = <0>;
1087                                 remote-endpoint = <&mipi_in_vopl>;
1088                         };
1089
1090                         vopl_out_edp: endpoint@1 {
1091                                 reg = <1>;
1092                                 remote-endpoint = <&edp_in_vopl>;
1093                         };
1094                 };
1095         };
1096
1097         vopl_mmu: iommu@ff8f3f00 {
1098                 compatible = "rockchip,iommu";
1099                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1100                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1101                 interrupt-names = "vopl_mmu";
1102                 #iommu-cells = <0>;
1103                 status = "disabled";
1104         };
1105
1106         vopb: vop@ff900000 {
1107                 compatible = "rockchip,rk3399-vop-big";
1108                 reg = <0x0 0xff900000 0x0 0x3efc>;
1109                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1110                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1111                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1112                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1113                 reset-names = "axi", "ahb", "dclk";
1114                 iommus = <&vopb_mmu>;
1115                 status = "disabled";
1116
1117                 vopb_out: port {
1118                         #address-cells = <1>;
1119                         #size-cells = <0>;
1120
1121                         vopb_out_edp: endpoint@0 {
1122                                 reg = <0>;
1123                                 remote-endpoint = <&edp_in_vopb>;
1124                         };
1125
1126                         vopb_out_mipi: endpoint@1 {
1127                                 reg = <1>;
1128                                 remote-endpoint = <&mipi_in_vopb>;
1129                         };
1130                 };
1131         };
1132
1133         vopb_mmu: iommu@ff903f00 {
1134                 compatible = "rockchip,iommu";
1135                 reg = <0x0 0xff903f00 0x0 0x100>;
1136                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1137                 interrupt-names = "vopb_mmu";
1138                 #iommu-cells = <0>;
1139                 status = "disabled";
1140         };
1141
1142         mipi_dsi: mipi@ff960000 {
1143                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1144                 reg = <0x0 0xff960000 0x0 0x8000>;
1145                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1146                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1147                          <&cru SCLK_DPHY_TX0_CFG>;
1148                 clock-names = "ref", "pclk", "phy_cfg";
1149                 rockchip,grf = <&grf>;
1150                 #address-cells = <1>;
1151                 #size-cells = <0>;
1152                 status = "disabled";
1153
1154                 ports {
1155                         #address-cells = <1>;
1156                         #size-cells = <0>;
1157                         reg = <1>;
1158
1159                         mipi_in: port {
1160                                 #address-cells = <1>;
1161                                 #size-cells = <0>;
1162
1163                                 mipi_in_vopb: endpoint@0 {
1164                                         reg = <0>;
1165                                         remote-endpoint = <&vopb_out_mipi>;
1166                                 };
1167                                 mipi_in_vopl: endpoint@1 {
1168                                         reg = <1>;
1169                                         remote-endpoint = <&vopl_out_mipi>;
1170                                 };
1171                         };
1172                 };
1173         };
1174
1175         edp: edp@ff970000 {
1176                 compatible = "rockchip,rk3399-edp";
1177                 reg = <0x0 0xff970000 0x0 0x8000>;
1178                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1179                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1180                 clock-names = "dp", "pclk";
1181                 resets = <&cru SRST_P_EDP_CTRL>;
1182                 reset-names = "dp";
1183                 rockchip,grf = <&grf>;
1184                 status = "disabled";
1185                 pinctrl-names = "default";
1186                 pinctrl-0 = <&edp_hpd>;
1187
1188                 ports {
1189                         #address-cells = <1>;
1190                         #size-cells = <0>;
1191
1192                         edp_in: port@0 {
1193                                 reg = <0>;
1194                                 #address-cells = <1>;
1195                                 #size-cells = <0>;
1196
1197                                 edp_in_vopb: endpoint@0 {
1198                                         reg = <0>;
1199                                         remote-endpoint = <&vopb_out_edp>;
1200                                 };
1201
1202                                 edp_in_vopl: endpoint@1 {
1203                                         reg = <1>;
1204                                         remote-endpoint = <&vopl_out_edp>;
1205                                 };
1206                         };
1207                 };
1208         };
1209
1210         display_subsystem: display-subsystem {
1211                 compatible = "rockchip,display-subsystem";
1212                 ports = <&vopl_out>, <&vopb_out>;
1213                 status = "disabled";
1214         };
1215
1216         pinctrl: pinctrl {
1217                 compatible = "rockchip,rk3399-pinctrl";
1218                 rockchip,grf = <&grf>;
1219                 rockchip,pmu = <&pmugrf>;
1220                 #address-cells = <0x2>;
1221                 #size-cells = <0x2>;
1222                 ranges;
1223
1224                 gpio0: gpio0@ff720000 {
1225                         compatible = "rockchip,gpio-bank";
1226                         reg = <0x0 0xff720000 0x0 0x100>;
1227                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1228                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1229
1230                         gpio-controller;
1231                         #gpio-cells = <0x2>;
1232
1233                         interrupt-controller;
1234                         #interrupt-cells = <0x2>;
1235                 };
1236
1237                 gpio1: gpio1@ff730000 {
1238                         compatible = "rockchip,gpio-bank";
1239                         reg = <0x0 0xff730000 0x0 0x100>;
1240                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1241                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1242
1243                         gpio-controller;
1244                         #gpio-cells = <0x2>;
1245
1246                         interrupt-controller;
1247                         #interrupt-cells = <0x2>;
1248                 };
1249
1250                 gpio2: gpio2@ff780000 {
1251                         compatible = "rockchip,gpio-bank";
1252                         reg = <0x0 0xff780000 0x0 0x100>;
1253                         clocks = <&cru PCLK_GPIO2>;
1254                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1255
1256                         gpio-controller;
1257                         #gpio-cells = <0x2>;
1258
1259                         interrupt-controller;
1260                         #interrupt-cells = <0x2>;
1261                 };
1262
1263                 gpio3: gpio3@ff788000 {
1264                         compatible = "rockchip,gpio-bank";
1265                         reg = <0x0 0xff788000 0x0 0x100>;
1266                         clocks = <&cru PCLK_GPIO3>;
1267                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1268
1269                         gpio-controller;
1270                         #gpio-cells = <0x2>;
1271
1272                         interrupt-controller;
1273                         #interrupt-cells = <0x2>;
1274                 };
1275
1276                 gpio4: gpio4@ff790000 {
1277                         compatible = "rockchip,gpio-bank";
1278                         reg = <0x0 0xff790000 0x0 0x100>;
1279                         clocks = <&cru PCLK_GPIO4>;
1280                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1281
1282                         gpio-controller;
1283                         #gpio-cells = <0x2>;
1284
1285                         interrupt-controller;
1286                         #interrupt-cells = <0x2>;
1287                 };
1288
1289                 pcfg_pull_up: pcfg-pull-up {
1290                         bias-pull-up;
1291                 };
1292
1293                 pcfg_pull_down: pcfg-pull-down {
1294                         bias-pull-down;
1295                 };
1296
1297                 pcfg_pull_none: pcfg-pull-none {
1298                         bias-disable;
1299                 };
1300
1301                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1302                         bias-disable;
1303                         drive-strength = <12>;
1304                 };
1305
1306                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1307                         bias-pull-up;
1308                         drive-strength = <8>;
1309                 };
1310
1311                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1312                         bias-pull-down;
1313                         drive-strength = <4>;
1314                 };
1315
1316                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1317                         bias-pull-up;
1318                         drive-strength = <2>;
1319                 };
1320
1321                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1322                         bias-pull-down;
1323                         drive-strength = <12>;
1324                 };
1325
1326                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1327                         bias-disable;
1328                         drive-strength = <13>;
1329                 };
1330
1331                 emmc {
1332                         emmc_pwr: emmc-pwr {
1333                                 rockchip,pins =
1334                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1335                         };
1336                 };
1337
1338                 gmac {
1339                         rgmii_pins: rgmii-pins {
1340                                 rockchip,pins =
1341                                         /* mac_txclk */
1342                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1343                                         /* mac_rxclk */
1344                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1345                                         /* mac_mdio */
1346                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1347                                         /* mac_txen */
1348                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1349                                         /* mac_clk */
1350                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1351                                         /* mac_rxdv */
1352                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1353                                         /* mac_mdc */
1354                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1355                                         /* mac_rxd1 */
1356                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1357                                         /* mac_rxd0 */
1358                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1359                                         /* mac_txd1 */
1360                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1361                                         /* mac_txd0 */
1362                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1363                                         /* mac_rxd3 */
1364                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1365                                         /* mac_rxd2 */
1366                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1367                                         /* mac_txd3 */
1368                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1369                                         /* mac_txd2 */
1370                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1371                         };
1372
1373                         rmii_pins: rmii-pins {
1374                                 rockchip,pins =
1375                                         /* mac_mdio */
1376                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1377                                         /* mac_txen */
1378                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1379                                         /* mac_clk */
1380                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1381                                         /* mac_rxer */
1382                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1383                                         /* mac_rxdv */
1384                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1385                                         /* mac_mdc */
1386                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1387                                         /* mac_rxd1 */
1388                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1389                                         /* mac_rxd0 */
1390                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1391                                         /* mac_txd1 */
1392                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1393                                         /* mac_txd0 */
1394                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1395                         };
1396                 };
1397
1398                 i2c0 {
1399                         i2c0_xfer: i2c0-xfer {
1400                                 rockchip,pins =
1401                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1402                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1403                         };
1404                 };
1405
1406                 i2c1 {
1407                         i2c1_xfer: i2c1-xfer {
1408                                 rockchip,pins =
1409                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1410                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1411                         };
1412                 };
1413
1414                 i2c2 {
1415                         i2c2_xfer: i2c2-xfer {
1416                                 rockchip,pins =
1417                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1418                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1419                         };
1420                 };
1421
1422                 i2c3 {
1423                         i2c3_xfer: i2c3-xfer {
1424                                 rockchip,pins =
1425                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1426                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1427                         };
1428                 };
1429
1430                 i2c4 {
1431                         i2c4_xfer: i2c4-xfer {
1432                                 rockchip,pins =
1433                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1434                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1435                         };
1436                 };
1437
1438                 i2c5 {
1439                         i2c5_xfer: i2c5-xfer {
1440                                 rockchip,pins =
1441                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1442                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1443                         };
1444                 };
1445
1446                 i2c6 {
1447                         i2c6_xfer: i2c6-xfer {
1448                                 rockchip,pins =
1449                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1450                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1451                         };
1452                 };
1453
1454                 i2c7 {
1455                         i2c7_xfer: i2c7-xfer {
1456                                 rockchip,pins =
1457                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1458                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1459                         };
1460                 };
1461
1462                 i2c8 {
1463                         i2c8_xfer: i2c8-xfer {
1464                                 rockchip,pins =
1465                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1466                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1467                         };
1468                 };
1469
1470                 i2s0 {
1471                         i2s0_8ch_bus: i2s0-8ch-bus {
1472                                 rockchip,pins =
1473                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1474                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1475                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1476                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1477                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1478                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1479                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1480                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1481                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1482                         };
1483                 };
1484
1485                 i2s1 {
1486                         i2s1_2ch_bus: i2s1-2ch-bus {
1487                                 rockchip,pins =
1488                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1489                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1490                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1491                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1492                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1493                         };
1494                 };
1495
1496                 sdio0 {
1497                         sdio0_bus1: sdio0-bus1 {
1498                                 rockchip,pins =
1499                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1500                         };
1501
1502                         sdio0_bus4: sdio0-bus4 {
1503                                 rockchip,pins =
1504                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1505                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1506                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1507                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1508                         };
1509
1510                         sdio0_cmd: sdio0-cmd {
1511                                 rockchip,pins =
1512                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1513                         };
1514
1515                         sdio0_clk: sdio0-clk {
1516                                 rockchip,pins =
1517                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1518                         };
1519
1520                         sdio0_cd: sdio0-cd {
1521                                 rockchip,pins =
1522                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1523                         };
1524
1525                         sdio0_pwr: sdio0-pwr {
1526                                 rockchip,pins =
1527                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1528                         };
1529
1530                         sdio0_bkpwr: sdio0-bkpwr {
1531                                 rockchip,pins =
1532                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1533                         };
1534
1535                         sdio0_wp: sdio0-wp {
1536                                 rockchip,pins =
1537                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1538                         };
1539
1540                         sdio0_int: sdio0-int {
1541                                 rockchip,pins =
1542                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1543                         };
1544                 };
1545
1546                 sdmmc {
1547                         sdmmc_bus1: sdmmc-bus1 {
1548                                 rockchip,pins =
1549                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1550                         };
1551
1552                         sdmmc_bus4: sdmmc-bus4 {
1553                                 rockchip,pins =
1554                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1555                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1556                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1557                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1558                         };
1559
1560                         sdmmc_clk: sdmmc-clk {
1561                                 rockchip,pins =
1562                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1563                         };
1564
1565                         sdmmc_cmd: sdmmc-cmd {
1566                                 rockchip,pins =
1567                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1568                         };
1569
1570                         sdmmc_cd: sdmcc-cd {
1571                                 rockchip,pins =
1572                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574
1575                         sdmmc_wp: sdmmc-wp {
1576                                 rockchip,pins =
1577                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1578                         };
1579                 };
1580
1581                 spdif {
1582                         spdif_bus: spdif-bus {
1583                                 rockchip,pins =
1584                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1585                         };
1586                 };
1587
1588                 spi0 {
1589                         spi0_clk: spi0-clk {
1590                                 rockchip,pins =
1591                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1592                         };
1593                         spi0_cs0: spi0-cs0 {
1594                                 rockchip,pins =
1595                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1596                         };
1597                         spi0_cs1: spi0-cs1 {
1598                                 rockchip,pins =
1599                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1600                         };
1601                         spi0_tx: spi0-tx {
1602                                 rockchip,pins =
1603                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1604                         };
1605                         spi0_rx: spi0-rx {
1606                                 rockchip,pins =
1607                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1608                         };
1609                 };
1610
1611                 spi1 {
1612                         spi1_clk: spi1-clk {
1613                                 rockchip,pins =
1614                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1615                         };
1616                         spi1_cs0: spi1-cs0 {
1617                                 rockchip,pins =
1618                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1619                         };
1620                         spi1_rx: spi1-rx {
1621                                 rockchip,pins =
1622                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1623                         };
1624                         spi1_tx: spi1-tx {
1625                                 rockchip,pins =
1626                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1627                         };
1628                 };
1629
1630                 spi2 {
1631                         spi2_clk: spi2-clk {
1632                                 rockchip,pins =
1633                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1634                         };
1635                         spi2_cs0: spi2-cs0 {
1636                                 rockchip,pins =
1637                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1638                         };
1639                         spi2_rx: spi2-rx {
1640                                 rockchip,pins =
1641                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1642                         };
1643                         spi2_tx: spi2-tx {
1644                                 rockchip,pins =
1645                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1646                         };
1647                 };
1648
1649                 spi3 {
1650                         spi3_clk: spi3-clk {
1651                                 rockchip,pins =
1652                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1653                         };
1654                         spi3_cs0: spi3-cs0 {
1655                                 rockchip,pins =
1656                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1657                         };
1658                         spi3_rx: spi3-rx {
1659                                 rockchip,pins =
1660                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1661                         };
1662                         spi3_tx: spi3-tx {
1663                                 rockchip,pins =
1664                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1665                         };
1666                 };
1667
1668                 spi4 {
1669                         spi4_clk: spi4-clk {
1670                                 rockchip,pins =
1671                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1672                         };
1673                         spi4_cs0: spi4-cs0 {
1674                                 rockchip,pins =
1675                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1676                         };
1677                         spi4_rx: spi4-rx {
1678                                 rockchip,pins =
1679                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1680                         };
1681                         spi4_tx: spi4-tx {
1682                                 rockchip,pins =
1683                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1684                         };
1685                 };
1686
1687                 spi5 {
1688                         spi5_clk: spi5-clk {
1689                                 rockchip,pins =
1690                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1691                         };
1692                         spi5_cs0: spi5-cs0 {
1693                                 rockchip,pins =
1694                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1695                         };
1696                         spi5_rx: spi5-rx {
1697                                 rockchip,pins =
1698                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1699                         };
1700                         spi5_tx: spi5-tx {
1701                                 rockchip,pins =
1702                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1703                         };
1704                 };
1705
1706                 tsadc {
1707                         otp_gpio: otp-gpio {
1708                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1709                         };
1710
1711                         otp_out: otp-out {
1712                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1713                         };
1714                 };
1715
1716                 uart0 {
1717                         uart0_xfer: uart0-xfer {
1718                                 rockchip,pins =
1719                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1720                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1721                         };
1722
1723                         uart0_cts: uart0-cts {
1724                                 rockchip,pins =
1725                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1726                         };
1727
1728                         uart0_rts: uart0-rts {
1729                                 rockchip,pins =
1730                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1731                         };
1732                 };
1733
1734                 uart1 {
1735                         uart1_xfer: uart1-xfer {
1736                                 rockchip,pins =
1737                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1738                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1739                         };
1740                 };
1741
1742                 uart2a {
1743                         uart2a_xfer: uart2a-xfer {
1744                                 rockchip,pins =
1745                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1746                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1747                         };
1748                 };
1749
1750                 uart2b {
1751                         uart2b_xfer: uart2b-xfer {
1752                                 rockchip,pins =
1753                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1754                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1755                         };
1756                 };
1757
1758                 uart2c {
1759                         uart2c_xfer: uart2c-xfer {
1760                                 rockchip,pins =
1761                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1762                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1763                         };
1764                 };
1765
1766                 uart3 {
1767                         uart3_xfer: uart3-xfer {
1768                                 rockchip,pins =
1769                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1770                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1771                         };
1772
1773                         uart3_cts: uart3-cts {
1774                                 rockchip,pins =
1775                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1776                         };
1777
1778                         uart3_rts: uart3-rts {
1779                                 rockchip,pins =
1780                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1781                         };
1782                 };
1783
1784                 uart4 {
1785                         uart4_xfer: uart4-xfer {
1786                                 rockchip,pins =
1787                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1788                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1789                         };
1790                 };
1791
1792                 uarthdcp {
1793                         uarthdcp_xfer: uarthdcp-xfer {
1794                                 rockchip,pins =
1795                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1796                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1797                         };
1798                 };
1799
1800                 pwm0 {
1801                         pwm0_pin: pwm0-pin {
1802                                 rockchip,pins =
1803                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1804                         };
1805
1806                         vop0_pwm_pin: vop0-pwm-pin {
1807                                 rockchip,pins =
1808                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1809                         };
1810                 };
1811
1812                 pwm1 {
1813                         pwm1_pin: pwm1-pin {
1814                                 rockchip,pins =
1815                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1816                         };
1817
1818                         vop1_pwm_pin: vop1-pwm-pin {
1819                                 rockchip,pins =
1820                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1821                         };
1822                 };
1823
1824                 pwm2 {
1825                         pwm2_pin: pwm2-pin {
1826                                 rockchip,pins =
1827                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1828                         };
1829                 };
1830
1831                 pwm3a {
1832                         pwm3a_pin: pwm3a-pin {
1833                                 rockchip,pins =
1834                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1835                         };
1836                 };
1837
1838                 pwm3b {
1839                         pwm3b_pin: pwm3b-pin {
1840                                 rockchip,pins =
1841                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1842                         };
1843                 };
1844
1845                 edp {
1846                         edp_hpd: edp-hpd {
1847                                 rockchip,pins =
1848                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1849                         };
1850                 };
1851         };
1852 };