arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         operating-points-v2 = <&cluster0_opp>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         operating-points-v2 = <&cluster0_opp>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164         };
 165
 166         cluster0_opp: opp_table0 {
 167                 compatible = "operating-points-v2";
 168                 opp-shared;
 169
 170                 opp00 {
 171                         opp-hz = /bits/ 64 <408000000>;
 172                         opp-microvolt = <900000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp01 {
 176                         opp-hz = /bits/ 64 <600000000>;
 177                         opp-microvolt = <900000>;
 178                 };
 179                 opp02 {
 180                         opp-hz = /bits/ 64 <816000000>;
 181                         opp-microvolt = <900000>;
 182                 };
 183                 opp03 {
 184                         opp-hz = /bits/ 64 <1008000000>;
 185                         opp-microvolt = <900000>;
 186                 };
 187         };
 188
 189         cluster1_opp: opp_table1 {
 190                 compatible = "operating-points-v2";
 191                 opp-shared;
 192
 193                 opp00 {
 194                         opp-hz = /bits/ 64 <408000000>;
 195                         opp-microvolt = <900000>;
 196                         clock-latency-ns = <40000>;
 197                 };
 198                 opp01 {
 199                         opp-hz = /bits/ 64 <600000000>;
 200                         opp-microvolt = <900000>;
 201                 };
 202                 opp02 {
 203                         opp-hz = /bits/ 64 <816000000>;
 204                         opp-microvolt = <900000>;
 205                 };
 206                 opp03 {
 207                         opp-hz = /bits/ 64 <1008000000>;
 208                         opp-microvolt = <900000>;
 209                 };
 210                 opp04 {
 211                         opp-hz = /bits/ 64 <1200000000>;
 212                         opp-microvolt = <900000>;
 213                 };
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 222         };
 223
 224         pmu_a53 {
 225                 compatible = "arm,cortex-a53-pmu";
 226                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 227                 interrupt-affinity = <&cpu_l0>,
 228                                      <&cpu_l1>,
 229                                      <&cpu_l2>,
 230                                      <&cpu_l3>;
 231         };
 232
 233         pmu_a72 {
 234                 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
 235                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 236                 interrupt-affinity = <&cpu_b0>,
 237                                      <&cpu_b1>;
 238         };
 239
 240         xin24m: xin24m {
 241                 compatible = "fixed-clock";
 242                 #clock-cells = <0>;
 243                 clock-frequency = <24000000>;
 244                 clock-output-names = "xin24m";
 245         };
 246
 247         amba {
 248                 compatible = "arm,amba-bus";
 249                 #address-cells = <2>;
 250                 #size-cells = <2>;
 251                 ranges;
 252
 253                 dmac_bus: dma-controller@ff6d0000 {
 254                         compatible = "arm,pl330", "arm,primecell";
 255                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 256                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 257                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 258                         #dma-cells = <1>;
 259                         clocks = <&cru ACLK_DMAC0_PERILP>;
 260                         clock-names = "apb_pclk";
 261                 };
 262
 263                 dmac_peri: dma-controller@ff6e0000 {
 264                         compatible = "arm,pl330", "arm,primecell";
 265                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 266                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 267                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 268                         #dma-cells = <1>;
 269                         clocks = <&cru ACLK_DMAC1_PERILP>;
 270                         clock-names = "apb_pclk";
 271                 };
 272         };
 273
 274         gmac: eth@fe300000 {
 275                 compatible = "rockchip,rk3399-gmac";
 276                 reg = <0x0 0xfe300000 0x0 0x10000>;
 277                 rockchip,grf = <&grf>;
 278                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 279                 interrupt-names = "macirq";
 280                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 281                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 282                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 283                          <&cru PCLK_GMAC>;
 284                 clock-names = "stmmaceth", "mac_clk_rx",
 285                               "mac_clk_tx", "clk_mac_ref",
 286                               "clk_mac_refout", "aclk_mac",
 287                               "pclk_mac";
 288                 resets = <&cru SRST_A_GMAC>;
 289                 reset-names = "stmmaceth";
 290                 status = "disabled";
 291         };
 292
 293         emmc_phy: phy {
 294                 compatible = "rockchip,rk3399-emmc-phy";
 295                 reg-offset = <0xf780>;
 296                 #phy-cells = <0>;
 297                 rockchip,grf = <&grf>;
 298                 status = "disabled";
 299         };
 300
 301         sdio0: dwmmc@fe310000 {
 302                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 303                 reg = <0x0 0xfe310000 0x0 0x4000>;
 304                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 305                 clock-freq-min-max = <400000 150000000>;
 306                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 307                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 308                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 309                 fifo-depth = <0x100>;
 310                 status = "disabled";
 311         };
 312
 313         sdmmc: dwmmc@fe320000 {
 314                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 315                 reg = <0x0 0xfe320000 0x0 0x4000>;
 316                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 317                 clock-freq-min-max = <400000 150000000>;
 318                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 319                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 320                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 321                 fifo-depth = <0x100>;
 322                 status = "disabled";
 323         };
 324
 325         sdhci: sdhci@fe330000 {
 326                 compatible = "arasan,sdhci-5.1";
 327                 reg = <0x0 0xfe330000 0x0 0x10000>;
 328                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 330                 clock-names = "clk_xin", "clk_ahb";
 331                 phys = <&emmc_phy>;
 332                 phy-names = "phy_arasan";
 333                 status = "disabled";
 334         };
 335
 336         usb2phy {
 337                 compatible = "rockchip,rk3399-usb-phy";
 338                 rockchip,grf = <&grf>;
 339                 vbus_drv-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342
 343                 usb2phy0: usb2-phy0 {
 344                         #phy-cells = <0>;
 345                         #clock-cells = <0>;
 346                         reg = <0xe458>;
 347                 };
 348
 349                 usb2phy1: usb2-phy1 {
 350                         #phy-cells = <0>;
 351                         #clock-cells = <0>;
 352                         reg = <0xe468>;
 353                 };
 354         };
 355
 356         usb_host0_echi: usb@fe380000 {
 357                 compatible = "generic-ehci";
 358                 reg = <0x0 0xfe380000 0x0 0x20000>;
 359                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 361                 clock-names = "hclk_host0", "hclk_host0_arb";
 362                 phys = <&usb2phy0>;
 363                 phy-names = "usb2_phy0";
 364                 status = "disabled";
 365         };
 366
 367         usb_host0_ohci: usb@fe3a0000 {
 368                 compatible = "generic-ohci";
 369                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 370                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 371                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 372                 clock-names = "hclk_host0", "hclk_host0_arb";
 373                 status = "disabled";
 374         };
 375
 376         usb_host1_echi: usb@fe3c0000 {
 377                 compatible = "generic-ehci";
 378                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 379                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 381                 clock-names = "hclk_host1", "hclk_host1_arb";
 382                 phys = <&usb2phy1>;
 383                 phy-names = "usb2_phy1";
 384                 status = "disabled";
 385         };
 386
 387         usb_host1_ohci: usb@fe3e0000 {
 388                 compatible = "generic-ohci";
 389                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 390                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 391                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 392                 clock-names = "hclk_host1", "hclk_host1_arb";
 393                 status = "disabled";
 394         };
 395
 396         usbdrd3_0: usb@fe800000 {
 397                 compatible = "rockchip,dwc3";
 398                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 399                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 400                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
 401                          <&cru ACLK_USB3_GRF>;
 402                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 403                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 404                               "aclk_usb3", "aclk_usb3_noc",
 405                               "aclk_usb3_grf";
 406                 #address-cells = <2>;
 407                 #size-cells = <2>;
 408                 ranges;
 409                 status = "disabled";
 410                 usbdrd_dwc3_0: dwc3 {
 411                         compatible = "snps,dwc3";
 412                         reg = <0x0 0xfe800000 0x0 0x100000>;
 413                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 414                         dr_mode = "otg";
 415                         tx-fifo-resize;
 416                         snps,dis_enblslpm_quirk;
 417                         snps,phyif_utmi_16_bits;
 418                         snps,dis_u2_freeclk_exists_quirk;
 419                         snps,dis_del_phy_power_chg_quirk;
 420                         status = "disabled";
 421                 };
 422         };
 423
 424         usbdrd3_1: usb@fe900000 {
 425                 compatible = "rockchip,dwc3";
 426                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 427                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 428                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
 429                          <&cru ACLK_USB3_GRF>;
 430                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 431                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 432                               "aclk_usb3", "aclk_usb3_noc",
 433                               "aclk_usb3_grf";
 434                 #address-cells = <2>;
 435                 #size-cells = <2>;
 436                 ranges;
 437                 status = "disabled";
 438                 usbdrd_dwc3_1: dwc3 {
 439                         compatible = "snps,dwc3";
 440                         reg = <0x0 0xfe900000 0x0 0x100000>;
 441                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 442                         dr_mode = "otg";
 443                         tx-fifo-resize;
 444                         snps,dis_enblslpm_quirk;
 445                         snps,phyif_utmi_16_bits;
 446                         snps,dis_u2_freeclk_exists_quirk;
 447                         snps,dis_del_phy_power_chg_quirk;
 448                         status = "disabled";
 449                 };
 450         };
 451
 452         gic: interrupt-controller@fee00000 {
 453                 compatible = "arm,gic-v3";
 454                 #interrupt-cells = <3>;
 455                 #address-cells = <2>;
 456                 #size-cells = <2>;
 457                 ranges;
 458                 interrupt-controller;
 459
 460                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 461                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 462                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 463                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 464                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 465                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 466                 its: interrupt-controller@fee20000 {
 467                         compatible = "arm,gic-v3-its";
 468                         msi-controller;
 469                         reg = <0x0 0xfee20000 0x0 0x20000>;
 470                 };
 471         };
 472
 473         saradc: saradc@ff100000 {
 474                 compatible = "rockchip,rk3399-saradc";
 475                 reg = <0x0 0xff100000 0x0 0x100>;
 476                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 477                 #io-channel-cells = <1>;
 478                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 479                 clock-names = "saradc", "apb_pclk";
 480                 status = "disabled";
 481         };
 482
 483         i2c0: i2c@ff3c0000 {
 484                 compatible = "rockchip,rk3399-i2c";
 485                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 486                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 487                 clock-names = "i2c", "pclk";
 488                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&i2c0_xfer>;
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 status = "disabled";
 494         };
 495
 496         i2c1: i2c@ff110000 {
 497                 compatible = "rockchip,rk3399-i2c";
 498                 reg = <0x0 0xff110000 0x0 0x1000>;
 499                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 500                 clock-names = "i2c", "pclk";
 501                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 502                 pinctrl-names = "default";
 503                 pinctrl-0 = <&i2c1_xfer>;
 504                 #address-cells = <1>;
 505                 #size-cells = <0>;
 506                 status = "disabled";
 507         };
 508
 509         i2c2: i2c@ff120000 {
 510                 compatible = "rockchip,rk3399-i2c";
 511                 reg = <0x0 0xff120000 0x0 0x1000>;
 512                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 513                 clock-names = "i2c", "pclk";
 514                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&i2c2_xfer>;
 517                 #address-cells = <1>;
 518                 #size-cells = <0>;
 519                 status = "disabled";
 520         };
 521
 522         i2c3: i2c@ff130000 {
 523                 compatible = "rockchip,rk3399-i2c";
 524                 reg = <0x0 0xff130000 0x0 0x1000>;
 525                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 526                 clock-names = "i2c", "pclk";
 527                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 528                 pinctrl-names = "default";
 529                 pinctrl-0 = <&i2c3_xfer>;
 530                 #address-cells = <1>;
 531                 #size-cells = <0>;
 532                 status = "disabled";
 533         };
 534
 535         i2c5: i2c@ff140000 {
 536                 compatible = "rockchip,rk3399-i2c";
 537                 reg = <0x0 0xff140000 0x0 0x1000>;
 538                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 539                 clock-names = "i2c", "pclk";
 540                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 541                 pinctrl-names = "default";
 542                 pinctrl-0 = <&i2c5_xfer>;
 543                 #address-cells = <1>;
 544                 #size-cells = <0>;
 545                 status = "disabled";
 546         };
 547
 548         i2c6: i2c@ff150000 {
 549                 compatible = "rockchip,rk3399-i2c";
 550                 reg = <0x0 0xff150000 0x0 0x1000>;
 551                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 552                 clock-names = "i2c", "pclk";
 553                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&i2c6_xfer>;
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 status = "disabled";
 559         };
 560
 561         i2c7: i2c@ff160000 {
 562                 compatible = "rockchip,rk3399-i2c";
 563                 reg = <0x0 0xff160000 0x0 0x1000>;
 564                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 565                 clock-names = "i2c", "pclk";
 566                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&i2c7_xfer>;
 569                 #address-cells = <1>;
 570                 #size-cells = <0>;
 571                 status = "disabled";
 572         };
 573
 574         uart0: serial@ff180000 {
 575                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 576                 reg = <0x0 0xff180000 0x0 0x100>;
 577                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 578                 clock-names = "baudclk", "apb_pclk";
 579                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 580                 reg-shift = <2>;
 581                 reg-io-width = <4>;
 582                 pinctrl-names = "default";
 583                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 584                 status = "disabled";
 585         };
 586
 587         uart1: serial@ff190000 {
 588                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 589                 reg = <0x0 0xff190000 0x0 0x100>;
 590                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 591                 clock-names = "baudclk", "apb_pclk";
 592                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 593                 reg-shift = <2>;
 594                 reg-io-width = <4>;
 595                 pinctrl-names = "default";
 596                 pinctrl-0 = <&uart1_xfer>;
 597                 status = "disabled";
 598         };
 599
 600         uart2: serial@ff1a0000 {
 601                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 602                 reg = <0x0 0xff1a0000 0x0 0x100>;
 603                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 604                 clock-names = "baudclk", "apb_pclk";
 605                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 606                 reg-shift = <2>;
 607                 reg-io-width = <4>;
 608                 pinctrl-names = "default";
 609                 pinctrl-0 = <&uart2c_xfer>;
 610                 status = "disabled";
 611         };
 612
 613         uart3: serial@ff1b0000 {
 614                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 615                 reg = <0x0 0xff1b0000 0x0 0x100>;
 616                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 617                 clock-names = "baudclk", "apb_pclk";
 618                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 619                 reg-shift = <2>;
 620                 reg-io-width = <4>;
 621                 pinctrl-names = "default";
 622                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 623                 status = "disabled";
 624         };
 625
 626         spi0: spi@ff1c0000 {
 627                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 628                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 629                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 630                 clock-names = "spiclk", "apb_pclk";
 631                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 632                 pinctrl-names = "default";
 633                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 634                 #address-cells = <1>;
 635                 #size-cells = <0>;
 636                 status = "disabled";
 637         };
 638
 639         spi1: spi@ff1d0000 {
 640                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 641                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 642                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 643                 clock-names = "spiclk", "apb_pclk";
 644                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 645                 pinctrl-names = "default";
 646                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 647                 #address-cells = <1>;
 648                 #size-cells = <0>;
 649                 status = "disabled";
 650         };
 651
 652         spi2: spi@ff1e0000 {
 653                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 654                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 655                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 656                 clock-names = "spiclk", "apb_pclk";
 657                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 658                 pinctrl-names = "default";
 659                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 660                 #address-cells = <1>;
 661                 #size-cells = <0>;
 662                 status = "disabled";
 663         };
 664
 665         spi4: spi@ff1f0000 {
 666                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 667                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 668                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 669                 clock-names = "spiclk", "apb_pclk";
 670                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 673                 #address-cells = <1>;
 674                 #size-cells = <0>;
 675                 status = "disabled";
 676         };
 677
 678         spi5: spi@ff200000 {
 679                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 680                 reg = <0x0 0xff200000 0x0 0x1000>;
 681                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 682                 clock-names = "spiclk", "apb_pclk";
 683                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 684                 pinctrl-names = "default";
 685                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 status = "disabled";
 689         };
 690
 691         thermal-zones {
 692                 #include "rk3368-thermal.dtsi"
 693         };
 694
 695         tsadc: tsadc@ff260000 {
 696                 compatible = "rockchip,rk3399-tsadc";
 697                 reg = <0x0 0xff260000 0x0 0x100>;
 698                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 699                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 700                 clock-names = "tsadc", "apb_pclk";
 701                 resets = <&cru SRST_TSADC>;
 702                 reset-names = "tsadc-apb";
 703                 pinctrl-names = "init", "default", "sleep";
 704                 pinctrl-0 = <&otp_gpio>;
 705                 pinctrl-1 = <&otp_out>;
 706                 pinctrl-2 = <&otp_gpio>;
 707                 #thermal-sensor-cells = <1>;
 708                 rockchip,hw-tshut-temp = <95000>;
 709                 status = "disabled";
 710         };
 711
 712         pmu: power-management@ff31000 {
 713                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 714                 reg = <0x0 0xff310000 0x0 0x1000>;
 715
 716                 power: power-controller {
 717                         status = "disabled";
 718                         compatible = "rockchip,rk3399-power-controller";
 719                         #power-domain-cells = <1>;
 720                         #address-cells = <1>;
 721                         #size-cells = <0>;
 722
 723                         pd_center {
 724                                 reg = <RK3399_PD_CENTER>;
 725                                 #address-cells = <1>;
 726                                 #size-cells = <0>;
 727
 728                                 pd_vdu {
 729                                         reg = <RK3399_PD_VDU>;
 730                                 };
 731                                 pd_vcodec {
 732                                         reg = <RK3399_PD_VCODEC>;
 733                                 };
 734                                 pd_iep {
 735                                         reg = <RK3399_PD_IEP>;
 736                                 };
 737                                 pd_rga {
 738                                         reg = <RK3399_PD_RGA>;
 739                                 };
 740                         };
 741                         pd_vio {
 742                                 reg = <RK3399_PD_VIO>;
 743                                 #address-cells = <1>;
 744                                 #size-cells = <0>;
 745
 746                                 pd_isp0 {
 747                                         reg = <RK3399_PD_ISP0>;
 748                                 };
 749                                 pd_isp1 {
 750                                         reg = <RK3399_PD_ISP1>;
 751                                 };
 752                                 pd_hdcp {
 753                                         reg = <RK3399_PD_HDCP>;
 754                                 };
 755                                 pd_vo {
 756                                         reg = <RK3399_PD_VO>;
 757                                         #address-cells = <1>;
 758                                         #size-cells = <0>;
 759
 760                                         pd_vopb {
 761                                                 reg = <RK3399_PD_VOPB>;
 762                                         };
 763                                         pd_vopl {
 764                                                 reg = <RK3399_PD_VOPL>;
 765                                         };
 766                                 };
 767                         };
 768                         pd_gpu {
 769                                 reg = <RK3399_PD_GPU>;
 770                         };
 771                 };
 772         };
 773
 774         pmugrf: syscon@ff320000 {
 775                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 776                 reg = <0x0 0xff320000 0x0 0x1000>;
 777         };
 778
 779         spi3: spi@ff350000 {
 780                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 781                 reg = <0x0 0xff350000 0x0 0x1000>;
 782                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 783                 clock-names = "spiclk", "apb_pclk";
 784                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 785                 pinctrl-names = "default";
 786                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 787                 #address-cells = <1>;
 788                 #size-cells = <0>;
 789                 status = "disabled";
 790         };
 791
 792         uart4: serial@ff370000 {
 793                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 794                 reg = <0x0 0xff370000 0x0 0x100>;
 795                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 796                 clock-names = "baudclk", "apb_pclk";
 797                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 798                 reg-shift = <2>;
 799                 reg-io-width = <4>;
 800                 pinctrl-names = "default";
 801                 pinctrl-0 = <&uart4_xfer>;
 802                 status = "disabled";
 803         };
 804
 805         i2c4: i2c@ff3d0000 {
 806                 compatible = "rockchip,rk3399-i2c";
 807                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 808                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 809                 clock-names = "i2c", "pclk";
 810                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 811                 pinctrl-names = "default";
 812                 pinctrl-0 = <&i2c4_xfer>;
 813                 #address-cells = <1>;
 814                 #size-cells = <0>;
 815                 status = "disabled";
 816         };
 817
 818         i2c8: i2c@ff3e0000 {
 819                 compatible = "rockchip,rk3399-i2c";
 820                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 821                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 822                 clock-names = "i2c", "pclk";
 823                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 824                 pinctrl-names = "default";
 825                 pinctrl-0 = <&i2c8_xfer>;
 826                 #address-cells = <1>;
 827                 #size-cells = <0>;
 828                 status = "disabled";
 829         };
 830
 831         pwm0: pwm@ff420000 {
 832                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 833                 reg = <0x0 0xff420000 0x0 0x10>;
 834                 #pwm-cells = <3>;
 835                 pinctrl-names = "default";
 836                 pinctrl-0 = <&pwm0_pin>;
 837                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 838                 clock-names = "pwm";
 839                 status = "disabled";
 840         };
 841
 842         pwm1: pwm@ff420010 {
 843                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 844                 reg = <0x0 0xff420010 0x0 0x10>;
 845                 #pwm-cells = <3>;
 846                 pinctrl-names = "default";
 847                 pinctrl-0 = <&pwm1_pin>;
 848                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 849                 clock-names = "pwm";
 850                 status = "disabled";
 851         };
 852
 853         pwm2: pwm@ff420020 {
 854                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 855                 reg = <0x0 0xff420020 0x0 0x10>;
 856                 #pwm-cells = <3>;
 857                 pinctrl-names = "default";
 858                 pinctrl-0 = <&pwm2_pin>;
 859                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 860                 clock-names = "pwm";
 861                 status = "disabled";
 862         };
 863
 864         pwm3: pwm@ff420030 {
 865                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 866                 reg = <0x0 0xff420030 0x0 0x10>;
 867                 #pwm-cells = <3>;
 868                 pinctrl-names = "default";
 869                 pinctrl-0 = <&pwm3a_pin>;
 870                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 871                 clock-names = "pwm";
 872                 status = "disabled";
 873         };
 874
 875         pmucru: pmu-clock-controller@ff750000 {
 876                 compatible = "rockchip,rk3399-pmucru";
 877                 reg = <0x0 0xff750000 0x0 0x1000>;
 878                 rockchip,grf = <&pmugrf>;
 879                 #clock-cells = <1>;
 880                 #reset-cells = <1>;
 881                 assigned-clocks = <&pmucru PLL_PPLL>;
 882                 assigned-clock-rates = <676000000>;
 883         };
 884
 885         cru: clock-controller@ff760000 {
 886                 compatible = "rockchip,rk3399-cru";
 887                 reg = <0x0 0xff760000 0x0 0x1000>;
 888                 rockchip,grf = <&grf>;
 889                 #clock-cells = <1>;
 890                 #reset-cells = <1>;
 891                 assigned-clocks =
 892                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 893                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 894                         <&cru PLL_NPLL>,
 895                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 896                         <&cru PCLK_PERIHP>,
 897                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 898                         <&cru PCLK_PERILP0>,
 899                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 900                 assigned-clock-rates =
 901                          <816000000>, <1008000000>,
 902                          <594000000>,  <800000000>,
 903                         <1000000000>,
 904                          <150000000>,   <75000000>,
 905                           <37500000>,
 906                          <100000000>,  <100000000>,
 907                           <50000000>,
 908                          <100000000>,   <50000000>;
 909         };
 910
 911         grf: syscon@ff770000 {
 912                 compatible = "rockchip,rk3399-grf", "syscon";
 913                 reg = <0x0 0xff770000 0x0 0x10000>;
 914         };
 915
 916         wdt0: watchdog@ff840000 {
 917                 compatible = "snps,dw-wdt";
 918                 reg = <0x0 0xff840000 0x0 0x100>;
 919                 clocks = <&cru PCLK_WDT>;
 920                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 921                 status = "disabled";
 922         };
 923
 924         spdif: spdif@ff870000 {
 925                 compatible = "rockchip,rk3399-spdif";
 926                 reg = <0x0 0xff870000 0x0 0x1000>;
 927                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 928                 dmas = <&dmac_bus 7>;
 929                 dma-names = "tx";
 930                 clock-names = "hclk", "mclk";
 931                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 932                 pinctrl-names = "default";
 933                 pinctrl-0 = <&spdif_bus>;
 934                 status = "disabled";
 935         };
 936
 937         i2s0: i2s@ff880000 {
 938                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 939                 reg = <0x0 0xff880000 0x0 0x1000>;
 940                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 941                 #address-cells = <1>;
 942                 #size-cells = <0>;
 943                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 944                 dma-names = "tx", "rx";
 945                 clock-names = "i2s_hclk", "i2s_clk";
 946                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 947                 pinctrl-names = "default";
 948                 pinctrl-0 = <&i2s0_8ch_bus>;
 949                 status = "disabled";
 950         };
 951
 952         i2s1: i2s@ff890000 {
 953                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 954                 reg = <0x0 0xff890000 0x0 0x1000>;
 955                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 956                 #address-cells = <1>;
 957                 #size-cells = <0>;
 958                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 959                 dma-names = "tx", "rx";
 960                 clock-names = "i2s_hclk", "i2s_clk";
 961                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 962                 pinctrl-names = "default";
 963                 pinctrl-0 = <&i2s1_2ch_bus>;
 964                 status = "disabled";
 965         };
 966
 967         i2s2: i2s@ff8a0000 {
 968                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 969                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 970                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 971                 #address-cells = <1>;
 972                 #size-cells = <0>;
 973                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 974                 dma-names = "tx", "rx";
 975                 clock-names = "i2s_hclk", "i2s_clk";
 976                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 977                 status = "disabled";
 978         };
 979
 980         pinctrl: pinctrl {
 981                 compatible = "rockchip,rk3399-pinctrl";
 982                 rockchip,grf = <&grf>;
 983                 rockchip,pmu = <&pmugrf>;
 984                 #address-cells = <0x2>;
 985                 #size-cells = <0x2>;
 986                 ranges;
 987
 988                 gpio0: gpio0@ff720000 {
 989                         compatible = "rockchip,gpio-bank";
 990                         reg = <0x0 0xff720000 0x0 0x100>;
 991                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 992                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 993
 994                         gpio-controller;
 995                         #gpio-cells = <0x2>;
 996
 997                         interrupt-controller;
 998                         #interrupt-cells = <0x2>;
 999                 };
1000
1001                 gpio1: gpio1@ff730000 {
1002                         compatible = "rockchip,gpio-bank";
1003                         reg = <0x0 0xff730000 0x0 0x100>;
1004                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1005                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1006
1007                         gpio-controller;
1008                         #gpio-cells = <0x2>;
1009
1010                         interrupt-controller;
1011                         #interrupt-cells = <0x2>;
1012                 };
1013
1014                 gpio2: gpio2@ff780000 {
1015                         compatible = "rockchip,gpio-bank";
1016                         reg = <0x0 0xff780000 0x0 0x100>;
1017                         clocks = <&cru PCLK_GPIO2>;
1018                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1019
1020                         gpio-controller;
1021                         #gpio-cells = <0x2>;
1022
1023                         interrupt-controller;
1024                         #interrupt-cells = <0x2>;
1025                 };
1026
1027                 gpio3: gpio3@ff788000 {
1028                         compatible = "rockchip,gpio-bank";
1029                         reg = <0x0 0xff788000 0x0 0x100>;
1030                         clocks = <&cru PCLK_GPIO3>;
1031                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1032
1033                         gpio-controller;
1034                         #gpio-cells = <0x2>;
1035
1036                         interrupt-controller;
1037                         #interrupt-cells = <0x2>;
1038                 };
1039
1040                 gpio4: gpio4@ff790000 {
1041                         compatible = "rockchip,gpio-bank";
1042                         reg = <0x0 0xff790000 0x0 0x100>;
1043                         clocks = <&cru PCLK_GPIO4>;
1044                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1045
1046                         gpio-controller;
1047                         #gpio-cells = <0x2>;
1048
1049                         interrupt-controller;
1050                         #interrupt-cells = <0x2>;
1051                 };
1052
1053                 pcfg_pull_up: pcfg-pull-up {
1054                         bias-pull-up;
1055                 };
1056
1057                 pcfg_pull_down: pcfg-pull-down {
1058                         bias-pull-down;
1059                 };
1060
1061                 pcfg_pull_none: pcfg-pull-none {
1062                         bias-disable;
1063                 };
1064
1065                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1066                         bias-disable;
1067                         drive-strength = <12>;
1068                 };
1069
1070                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1071                         bias-pull-up;
1072                         drive-strength = <8>;
1073                 };
1074
1075                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1076                         bias-pull-down;
1077                         drive-strength = <4>;
1078                 };
1079
1080                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1081                         bias-pull-up;
1082                         drive-strength = <2>;
1083                 };
1084
1085                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1086                         bias-pull-down;
1087                         drive-strength = <12>;
1088                 };
1089
1090                 emmc {
1091                         emmc_pwr: emmc-pwr {
1092                                 rockchip,pins =
1093                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1094                         };
1095                 };
1096
1097                 gmac {
1098                         rgmii_pins: rgmii-pins {
1099                                 rockchip,pins =
1100                                         /* mac_txclk */
1101                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1102                                         /* mac_rxclk */
1103                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1104                                         /* mac_mdio */
1105                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1106                                         /* mac_txen */
1107                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1108                                         /* mac_clk */
1109                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1110                                         /* mac_rxdv */
1111                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1112                                         /* mac_mdc */
1113                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1114                                         /* mac_rxd1 */
1115                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1116                                         /* mac_rxd0 */
1117                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1118                                         /* mac_txd1 */
1119                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1120                                         /* mac_txd0 */
1121                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1122                                         /* mac_rxd3 */
1123                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1124                                         /* mac_rxd2 */
1125                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1126                                         /* mac_txd3 */
1127                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1128                                         /* mac_txd2 */
1129                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
1130                         };
1131
1132                         rmii_pins: rmii-pins {
1133                                 rockchip,pins =
1134                                         /* mac_mdio */
1135                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1136                                         /* mac_txen */
1137                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1138                                         /* mac_clk */
1139                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1140                                         /* mac_rxer */
1141                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1142                                         /* mac_rxdv */
1143                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1144                                         /* mac_mdc */
1145                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1146                                         /* mac_rxd1 */
1147                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1148                                         /* mac_rxd0 */
1149                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1150                                         /* mac_txd1 */
1151                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1152                                         /* mac_txd0 */
1153                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
1154                         };
1155                 };
1156
1157                 i2c0 {
1158                         i2c0_xfer: i2c0-xfer {
1159                                 rockchip,pins =
1160                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1161                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1162                         };
1163                 };
1164
1165                 i2c1 {
1166                         i2c1_xfer: i2c1-xfer {
1167                                 rockchip,pins =
1168                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1169                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1170                         };
1171                 };
1172
1173                 i2c2 {
1174                         i2c2_xfer: i2c2-xfer {
1175                                 rockchip,pins =
1176                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1177                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1178                         };
1179                 };
1180
1181                 i2c3 {
1182                         i2c3_xfer: i2c3-xfer {
1183                                 rockchip,pins =
1184                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1185                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1186                         };
1187                 };
1188
1189                 i2c4 {
1190                         i2c4_xfer: i2c4-xfer {
1191                                 rockchip,pins =
1192                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1193                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1194                         };
1195                 };
1196
1197                 i2c5 {
1198                         i2c5_xfer: i2c5-xfer {
1199                                 rockchip,pins =
1200                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1201                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1202                         };
1203                 };
1204
1205                 i2c6 {
1206                         i2c6_xfer: i2c6-xfer {
1207                                 rockchip,pins =
1208                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1209                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1210                         };
1211                 };
1212
1213                 i2c7 {
1214                         i2c7_xfer: i2c7-xfer {
1215                                 rockchip,pins =
1216                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1217                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1218                         };
1219                 };
1220
1221                 i2c8 {
1222                         i2c8_xfer: i2c8-xfer {
1223                                 rockchip,pins =
1224                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1225                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1226                         };
1227                 };
1228
1229                 i2s0 {
1230                         i2s0_8ch_bus: i2s0-8ch-bus {
1231                                 rockchip,pins =
1232                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1233                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1234                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1235                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1236                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1237                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1238                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1239                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1240                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1241                         };
1242                 };
1243
1244                 i2s1 {
1245                         i2s1_2ch_bus: i2s1-2ch-bus {
1246                                 rockchip,pins =
1247                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1248                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1249                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1250                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1251                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1252                         };
1253                 };
1254
1255                 sdio0 {
1256                         sdio0_bus1: sdio0-bus1 {
1257                                 rockchip,pins =
1258                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1259                         };
1260
1261                         sdio0_bus4: sdio0-bus4 {
1262                                 rockchip,pins =
1263                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1264                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1265                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1266                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1267                         };
1268
1269                         sdio0_cmd: sdio0-cmd {
1270                                 rockchip,pins =
1271                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1272                         };
1273
1274                         sdio0_clk: sdio0-clk {
1275                                 rockchip,pins =
1276                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1277                         };
1278
1279                         sdio0_cd: sdio0-cd {
1280                                 rockchip,pins =
1281                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1282                         };
1283
1284                         sdio0_pwr: sdio0-pwr {
1285                                 rockchip,pins =
1286                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1287                         };
1288
1289                         sdio0_bkpwr: sdio0-bkpwr {
1290                                 rockchip,pins =
1291                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1292                         };
1293
1294                         sdio0_wp: sdio0-wp {
1295                                 rockchip,pins =
1296                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1297                         };
1298
1299                         sdio0_int: sdio0-int {
1300                                 rockchip,pins =
1301                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1302                         };
1303                 };
1304
1305                 sdmmc {
1306                         sdmmc_bus1: sdmmc-bus1 {
1307                                 rockchip,pins =
1308                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1309                         };
1310
1311                         sdmmc_bus4: sdmmc-bus4 {
1312                                 rockchip,pins =
1313                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1314                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1315                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1316                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1317                         };
1318
1319                         sdmmc_clk: sdmmc-clk {
1320                                 rockchip,pins =
1321                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1322                         };
1323
1324                         sdmmc_cmd: sdmmc-cmd {
1325                                 rockchip,pins =
1326                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1327                         };
1328
1329                         sdmmc_cd: sdmcc-cd {
1330                                 rockchip,pins =
1331                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1332                         };
1333
1334                         sdmmc_wp: sdmmc-wp {
1335                                 rockchip,pins =
1336                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1337                         };
1338                 };
1339
1340                 spdif {
1341                         spdif_bus: spdif-bus {
1342                                 rockchip,pins =
1343                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1344                         };
1345                 };
1346
1347                 spi0 {
1348                         spi0_clk: spi0-clk {
1349                                 rockchip,pins =
1350                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1351                         };
1352                         spi0_cs0: spi0-cs0 {
1353                                 rockchip,pins =
1354                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1355                         };
1356                         spi0_cs1: spi0-cs1 {
1357                                 rockchip,pins =
1358                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1359                         };
1360                         spi0_tx: spi0-tx {
1361                                 rockchip,pins =
1362                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1363                         };
1364                         spi0_rx: spi0-rx {
1365                                 rockchip,pins =
1366                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1367                         };
1368                 };
1369
1370                 spi1 {
1371                         spi1_clk: spi1-clk {
1372                                 rockchip,pins =
1373                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1374                         };
1375                         spi1_cs0: spi1-cs0 {
1376                                 rockchip,pins =
1377                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1378                         };
1379                         spi1_rx: spi1-rx {
1380                                 rockchip,pins =
1381                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1382                         };
1383                         spi1_tx: spi1-tx {
1384                                 rockchip,pins =
1385                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1386                         };
1387                 };
1388
1389                 spi2 {
1390                         spi2_clk: spi2-clk {
1391                                 rockchip,pins =
1392                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1393                         };
1394                         spi2_cs0: spi2-cs0 {
1395                                 rockchip,pins =
1396                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1397                         };
1398                         spi2_rx: spi2-rx {
1399                                 rockchip,pins =
1400                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1401                         };
1402                         spi2_tx: spi2-tx {
1403                                 rockchip,pins =
1404                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1405                         };
1406                 };
1407
1408                 spi3 {
1409                         spi3_clk: spi3-clk {
1410                                 rockchip,pins =
1411                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1412                         };
1413                         spi3_cs0: spi3-cs0 {
1414                                 rockchip,pins =
1415                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1416                         };
1417                         spi3_rx: spi3-rx {
1418                                 rockchip,pins =
1419                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1420                         };
1421                         spi3_tx: spi3-tx {
1422                                 rockchip,pins =
1423                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1424                         };
1425                 };
1426
1427                 spi4 {
1428                         spi4_clk: spi4-clk {
1429                                 rockchip,pins =
1430                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1431                         };
1432                         spi4_cs0: spi4-cs0 {
1433                                 rockchip,pins =
1434                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1435                         };
1436                         spi4_rx: spi4-rx {
1437                                 rockchip,pins =
1438                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1439                         };
1440                         spi4_tx: spi4-tx {
1441                                 rockchip,pins =
1442                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1443                         };
1444                 };
1445
1446                 spi5 {
1447                         spi5_clk: spi5-clk {
1448                                 rockchip,pins =
1449                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1450                         };
1451                         spi5_cs0: spi5-cs0 {
1452                                 rockchip,pins =
1453                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1454                         };
1455                         spi5_rx: spi5-rx {
1456                                 rockchip,pins =
1457                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1458                         };
1459                         spi5_tx: spi5-tx {
1460                                 rockchip,pins =
1461                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1462                         };
1463                 };
1464
1465                 tsadc {
1466                         otp_gpio: otp-gpio {
1467                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1468                         };
1469
1470                         otp_out: otp-out {
1471                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1472                         };
1473                 };
1474
1475                 uart0 {
1476                         uart0_xfer: uart0-xfer {
1477                                 rockchip,pins =
1478                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1479                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1480                         };
1481
1482                         uart0_cts: uart0-cts {
1483                                 rockchip,pins =
1484                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1485                         };
1486
1487                         uart0_rts: uart0-rts {
1488                                 rockchip,pins =
1489                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1490                         };
1491                 };
1492
1493                 uart1 {
1494                         uart1_xfer: uart1-xfer {
1495                                 rockchip,pins =
1496                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1497                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1498                         };
1499                 };
1500
1501                 uart2a {
1502                         uart2a_xfer: uart2a-xfer {
1503                                 rockchip,pins =
1504                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1505                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1506                         };
1507                 };
1508
1509                 uart2b {
1510                         uart2b_xfer: uart2b-xfer {
1511                                 rockchip,pins =
1512                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1513                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1514                         };
1515                 };
1516
1517                 uart2c {
1518                         uart2c_xfer: uart2c-xfer {
1519                                 rockchip,pins =
1520                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1521                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1522                         };
1523                 };
1524
1525                 uart3 {
1526                         uart3_xfer: uart3-xfer {
1527                                 rockchip,pins =
1528                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1529                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1530                         };
1531
1532                         uart3_cts: uart3-cts {
1533                                 rockchip,pins =
1534                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1535                         };
1536
1537                         uart3_rts: uart3-rts {
1538                                 rockchip,pins =
1539                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1540                         };
1541                 };
1542
1543                 uart4 {
1544                         uart4_xfer: uart4-xfer {
1545                                 rockchip,pins =
1546                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1547                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1548                         };
1549                 };
1550
1551                 uarthdcp {
1552                         uarthdcp_xfer: uarthdcp-xfer {
1553                                 rockchip,pins =
1554                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1555                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1556                         };
1557                 };
1558
1559                 pwm0 {
1560                         pwm0_pin: pwm0-pin {
1561                                 rockchip,pins =
1562                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1563                         };
1564
1565                         vop0_pwm_pin: vop0-pwm-pin {
1566                                 rockchip,pins =
1567                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1568                         };
1569                 };
1570
1571                 pwm1 {
1572                         pwm1_pin: pwm1-pin {
1573                                 rockchip,pins =
1574                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1575                         };
1576
1577                         vop1_pwm_pin: vop1-pwm-pin {
1578                                 rockchip,pins =
1579                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1580                         };
1581                 };
1582
1583                 pwm2 {
1584                         pwm2_pin: pwm2-pin {
1585                                 rockchip,pins =
1586                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1587                         };
1588                 };
1589
1590                 pwm3a {
1591                         pwm3a_pin: pwm3a-pin {
1592                                 rockchip,pins =
1593                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1594                         };
1595                 };
1596
1597                 pwm3b {
1598                         pwm3b_pin: pwm3b-pin {
1599                                 rockchip,pins =
1600                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1601                         };
1602                 };
1603
1604                 pmic {
1605                         pmic_int_l: pmic-int-l {
1606                                 rockchip,pins =
1607                                         <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
1608                         };
1609                 };
1610         };
1611 };