2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
75 compatible = "arm,psci-1.0";
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 clocks = <&cru ARMCLKL>;
116 operating-points-v2 = <&cluster0_opp>;
121 compatible = "arm,cortex-a53", "arm,armv8";
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 operating-points-v2 = <&cluster0_opp>;
130 compatible = "arm,cortex-a53", "arm,armv8";
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster0_opp>;
148 compatible = "arm,cortex-a72", "arm,armv8";
150 enable-method = "psci";
151 #cooling-cells = <2>; /* min followed by max */
152 clocks = <&cru ARMCLKB>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a72", "arm,armv8";
160 enable-method = "psci";
161 clocks = <&cru ARMCLKB>;
162 operating-points-v2 = <&cluster1_opp>;
166 cluster0_opp: opp_table0 {
167 compatible = "operating-points-v2";
171 opp-hz = /bits/ 64 <408000000>;
172 opp-microvolt = <900000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <600000000>;
177 opp-microvolt = <900000>;
180 opp-hz = /bits/ 64 <816000000>;
181 opp-microvolt = <900000>;
184 opp-hz = /bits/ 64 <1008000000>;
185 opp-microvolt = <900000>;
189 cluster1_opp: opp_table1 {
190 compatible = "operating-points-v2";
194 opp-hz = /bits/ 64 <408000000>;
195 opp-microvolt = <900000>;
196 clock-latency-ns = <40000>;
199 opp-hz = /bits/ 64 <600000000>;
200 opp-microvolt = <900000>;
203 opp-hz = /bits/ 64 <816000000>;
204 opp-microvolt = <900000>;
207 opp-hz = /bits/ 64 <1008000000>;
208 opp-microvolt = <900000>;
211 opp-hz = /bits/ 64 <1200000000>;
212 opp-microvolt = <900000>;
217 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
219 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
220 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
221 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
225 compatible = "arm,armv8-pmuv3";
226 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
230 compatible = "fixed-clock";
232 clock-frequency = <24000000>;
233 clock-output-names = "xin24m";
237 compatible = "arm,amba-bus";
238 #address-cells = <2>;
242 dmac_bus: dma-controller@ff6d0000 {
243 compatible = "arm,pl330", "arm,primecell";
244 reg = <0x0 0xff6d0000 0x0 0x4000>;
245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cru ACLK_DMAC0_PERILP>;
249 clock-names = "apb_pclk";
252 dmac_peri: dma-controller@ff6e0000 {
253 compatible = "arm,pl330", "arm,primecell";
254 reg = <0x0 0xff6e0000 0x0 0x4000>;
255 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cru ACLK_DMAC1_PERILP>;
259 clock-names = "apb_pclk";
264 compatible = "rockchip,rk3399-gmac";
265 reg = <0x0 0xfe300000 0x0 0x10000>;
266 rockchip,grf = <&grf>;
267 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-names = "macirq";
269 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
270 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
271 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
273 clock-names = "stmmaceth", "mac_clk_rx",
274 "mac_clk_tx", "clk_mac_ref",
275 "clk_mac_refout", "aclk_mac",
277 resets = <&cru SRST_A_GMAC>;
278 reset-names = "stmmaceth";
283 compatible = "rockchip,rk3399-emmc-phy";
284 reg-offset = <0xf780>;
286 rockchip,grf = <&grf>;
290 sdio0: dwmmc@fe310000 {
291 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
292 reg = <0x0 0xfe310000 0x0 0x4000>;
293 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
294 clock-freq-min-max = <400000 150000000>;
295 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
296 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
297 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
298 fifo-depth = <0x100>;
302 sdmmc: dwmmc@fe320000 {
303 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
304 reg = <0x0 0xfe320000 0x0 0x4000>;
305 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
306 clock-freq-min-max = <400000 150000000>;
307 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
308 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
309 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
310 fifo-depth = <0x100>;
314 sdhci: sdhci@fe330000 {
315 compatible = "arasan,sdhci-5.1";
316 reg = <0x0 0xfe330000 0x0 0x10000>;
317 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
319 clock-names = "clk_xin", "clk_ahb";
321 phy-names = "phy_arasan";
326 compatible = "rockchip,rk3399-usb-phy";
327 rockchip,grf = <&grf>;
328 #address-cells = <1>;
331 usb2phy0: usb2-phy0 {
337 usb2phy1: usb2-phy1 {
344 usb_host0_echi: usb@fe380000 {
345 compatible = "generic-ehci";
346 reg = <0x0 0xfe380000 0x0 0x20000>;
347 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
349 clock-names = "hclk_host0", "hclk_host0_arb";
351 phy-names = "usb2_phy0";
355 usb_host0_ohci: usb@fe3a0000 {
356 compatible = "generic-ohci";
357 reg = <0x0 0xfe3a0000 0x0 0x20000>;
358 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
360 clock-names = "hclk_host0", "hclk_host0_arb";
364 usb_host1_echi: usb@fe3c0000 {
365 compatible = "generic-ehci";
366 reg = <0x0 0xfe3c0000 0x0 0x20000>;
367 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
369 clock-names = "hclk_host1", "hclk_host1_arb";
371 phy-names = "usb2_phy1";
375 usb_host1_ohci: usb@fe3e0000 {
376 compatible = "generic-ohci";
377 reg = <0x0 0xfe3e0000 0x0 0x20000>;
378 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
380 clock-names = "hclk_host1", "hclk_host1_arb";
384 usbdrd3_0: usb@fe800000 {
385 compatible = "rockchip,dwc3";
386 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
387 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
388 <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
389 <&cru ACLK_USB3_GRF>;
390 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
391 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
392 "aclk_usb3", "aclk_usb3_noc",
394 #address-cells = <2>;
398 usbdrd_dwc3_0: dwc3 {
399 compatible = "snps,dwc3";
400 reg = <0x0 0xfe800000 0x0 0x100000>;
401 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
404 snps,dis_enblslpm_quirk;
405 snps,phyif_utmi_16_bits;
406 snps,dis_u2_freeclk_exists_quirk;
407 snps,dis_del_phy_power_chg_quirk;
412 usbdrd3_1: usb@fe900000 {
413 compatible = "rockchip,dwc3";
414 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
415 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
416 <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
417 <&cru ACLK_USB3_GRF>;
418 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
419 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
420 "aclk_usb3", "aclk_usb3_noc",
422 #address-cells = <2>;
426 usbdrd_dwc3_1: dwc3 {
427 compatible = "snps,dwc3";
428 reg = <0x0 0xfe900000 0x0 0x100000>;
429 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
432 snps,dis_enblslpm_quirk;
433 snps,phyif_utmi_16_bits;
434 snps,dis_u2_freeclk_exists_quirk;
435 snps,dis_del_phy_power_chg_quirk;
440 gic: interrupt-controller@fee00000 {
441 compatible = "arm,gic-v3";
442 #interrupt-cells = <3>;
443 #address-cells = <2>;
446 interrupt-controller;
448 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
449 <0x0 0xfef00000 0 0xc0000>, /* GICR */
450 <0x0 0xfff00000 0 0x10000>, /* GICC */
451 <0x0 0xfff10000 0 0x10000>, /* GICH */
452 <0x0 0xfff20000 0 0x10000>; /* GICV */
453 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
454 its: interrupt-controller@fee20000 {
455 compatible = "arm,gic-v3-its";
457 reg = <0x0 0xfee20000 0x0 0x20000>;
461 saradc: saradc@ff100000 {
462 compatible = "rockchip,rk3399-saradc";
463 reg = <0x0 0xff100000 0x0 0x100>;
464 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
465 #io-channel-cells = <1>;
466 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
467 clock-names = "saradc", "apb_pclk";
472 compatible = "rockchip,rk3399-i2c";
473 reg = <0x0 0xff3c0000 0x0 0x1000>;
474 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
475 clock-names = "i2c", "pclk";
476 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2c0_xfer>;
479 #address-cells = <1>;
485 compatible = "rockchip,rk3399-i2c";
486 reg = <0x0 0xff110000 0x0 0x1000>;
487 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
488 clock-names = "i2c", "pclk";
489 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&i2c1_xfer>;
492 #address-cells = <1>;
498 compatible = "rockchip,rk3399-i2c";
499 reg = <0x0 0xff120000 0x0 0x1000>;
500 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
501 clock-names = "i2c", "pclk";
502 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&i2c2_xfer>;
505 #address-cells = <1>;
511 compatible = "rockchip,rk3399-i2c";
512 reg = <0x0 0xff130000 0x0 0x1000>;
513 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
514 clock-names = "i2c", "pclk";
515 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&i2c3_xfer>;
518 #address-cells = <1>;
524 compatible = "rockchip,rk3399-i2c";
525 reg = <0x0 0xff140000 0x0 0x1000>;
526 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
527 clock-names = "i2c", "pclk";
528 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2c5_xfer>;
531 #address-cells = <1>;
537 compatible = "rockchip,rk3399-i2c";
538 reg = <0x0 0xff150000 0x0 0x1000>;
539 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
540 clock-names = "i2c", "pclk";
541 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&i2c6_xfer>;
544 #address-cells = <1>;
550 compatible = "rockchip,rk3399-i2c";
551 reg = <0x0 0xff160000 0x0 0x1000>;
552 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
553 clock-names = "i2c", "pclk";
554 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2c7_xfer>;
557 #address-cells = <1>;
562 uart0: serial@ff180000 {
563 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
564 reg = <0x0 0xff180000 0x0 0x100>;
565 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
566 clock-names = "baudclk", "apb_pclk";
567 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
575 uart1: serial@ff190000 {
576 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
577 reg = <0x0 0xff190000 0x0 0x100>;
578 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
579 clock-names = "baudclk", "apb_pclk";
580 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&uart1_xfer>;
588 uart2: serial@ff1a0000 {
589 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
590 reg = <0x0 0xff1a0000 0x0 0x100>;
591 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
592 clock-names = "baudclk", "apb_pclk";
593 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&uart2c_xfer>;
601 uart3: serial@ff1b0000 {
602 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
603 reg = <0x0 0xff1b0000 0x0 0x100>;
604 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
605 clock-names = "baudclk", "apb_pclk";
606 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
615 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
616 reg = <0x0 0xff1c0000 0x0 0x1000>;
617 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
618 clock-names = "spiclk", "apb_pclk";
619 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
622 #address-cells = <1>;
628 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
629 reg = <0x0 0xff1d0000 0x0 0x1000>;
630 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
631 clock-names = "spiclk", "apb_pclk";
632 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
633 pinctrl-names = "default";
634 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
635 #address-cells = <1>;
641 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
642 reg = <0x0 0xff1e0000 0x0 0x1000>;
643 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
644 clock-names = "spiclk", "apb_pclk";
645 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
648 #address-cells = <1>;
654 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
655 reg = <0x0 0xff1f0000 0x0 0x1000>;
656 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
657 clock-names = "spiclk", "apb_pclk";
658 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
661 #address-cells = <1>;
667 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
668 reg = <0x0 0xff200000 0x0 0x1000>;
669 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
670 clock-names = "spiclk", "apb_pclk";
671 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
674 #address-cells = <1>;
680 #include "rk3368-thermal.dtsi"
683 tsadc: tsadc@ff260000 {
684 compatible = "rockchip,rk3399-tsadc";
685 reg = <0x0 0xff260000 0x0 0x100>;
686 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
687 rockchip,grf = <&grf>;
688 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
689 clock-names = "tsadc", "apb_pclk";
690 assigned-clocks = <&cru SCLK_TSADC>;
691 assigned-clock-rates = <750000>;
692 resets = <&cru SRST_TSADC>;
693 reset-names = "tsadc-apb";
694 pinctrl-names = "init", "default", "sleep";
695 pinctrl-0 = <&otp_gpio>;
696 pinctrl-1 = <&otp_out>;
697 pinctrl-2 = <&otp_gpio>;
698 #thermal-sensor-cells = <1>;
699 rockchip,hw-tshut-temp = <95000>;
703 pmu: power-management@ff31000 {
704 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
705 reg = <0x0 0xff310000 0x0 0x1000>;
707 power: power-controller {
709 compatible = "rockchip,rk3399-power-controller";
710 #power-domain-cells = <1>;
711 #address-cells = <1>;
715 reg = <RK3399_PD_CENTER>;
716 #address-cells = <1>;
720 reg = <RK3399_PD_VDU>;
723 reg = <RK3399_PD_VCODEC>;
726 reg = <RK3399_PD_IEP>;
729 reg = <RK3399_PD_RGA>;
733 reg = <RK3399_PD_VIO>;
734 #address-cells = <1>;
738 reg = <RK3399_PD_ISP0>;
741 reg = <RK3399_PD_ISP1>;
744 reg = <RK3399_PD_HDCP>;
747 reg = <RK3399_PD_VO>;
748 #address-cells = <1>;
752 reg = <RK3399_PD_VOPB>;
755 reg = <RK3399_PD_VOPL>;
760 reg = <RK3399_PD_GPU>;
765 pmugrf: syscon@ff320000 {
766 compatible = "rockchip,rk3399-pmugrf", "syscon";
767 reg = <0x0 0xff320000 0x0 0x1000>;
771 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
772 reg = <0x0 0xff350000 0x0 0x1000>;
773 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
774 clock-names = "spiclk", "apb_pclk";
775 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
776 pinctrl-names = "default";
777 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
778 #address-cells = <1>;
783 uart4: serial@ff370000 {
784 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
785 reg = <0x0 0xff370000 0x0 0x100>;
786 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
787 clock-names = "baudclk", "apb_pclk";
788 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
791 pinctrl-names = "default";
792 pinctrl-0 = <&uart4_xfer>;
797 compatible = "rockchip,rk3399-i2c";
798 reg = <0x0 0xff3d0000 0x0 0x1000>;
799 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
800 clock-names = "i2c", "pclk";
801 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
802 pinctrl-names = "default";
803 pinctrl-0 = <&i2c4_xfer>;
804 #address-cells = <1>;
810 compatible = "rockchip,rk3399-i2c";
811 reg = <0x0 0xff3e0000 0x0 0x1000>;
812 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
813 clock-names = "i2c", "pclk";
814 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
815 pinctrl-names = "default";
816 pinctrl-0 = <&i2c8_xfer>;
817 #address-cells = <1>;
823 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
824 reg = <0x0 0xff420000 0x0 0x10>;
826 pinctrl-names = "default";
827 pinctrl-0 = <&pwm0_pin>;
828 clocks = <&pmucru PCLK_RKPWM_PMU>;
834 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
835 reg = <0x0 0xff420010 0x0 0x10>;
837 pinctrl-names = "default";
838 pinctrl-0 = <&pwm1_pin>;
839 clocks = <&pmucru PCLK_RKPWM_PMU>;
845 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
846 reg = <0x0 0xff420020 0x0 0x10>;
848 pinctrl-names = "default";
849 pinctrl-0 = <&pwm2_pin>;
850 clocks = <&pmucru PCLK_RKPWM_PMU>;
856 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
857 reg = <0x0 0xff420030 0x0 0x10>;
859 pinctrl-names = "default";
860 pinctrl-0 = <&pwm3a_pin>;
861 clocks = <&pmucru PCLK_RKPWM_PMU>;
866 pmucru: pmu-clock-controller@ff750000 {
867 compatible = "rockchip,rk3399-pmucru";
868 reg = <0x0 0xff750000 0x0 0x1000>;
871 assigned-clocks = <&pmucru PLL_PPLL>;
872 assigned-clock-rates = <676000000>;
875 cru: clock-controller@ff760000 {
876 compatible = "rockchip,rk3399-cru";
877 reg = <0x0 0xff760000 0x0 0x1000>;
881 <&cru ARMCLKL>, <&cru ARMCLKB>,
882 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
884 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
886 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
888 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
889 assigned-clock-rates =
890 <816000000>, <1008000000>,
891 <594000000>, <800000000>,
893 <150000000>, <75000000>,
895 <100000000>, <100000000>,
897 <100000000>, <50000000>;
900 grf: syscon@ff770000 {
901 compatible = "rockchip,rk3399-grf", "syscon";
902 reg = <0x0 0xff770000 0x0 0x10000>;
905 wdt0: watchdog@ff840000 {
906 compatible = "snps,dw-wdt";
907 reg = <0x0 0xff840000 0x0 0x100>;
908 clocks = <&cru PCLK_WDT>;
909 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
913 spdif: spdif@ff870000 {
914 compatible = "rockchip,rk3399-spdif";
915 reg = <0x0 0xff870000 0x0 0x1000>;
916 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
917 dmas = <&dmac_bus 7>;
919 clock-names = "mclk", "hclk";
920 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&spdif_bus>;
927 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
928 reg = <0x0 0xff880000 0x0 0x1000>;
929 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
930 #address-cells = <1>;
932 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
933 dma-names = "tx", "rx";
934 clock-names = "i2s_clk", "i2s_hclk";
935 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
936 pinctrl-names = "default";
937 pinctrl-0 = <&i2s0_8ch_bus>;
942 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
943 reg = <0x0 0xff890000 0x0 0x1000>;
944 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
945 #address-cells = <1>;
947 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
948 dma-names = "tx", "rx";
949 clock-names = "i2s_clk", "i2s_hclk";
950 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
951 pinctrl-names = "default";
952 pinctrl-0 = <&i2s1_2ch_bus>;
957 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
958 reg = <0x0 0xff8a0000 0x0 0x1000>;
959 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
960 #address-cells = <1>;
962 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
963 dma-names = "tx", "rx";
964 clock-names = "i2s_clk", "i2s_hclk";
965 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
970 compatible = "arm,malit860",
975 reg = <0x0 0xff9a0000 0x0 0x10000>;
977 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
980 interrupt-names = "GPU", "JOB", "MMU";
982 clocks = <&cru ACLK_GPU>;
983 clock-names = "clk_mali";
984 operating-points-v2 = <&gpu_opp_table>;
988 gpu_opp_table: gpu_opp_table {
989 compatible = "operating-points-v2";
993 opp-hz = /bits/ 64 <200000000>;
994 opp-microvolt = <900000>;
997 opp-hz = /bits/ 64 <300000000>;
998 opp-microvolt = <900000>;
1001 opp-hz = /bits/ 64 <400000000>;
1002 opp-microvolt = <900000>;
1005 opp-hz = /bits/ 64 <500000000>;
1006 opp-microvolt = <900000>;
1010 vopl: vop@ff8f0000 {
1011 compatible = "rockchip,rk3399-vop-lit";
1012 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1013 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1015 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1016 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1017 reset-names = "axi", "ahb", "dclk";
1018 iommus = <&vopl_mmu>;
1019 status = "disabled";
1022 #address-cells = <1>;
1025 vopl_out_mipi: endpoint@1 {
1027 remote-endpoint = <&mipi_in_vopl>;
1032 vopl_mmu: iommu@ff8f3f00 {
1033 compatible = "rockchip,iommu";
1034 reg = <0x0 0xff8f3f00 0x0 0x100>;
1035 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1036 interrupt-names = "vopl_mmu";
1038 status = "disabled";
1041 vopb: vop@ff900000 {
1042 compatible = "rockchip,rk3399-vop-big";
1043 reg = <0x0 0xff900000 0x0 0x3efc>;
1044 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1046 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1047 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1048 reset-names = "axi", "ahb", "dclk";
1049 iommus = <&vopb_mmu>;
1050 status = "disabled";
1053 #address-cells = <1>;
1056 vopb_out_mipi: endpoint@1 {
1058 remote-endpoint = <&mipi_in_vopb>;
1063 vopb_mmu: iommu@ff903f00 {
1064 compatible = "rockchip,iommu";
1065 reg = <0x0 0xff903f00 0x0 0x100>;
1066 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1067 interrupt-names = "vopb_mmu";
1069 status = "disabled";
1072 mipi_dsi: mipi@ff960000 {
1073 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1074 reg = <0x0 0xff960000 0x0 0x8000>;
1075 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1077 <&cru SCLK_DPHY_TX0_CFG>;
1078 clock-names = "ref", "pclk", "phy_cfg";
1079 rockchip,grf = <&grf>;
1080 #address-cells = <1>;
1082 status = "disabled";
1085 #address-cells = <1>;
1090 #address-cells = <1>;
1093 mipi_in_vopb: endpoint@0 {
1095 remote-endpoint = <&vopb_out_mipi>;
1097 mipi_in_vopl: endpoint@1 {
1099 remote-endpoint = <&vopl_out_mipi>;
1105 display_subsystem: display-subsystem {
1106 compatible = "rockchip,display-subsystem";
1107 ports = <&vopl_out>, <&vopb_out>;
1108 status = "disabled";
1112 compatible = "rockchip,rk3399-pinctrl";
1113 rockchip,grf = <&grf>;
1114 rockchip,pmu = <&pmugrf>;
1115 #address-cells = <0x2>;
1116 #size-cells = <0x2>;
1119 gpio0: gpio0@ff720000 {
1120 compatible = "rockchip,gpio-bank";
1121 reg = <0x0 0xff720000 0x0 0x100>;
1122 clocks = <&pmucru PCLK_GPIO0_PMU>;
1123 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1126 #gpio-cells = <0x2>;
1128 interrupt-controller;
1129 #interrupt-cells = <0x2>;
1132 gpio1: gpio1@ff730000 {
1133 compatible = "rockchip,gpio-bank";
1134 reg = <0x0 0xff730000 0x0 0x100>;
1135 clocks = <&pmucru PCLK_GPIO1_PMU>;
1136 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1139 #gpio-cells = <0x2>;
1141 interrupt-controller;
1142 #interrupt-cells = <0x2>;
1145 gpio2: gpio2@ff780000 {
1146 compatible = "rockchip,gpio-bank";
1147 reg = <0x0 0xff780000 0x0 0x100>;
1148 clocks = <&cru PCLK_GPIO2>;
1149 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1152 #gpio-cells = <0x2>;
1154 interrupt-controller;
1155 #interrupt-cells = <0x2>;
1158 gpio3: gpio3@ff788000 {
1159 compatible = "rockchip,gpio-bank";
1160 reg = <0x0 0xff788000 0x0 0x100>;
1161 clocks = <&cru PCLK_GPIO3>;
1162 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1165 #gpio-cells = <0x2>;
1167 interrupt-controller;
1168 #interrupt-cells = <0x2>;
1171 gpio4: gpio4@ff790000 {
1172 compatible = "rockchip,gpio-bank";
1173 reg = <0x0 0xff790000 0x0 0x100>;
1174 clocks = <&cru PCLK_GPIO4>;
1175 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1178 #gpio-cells = <0x2>;
1180 interrupt-controller;
1181 #interrupt-cells = <0x2>;
1184 pcfg_pull_up: pcfg-pull-up {
1188 pcfg_pull_down: pcfg-pull-down {
1192 pcfg_pull_none: pcfg-pull-none {
1196 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1198 drive-strength = <12>;
1201 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1203 drive-strength = <8>;
1206 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1208 drive-strength = <4>;
1211 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1213 drive-strength = <2>;
1216 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1218 drive-strength = <12>;
1222 emmc_pwr: emmc-pwr {
1224 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1229 rgmii_pins: rgmii-pins {
1232 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1234 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1236 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1238 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1240 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1242 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1244 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1246 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1248 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1250 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1252 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1254 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1256 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1258 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1260 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
1263 rmii_pins: rmii-pins {
1266 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1268 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1270 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1272 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1274 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1276 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1278 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1280 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1282 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1284 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
1289 i2c0_xfer: i2c0-xfer {
1291 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1292 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1297 i2c1_xfer: i2c1-xfer {
1299 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1300 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1305 i2c2_xfer: i2c2-xfer {
1307 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1308 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1313 i2c3_xfer: i2c3-xfer {
1315 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1316 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1321 i2c4_xfer: i2c4-xfer {
1323 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1324 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1329 i2c5_xfer: i2c5-xfer {
1331 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1332 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1337 i2c6_xfer: i2c6-xfer {
1339 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1340 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1345 i2c7_xfer: i2c7-xfer {
1347 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1348 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1353 i2c8_xfer: i2c8-xfer {
1355 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1356 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1361 i2s0_8ch_bus: i2s0-8ch-bus {
1363 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1364 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1365 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1366 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1367 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1368 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1369 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1370 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1371 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1376 i2s1_2ch_bus: i2s1-2ch-bus {
1378 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1379 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1380 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1381 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1382 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1387 sdio0_bus1: sdio0-bus1 {
1389 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1392 sdio0_bus4: sdio0-bus4 {
1394 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1395 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1396 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1397 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1400 sdio0_cmd: sdio0-cmd {
1402 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1405 sdio0_clk: sdio0-clk {
1407 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1410 sdio0_cd: sdio0-cd {
1412 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1415 sdio0_pwr: sdio0-pwr {
1417 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1420 sdio0_bkpwr: sdio0-bkpwr {
1422 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1425 sdio0_wp: sdio0-wp {
1427 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1430 sdio0_int: sdio0-int {
1432 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1437 sdmmc_bus1: sdmmc-bus1 {
1439 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1442 sdmmc_bus4: sdmmc-bus4 {
1444 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1445 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1446 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1447 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1450 sdmmc_clk: sdmmc-clk {
1452 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1455 sdmmc_cmd: sdmmc-cmd {
1457 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1460 sdmmc_cd: sdmcc-cd {
1462 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1465 sdmmc_wp: sdmmc-wp {
1467 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1472 spdif_bus: spdif-bus {
1474 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1479 spi0_clk: spi0-clk {
1481 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1483 spi0_cs0: spi0-cs0 {
1485 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1487 spi0_cs1: spi0-cs1 {
1489 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1493 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1497 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1502 spi1_clk: spi1-clk {
1504 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1506 spi1_cs0: spi1-cs0 {
1508 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1512 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1516 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1521 spi2_clk: spi2-clk {
1523 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1525 spi2_cs0: spi2-cs0 {
1527 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1531 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1535 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1540 spi3_clk: spi3-clk {
1542 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1544 spi3_cs0: spi3-cs0 {
1546 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1550 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1554 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1559 spi4_clk: spi4-clk {
1561 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1563 spi4_cs0: spi4-cs0 {
1565 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1569 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1573 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1578 spi5_clk: spi5-clk {
1580 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1582 spi5_cs0: spi5-cs0 {
1584 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1588 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1592 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1597 otp_gpio: otp-gpio {
1598 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1602 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1607 uart0_xfer: uart0-xfer {
1609 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1610 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1613 uart0_cts: uart0-cts {
1615 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1618 uart0_rts: uart0-rts {
1620 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1625 uart1_xfer: uart1-xfer {
1627 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1628 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1633 uart2a_xfer: uart2a-xfer {
1635 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1636 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1641 uart2b_xfer: uart2b-xfer {
1643 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1644 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1649 uart2c_xfer: uart2c-xfer {
1651 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1652 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1657 uart3_xfer: uart3-xfer {
1659 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1660 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1663 uart3_cts: uart3-cts {
1665 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1668 uart3_rts: uart3-rts {
1670 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1675 uart4_xfer: uart4-xfer {
1677 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1678 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1683 uarthdcp_xfer: uarthdcp-xfer {
1685 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1686 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1691 pwm0_pin: pwm0-pin {
1693 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1696 vop0_pwm_pin: vop0-pwm-pin {
1698 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1703 pwm1_pin: pwm1-pin {
1705 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1708 vop1_pwm_pin: vop1-pwm-pin {
1710 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1715 pwm2_pin: pwm2-pin {
1717 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1722 pwm3a_pin: pwm3a-pin {
1724 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1729 pwm3b_pin: pwm3b-pin {
1731 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1736 pmic_int_l: pmic-int-l {
1738 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;