arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71         };
  72
  73         cpus {
  74                 #address-cells = <2>;
  75                 #size-cells = <0>;
  76
  77                 cpu-map {
  78                         cluster0 {
  79                                 core0 {
  80                                         cpu = <&cpu_l0>;
  81                                 };
  82                                 core1 {
  83                                         cpu = <&cpu_l1>;
  84                                 };
  85                                 core2 {
  86                                         cpu = <&cpu_l2>;
  87                                 };
  88                                 core3 {
  89                                         cpu = <&cpu_l3>;
  90                                 };
  91                         };
  92
  93                         cluster1 {
  94                                 core0 {
  95                                         cpu = <&cpu_b0>;
  96                                 };
  97                                 core1 {
  98                                         cpu = <&cpu_b1>;
  99                                 };
 100                         };
 101                 };
 102
 103                 cpu_l0: cpu@0 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a53", "arm,armv8";
 106                         reg = <0x0 0x0>;
 107
 108                         #cooling-cells = <2>; /* min followed by max */
 109                 };
 110
 111                 cpu_l1: cpu@1 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x1>;
 115                 };
 116
 117                 cpu_l2: cpu@2 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a53", "arm,armv8";
 120                         reg = <0x0 0x2>;
 121                 };
 122
 123                 cpu_l3: cpu@3 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a53", "arm,armv8";
 126                         reg = <0x0 0x3>;
 127                 };
 128
 129                 cpu_b0: cpu@100 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a72", "arm,armv8";
 132                         reg = <0x0 0x100>;
 133
 134                         #cooling-cells = <2>; /* min followed by max */
 135                 };
 136
 137                 cpu_b1: cpu@101 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a72", "arm,armv8";
 140                         reg = <0x0 0x101>;
 141                 };
 142         };
 143
 144         timer {
 145                 compatible = "arm,armv8-timer";
 146                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 150         };
 151
 152         xin24m: xin24m {
 153                 compatible = "fixed-clock";
 154                 #clock-cells = <0>;
 155                 clock-frequency = <24000000>;
 156                 clock-output-names = "xin24m";
 157         };
 158
 159         gic: interrupt-controller@fee00000 {
 160                 compatible = "arm,gic-v3";
 161                 #interrupt-cells = <3>;
 162                 #address-cells = <2>;
 163                 #size-cells = <2>;
 164                 ranges;
 165                 interrupt-controller;
 166
 167                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 168                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 169                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 170                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 171                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 172                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 173                 its: interrupt-controller@fee20000 {
 174                         compatible = "arm,gic-v3-its";
 175                         msi-controller;
 176                         reg = <0x0 0xfee20000 0x0 0x20000>;
 177                 };
 178         };
 179
 180         amba {
 181                 compatible = "arm,amba-bus";
 182                 #address-cells = <2>;
 183                 #size-cells = <2>;
 184                 ranges;
 185
 186                 dmac_bus: dma-controller@ff6d0000 {
 187                         compatible = "arm,pl330", "arm,primecell";
 188                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 189                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 190                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 191                         #dma-cells = <1>;
 192                         clocks = <&cru ACLK_DMAC0_PERILP>;
 193                         clock-names = "apb_pclk";
 194                 };
 195
 196                 dmac_peri: dma-controller@ff6e0000 {
 197                         compatible = "arm,pl330", "arm,primecell";
 198                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 199                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 201                         #dma-cells = <1>;
 202                         clocks = <&cru ACLK_DMAC1_PERILP>;
 203                         clock-names = "apb_pclk";
 204                 };
 205         };
 206
 207         saradc: saradc@ff100000 {
 208                 compatible = "rockchip,rk3399-saradc";
 209                 reg = <0x0 0xff100000 0x0 0x100>;
 210                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 211                 #io-channel-cells = <1>;
 212                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 213                 clock-names = "saradc", "apb_pclk";
 214                 status = "disabled";
 215         };
 216
 217         i2c0: i2c@ff3c0000 {
 218                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 219                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 220                 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
 221                 clock-names = "i2c", "i2c_sclk";
 222                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&i2c0_xfer>;
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 status = "disabled";
 228         };
 229
 230         i2c1: i2c@ff110000 {
 231                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 232                 reg = <0x0 0xff110000 0x0 0x1000>;
 233                 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
 234                 clock-names = "i2c", "i2c_sclk";
 235                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 236                 pinctrl-names = "default";
 237                 pinctrl-0 = <&i2c1_xfer>;
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 status = "disabled";
 241         };
 242
 243         i2c2: i2c@ff120000 {
 244                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 245                 reg = <0x0 0xff120000 0x0 0x1000>;
 246                 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
 247                 clock-names = "i2c", "i2c_sclk";
 248                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 249                 pinctrl-names = "default";
 250                 pinctrl-0 = <&i2c2_xfer>;
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 status = "disabled";
 254         };
 255
 256         i2c3: i2c@ff130000 {
 257                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 258                 reg = <0x0 0xff130000 0x0 0x1000>;
 259                 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
 260                 clock-names = "i2c", "i2c_sclk";
 261                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 262                 pinctrl-names = "default";
 263                 pinctrl-0 = <&i2c3_xfer>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 status = "disabled";
 267         };
 268
 269         i2c5: i2c@ff140000 {
 270                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 271                 reg = <0x0 0xff140000 0x0 0x1000>;
 272                 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
 273                 clock-names = "i2c", "i2c_sclk";
 274                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 275                 pinctrl-names = "default";
 276                 pinctrl-0 = <&i2c5_xfer>;
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 status = "disabled";
 280         };
 281
 282         i2c6: i2c@ff150000 {
 283                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 284                 reg = <0x0 0xff150000 0x0 0x1000>;
 285                 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
 286                 clock-names = "i2c", "i2c_sclk";
 287                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 288                 pinctrl-names = "default";
 289                 pinctrl-0 = <&i2c6_xfer>;
 290                 #address-cells = <1>;
 291                 #size-cells = <0>;
 292                 status = "disabled";
 293         };
 294
 295         i2c7: i2c@ff160000 {
 296                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 297                 reg = <0x0 0xff160000 0x0 0x1000>;
 298                 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
 299                 clock-names = "i2c", "i2c_sclk";
 300                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 301                 pinctrl-names = "default";
 302                 pinctrl-0 = <&i2c7_xfer>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 status = "disabled";
 306         };
 307
 308         emmc_phy: phy {
 309                 compatible = "rockchip,rk3399-emmc-phy";
 310                 reg-offset = <0xf780>;
 311                 #phy-cells = <0>;
 312                 rockchip,grf = <&grf>;
 313                 status = "disabled";
 314         };
 315
 316         sdio0: dwmmc@fe310000 {
 317                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 318                 reg = <0x0 0xfe310000 0x0 0x4000>;
 319                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 320                 clock-freq-min-max = <400000 150000000>;
 321                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 322                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 323                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 324                 fifo-depth = <0x100>;
 325                 status = "disabled";
 326         };
 327
 328         sdmmc: dwmmc@fe320000 {
 329                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 330                 reg = <0x0 0xfe320000 0x0 0x4000>;
 331                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 332                 clock-freq-min-max = <400000 150000000>;
 333                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 334                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 335                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 336                 fifo-depth = <0x100>;
 337                 status = "disabled";
 338         };
 339
 340         sdhci: sdhci@fe330000 {
 341                 compatible = "arasan,sdhci-5.1";
 342                 reg = <0x0 0xfe330000 0x0 0x10000>;
 343                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 344                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 345                 clock-names = "clk_xin", "clk_ahb";
 346                 phys = <&emmc_phy>;
 347                 phy-names = "phy_arasan";
 348                 status = "disabled";
 349         };
 350
 351         uart0: serial@ff180000 {
 352                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 353                 reg = <0x0 0xff180000 0x0 0x100>;
 354                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 355                 clock-names = "baudclk", "apb_pclk";
 356                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 357                 reg-shift = <2>;
 358                 reg-io-width = <4>;
 359                 status = "disabled";
 360         };
 361
 362         uart1: serial@ff190000 {
 363                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 364                 reg = <0x0 0xff190000 0x0 0x100>;
 365                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 366                 clock-names = "baudclk", "apb_pclk";
 367                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 368                 reg-shift = <2>;
 369                 reg-io-width = <4>;
 370                 status = "disabled";
 371         };
 372
 373         uart2: serial@ff1a0000 {
 374                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 375                 reg = <0x0 0xff1a0000 0x0 0x100>;
 376                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 377                 clock-names = "baudclk", "apb_pclk";
 378                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 379                 reg-shift = <2>;
 380                 reg-io-width = <4>;
 381                 status = "disabled";
 382         };
 383
 384         uart3: serial@ff1b0000 {
 385                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 386                 reg = <0x0 0xff1b0000 0x0 0x100>;
 387                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 388                 clock-names = "baudclk", "apb_pclk";
 389                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 390                 reg-shift = <2>;
 391                 reg-io-width = <4>;
 392                 status = "disabled";
 393         };
 394
 395         spi0: spi@ff1c0000 {
 396                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 397                 reg = <0x0 0xff110000 0x0 0x1000>;
 398                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 399                 clock-names = "spiclk", "apb_pclk";
 400                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 status = "disabled";
 406         };
 407
 408         spi1: spi@ff1d0000 {
 409                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 410                 reg = <0x0 0xff120000 0x0 0x1000>;
 411                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 412                 clock-names = "spiclk", "apb_pclk";
 413                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 status = "disabled";
 419         };
 420
 421         spi2: spi@ff1e0000 {
 422                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 423                 reg = <0x0 0xff130000 0x0 0x1000>;
 424                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 425                 clock-names = "spiclk", "apb_pclk";
 426                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 status = "disabled";
 432         };
 433
 434         spi4: spi@ff1f0000 {
 435                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 436                 reg = <0x0 0xff120000 0x0 0x1000>;
 437                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 438                 clock-names = "spiclk", "apb_pclk";
 439                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 status = "disabled";
 445         };
 446
 447         spi5: spi@ff200000 {
 448                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 449                 reg = <0x0 0xff130000 0x0 0x1000>;
 450                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 451                 clock-names = "spiclk", "apb_pclk";
 452                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 status = "disabled";
 458         };
 459
 460         thermal-zones {
 461                 #include "rk3368-thermal.dtsi"
 462         };
 463
 464         tsadc: tsadc@ff260000 {
 465                 compatible = "rockchip,rk3399-tsadc";
 466                 reg = <0x0 0xff260000 0x0 0x100>;
 467                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 469                 clock-names = "tsadc", "apb_pclk";
 470                 resets = <&cru SRST_TSADC>;
 471                 reset-names = "tsadc-apb";
 472                 pinctrl-names = "init", "default", "sleep";
 473                 pinctrl-0 = <&otp_gpio>;
 474                 pinctrl-1 = <&otp_out>;
 475                 pinctrl-2 = <&otp_gpio>;
 476                 #thermal-sensor-cells = <1>;
 477                 rockchip,hw-tshut-temp = <95000>;
 478                 status = "disabled";
 479         };
 480
 481         pmugrf: syscon@ff320000 {
 482                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 483                 reg = <0x0 0xff320000 0x0 0x1000>;
 484         };
 485
 486         spi3: spi@ff350000 {
 487                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 488                 reg = <0x0 0xff110000 0x0 0x1000>;
 489                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 490                 clock-names = "spiclk", "apb_pclk";
 491                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 494                 #address-cells = <1>;
 495                 #size-cells = <0>;
 496                 status = "disabled";
 497         };
 498
 499         uart4: serial@ff370000 {
 500                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 501                 reg = <0x0 0xff370000 0x0 0x100>;
 502                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 503                 clock-names = "baudclk", "apb_pclk";
 504                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 505                 reg-shift = <2>;
 506                 reg-io-width = <4>;
 507                 status = "disabled";
 508         };
 509
 510         i2c4: i2c@ff3d0000 {
 511                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 512                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 513                 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
 514                 clock-names = "i2c", "i2c_sclk";
 515                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&i2c4_xfer>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 status = "disabled";
 521         };
 522
 523         i2c8: i2c@ff3e0000 {
 524                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 525                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 526                 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
 527                 clock-names = "i2c", "i2c_sclk";
 528                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 529                 pinctrl-names = "default";
 530                 pinctrl-0 = <&i2c8_xfer>;
 531                 #address-cells = <1>;
 532                 #size-cells = <0>;
 533                 status = "disabled";
 534         };
 535
 536         pwm0: pwm@ff420000 {
 537                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 538                 reg = <0x0 0xff420000 0x0 0x10>;
 539                 #pwm-cells = <3>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&pwm0_pin>;
 542                 clocks = <&cru PCLK_RKPWM_PMU>;
 543                 clock-names = "pwm";
 544                 status = "disabled";
 545         };
 546
 547         pwm1: pwm@ff420010 {
 548                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 549                 reg = <0x0 0xff420010 0x0 0x10>;
 550                 #pwm-cells = <3>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&pwm1_pin>;
 553                 clocks = <&cru PCLK_RKPWM_PMU>;
 554                 clock-names = "pwm";
 555                 status = "disabled";
 556         };
 557
 558         pwm2: pwm@ff420020 {
 559                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 560                 reg = <0x0 0xff420020 0x0 0x10>;
 561                 #pwm-cells = <3>;
 562                 pinctrl-names = "default";
 563                 pinctrl-0 = <&pwm2_pin>;
 564                 clocks = <&cru PCLK_RKPWM_PMU>;
 565                 clock-names = "pwm";
 566                 status = "disabled";
 567         };
 568
 569         pwm3: pwm@ff420030 {
 570                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 571                 reg = <0x0 0xff420030 0x0 0x10>;
 572                 #pwm-cells = <3>;
 573                 pinctrl-names = "default";
 574                 pinctrl-0 = <&pwm3a_pin>;
 575                 clocks = <&cru PCLK_RKPWM_PMU>;
 576                 clock-names = "pwm";
 577                 status = "disabled";
 578         };
 579
 580         pmu: power-management@ff731000 {
 581                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 582                 reg = <0x0 0xff310000 0x0 0x1000>;
 583
 584                 power: power-controller {
 585                         status = "disabled";
 586                         compatible = "rockchip,rk3399-power-controller";
 587                         #power-domain-cells = <1>;
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590
 591                         pd_center {
 592                                 reg = <RK3399_PD_CENTER>;
 593                                 #address-cells = <1>;
 594                                 #size-cells = <0>;
 595
 596                                 pd_vdu {
 597                                         reg = <RK3399_PD_VDU>;
 598                                 };
 599                                 pd_vcodec {
 600                                         reg = <RK3399_PD_VCODEC>;
 601                                 };
 602                                 pd_iep {
 603                                         reg = <RK3399_PD_IEP>;
 604                                 };
 605                                 pd_rga {
 606                                         reg = <RK3399_PD_RGA>;
 607                                 };
 608                         };
 609                         pd_vio {
 610                                 reg = <RK3399_PD_VIO>;
 611                                 #address-cells = <1>;
 612                                 #size-cells = <0>;
 613
 614                                 pd_isp0 {
 615                                         reg = <RK3399_PD_ISP0>;
 616                                 };
 617                                 pd_isp1 {
 618                                         reg = <RK3399_PD_ISP1>;
 619                                 };
 620                                 pd_hdcp {
 621                                         reg = <RK3399_PD_HDCP>;
 622                                 };
 623                                 pd_vo {
 624                                         reg = <RK3399_PD_VO>;
 625                                         #address-cells = <1>;
 626                                         #size-cells = <0>;
 627
 628                                         pd_vopb {
 629                                                 reg = <RK3399_PD_VOPB>;
 630                                         };
 631                                         pd_vopl {
 632                                                 reg = <RK3399_PD_VOPL>;
 633                                         };
 634                                 };
 635                         };
 636                         pd_gpu {
 637                                 reg = <RK3399_PD_GPU>;
 638                         };
 639                 };
 640         };
 641
 642         pmucru: pmu-clock-controller@ff750000 {
 643                 compatible = "rockchip,rk3399-pmucru";
 644                 reg = <0x0 0xff750000 0x0 0x1000>;
 645                 rockchip,grf = <&pmugrf>;
 646                 #clock-cells = <1>;
 647                 #reset-cells = <1>;
 648         };
 649
 650         cru: clock-controller@ff760000 {
 651                 compatible = "rockchip,rk3399-cru";
 652                 reg = <0x0 0xff760000 0x0 0x1000>;
 653                 rockchip,grf = <&grf>;
 654                 #clock-cells = <1>;
 655                 #reset-cells = <1>;
 656         };
 657
 658         grf: syscon@ff770000 {
 659                 compatible = "rockchip,rk3399-grf", "syscon";
 660                 reg = <0x0 0xff770000 0x0 0x10000>;
 661         };
 662
 663         spdif: spdif@ff870000 {
 664                 compatible = "rockchip,rk3399-spdif";
 665                 reg = <0x0 0xff870000 0x0 0x1000>;
 666                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 667                 dmas = <&dmac_bus 7>;
 668                 dma-names = "tx";
 669                 clock-names = "hclk", "mclk";
 670                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&spdif_bus>;
 673                 status = "disabled";
 674         };
 675
 676         i2s0: i2s@ff880000 {
 677                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 678                 reg = <0x0 0xff880000 0x0 0x1000>;
 679                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 680                 #address-cells = <1>;
 681                 #size-cells = <0>;
 682                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 683                 dma-names = "tx", "rx";
 684                 clock-names = "i2s_hclk", "i2s_clk";
 685                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 686                 pinctrl-names = "default";
 687                 pinctrl-0 = <&i2s0_8ch_bus>;
 688                 status = "disabled";
 689         };
 690
 691         i2s1: i2s@ff890000 {
 692                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 693                 reg = <0x0 0xff890000 0x0 0x1000>;
 694                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 695                 #address-cells = <1>;
 696                 #size-cells = <0>;
 697                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 698                 dma-names = "tx", "rx";
 699                 clock-names = "i2s_hclk", "i2s_clk";
 700                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 701                 pinctrl-names = "default";
 702                 pinctrl-0 = <&i2s1_2ch_bus>;
 703                 status = "disabled";
 704         };
 705
 706         i2s2: i2s@ff8a0000 {
 707                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 708                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 709                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 710                 #address-cells = <1>;
 711                 #size-cells = <0>;
 712                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 713                 dma-names = "tx", "rx";
 714                 clock-names = "i2s_hclk", "i2s_clk";
 715                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 716                 status = "disabled";
 717         };
 718
 719         pinctrl: pinctrl {
 720                 compatible = "rockchip,rk3399-pinctrl";
 721                 rockchip,grf = <&grf>;
 722                 rockchip,pmu = <&pmugrf>;
 723                 #address-cells = <0x2>;
 724                 #size-cells = <0x2>;
 725                 ranges;
 726
 727                 gpio0: gpio0@ff720000 {
 728                         compatible = "rockchip,gpio-bank";
 729                         reg = <0x0 0xff720000 0x0 0x100>;
 730                         clocks = <&xin24m>;
 731                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 732
 733                         gpio-controller;
 734                         #gpio-cells = <0x2>;
 735
 736                         interrupt-controller;
 737                         #interrupt-cells = <0x2>;
 738                 };
 739
 740                 gpio1: gpio1@ff730000 {
 741                         compatible = "rockchip,gpio-bank";
 742                         reg = <0x0 0xff730000 0x0 0x100>;
 743                         clocks = <&xin24m>;
 744                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 745
 746                         gpio-controller;
 747                         #gpio-cells = <0x2>;
 748
 749                         interrupt-controller;
 750                         #interrupt-cells = <0x2>;
 751                 };
 752
 753                 gpio2: gpio2@ff780000 {
 754                         compatible = "rockchip,gpio-bank";
 755                         reg = <0x0 0xff780000 0x0 0x100>;
 756                         clocks = <&xin24m>;
 757                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 758
 759                         gpio-controller;
 760                         #gpio-cells = <0x2>;
 761
 762                         interrupt-controller;
 763                         #interrupt-cells = <0x2>;
 764                 };
 765
 766                 gpio3: gpio3@ff788000 {
 767                         compatible = "rockchip,gpio-bank";
 768                         reg = <0x0 0xff788000 0x0 0x100>;
 769                         clocks = <&xin24m>;
 770                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 771
 772                         gpio-controller;
 773                         #gpio-cells = <0x2>;
 774
 775                         interrupt-controller;
 776                         #interrupt-cells = <0x2>;
 777                 };
 778
 779                 gpio4: gpio4@ff790000 {
 780                         compatible = "rockchip,gpio-bank";
 781                         reg = <0x0 0xff790000 0x0 0x100>;
 782                         clocks = <&xin24m>;
 783                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 784
 785                         gpio-controller;
 786                         #gpio-cells = <0x2>;
 787
 788                         interrupt-controller;
 789                         #interrupt-cells = <0x2>;
 790                 };
 791
 792                 pcfg_pull_up: pcfg-pull-up {
 793                         bias-pull-up;
 794                 };
 795
 796                 pcfg_pull_down: pcfg-pull-down {
 797                         bias-pull-down;
 798                 };
 799
 800                 pcfg_pull_none: pcfg-pull-none {
 801                         bias-disable;
 802                 };
 803
 804                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 805                         bias-disable;
 806                         drive-strength = <12>;
 807                 };
 808
 809                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 810                         bias-pull-up;
 811                         drive-strength = <8>;
 812                 };
 813
 814                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 815                         bias-pull-down;
 816                         drive-strength = <4>;
 817                 };
 818
 819                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 820                         bias-pull-up;
 821                         drive-strength = <2>;
 822                 };
 823
 824                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 825                         bias-pull-down;
 826                         drive-strength = <12>;
 827                 };
 828
 829                 emmc {
 830                         emmc_pwr: emmc-pwr {
 831                                 rockchip,pins =
 832                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 833                         };
 834                 };
 835
 836                 gmac {
 837                         rgmii_pins: rgmii-pins {
 838                                 rockchip,pins =
 839                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 840                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 841                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 842                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 843                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 844                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 845                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 846                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 847                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 848                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 849                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 850                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 851                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 852                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 853                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 854                         };
 855
 856                         rmii_pins: rmii-pins {
 857                                 rockchip,pins =
 858                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 859                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 860                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 861                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 862                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 863                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 864                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 865                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 866                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 867                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 868                         };
 869                 };
 870
 871                 i2c0 {
 872                         i2c0_xfer: i2c0-xfer {
 873                                 rockchip,pins =
 874                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 875                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 876                         };
 877                 };
 878
 879                 i2c1 {
 880                         i2c1_xfer: i2c1-xfer {
 881                                 rockchip,pins =
 882                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 883                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 884                         };
 885                 };
 886
 887                 i2c2 {
 888                         i2c2_xfer: i2c2-xfer {
 889                                 rockchip,pins =
 890                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 891                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 892                         };
 893                 };
 894
 895                 i2c3 {
 896                         i2c3_xfer: i2c3-xfer {
 897                                 rockchip,pins =
 898                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 899                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 900                         };
 901                 };
 902
 903                 i2c4 {
 904                         i2c4_xfer: i2c4-xfer {
 905                                 rockchip,pins =
 906                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 907                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 908                         };
 909                 };
 910
 911                 i2c5 {
 912                         i2c5_xfer: i2c5-xfer {
 913                                 rockchip,pins =
 914                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 915                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 916                         };
 917                 };
 918
 919                 i2c6 {
 920                         i2c6_xfer: i2c6-xfer {
 921                                 rockchip,pins =
 922                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 923                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 924                         };
 925                 };
 926
 927                 i2c7 {
 928                         i2c7_xfer: i2c7-xfer {
 929                                 rockchip,pins =
 930                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 931                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 932                         };
 933                 };
 934
 935                 i2c8 {
 936                         i2c8_xfer: i2c8-xfer {
 937                                 rockchip,pins =
 938                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 939                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 940                         };
 941                 };
 942
 943                 i2s0 {
 944                         i2s0_8ch_bus: i2s0-8ch-bus {
 945                                 rockchip,pins =
 946                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 947                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 948                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 949                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 950                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 951                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 952                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 953                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 954                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 955                         };
 956                 };
 957
 958                 i2s1 {
 959                         i2s1_2ch_bus: i2s1-2ch-bus {
 960                                 rockchip,pins =
 961                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 962                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 963                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 964                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 965                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 966                         };
 967                 };
 968
 969                 sdio0 {
 970                         sdio0_bus1: sdio0-bus1 {
 971                                 rockchip,pins =
 972                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
 973                         };
 974
 975                         sdio0_bus4: sdio0-bus4 {
 976                                 rockchip,pins =
 977                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
 978                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
 979                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
 980                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
 981                         };
 982
 983                         sdio0_cmd: sdio0-cmd {
 984                                 rockchip,pins =
 985                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
 986                         };
 987
 988                         sdio0_clk: sdio0-clk {
 989                                 rockchip,pins =
 990                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 991                         };
 992
 993                         sdio0_cd: sdio0-cd {
 994                                 rockchip,pins =
 995                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
 996                         };
 997
 998                         sdio0_pwr: sdio0-pwr {
 999                                 rockchip,pins =
1000                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1001                         };
1002
1003                         sdio0_bkpwr: sdio0-bkpwr {
1004                                 rockchip,pins =
1005                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1006                         };
1007
1008                         sdio0_wp: sdio0-wp {
1009                                 rockchip,pins =
1010                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1011                         };
1012
1013                         sdio0_int: sdio0-int {
1014                                 rockchip,pins =
1015                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1016                         };
1017                 };
1018
1019                 sdmmc {
1020                         sdmmc_bus1: sdmmc-bus1 {
1021                                 rockchip,pins =
1022                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1023                         };
1024
1025                         sdmmc_bus4: sdmmc-bus4 {
1026                                 rockchip,pins =
1027                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1028                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1029                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1030                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1031                         };
1032
1033                         sdmmc_clk: sdmmc-clk {
1034                                 rockchip,pins =
1035                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1036                         };
1037
1038                         sdmmc_cmd: sdmmc-cmd {
1039                                 rockchip,pins =
1040                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1041                         };
1042
1043                         sdmmc_cd: sdmcc-cd {
1044                                 rockchip,pins =
1045                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1046                         };
1047
1048                         sdmmc_wp: sdmmc-wp {
1049                                 rockchip,pins =
1050                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1051                         };
1052                 };
1053
1054                 spdif {
1055                         spdif_bus: spdif-bus {
1056                                 rockchip,pins =
1057                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1058                         };
1059                 };
1060
1061                 spi0 {
1062                         spi0_clk: spi0-clk {
1063                                 rockchip,pins =
1064                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1065                         };
1066                         spi0_cs0: spi0-cs0 {
1067                                 rockchip,pins =
1068                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1069                         };
1070                         spi0_cs1: spi0-cs1 {
1071                                 rockchip,pins =
1072                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1073                         };
1074                         spi0_tx: spi0-tx {
1075                                 rockchip,pins =
1076                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1077                         };
1078                         spi0_rx: spi0-rx {
1079                                 rockchip,pins =
1080                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1081                         };
1082                 };
1083
1084                 spi1 {
1085                         spi1_clk: spi1-clk {
1086                                 rockchip,pins =
1087                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1088                         };
1089                         spi1_cs0: spi1-cs0 {
1090                                 rockchip,pins =
1091                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1092                         };
1093                         spi1_rx: spi1-rx {
1094                                 rockchip,pins =
1095                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1096                         };
1097                         spi1_tx: spi1-tx {
1098                                 rockchip,pins =
1099                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1100                         };
1101                 };
1102
1103                 spi2 {
1104                         spi2_clk: spi2-clk {
1105                                 rockchip,pins =
1106                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1107                         };
1108                         spi2_cs0: spi2-cs0 {
1109                                 rockchip,pins =
1110                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1111                         };
1112                         spi2_rx: spi2-rx {
1113                                 rockchip,pins =
1114                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1115                         };
1116                         spi2_tx: spi2-tx {
1117                                 rockchip,pins =
1118                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1119                         };
1120                 };
1121
1122                 spi3 {
1123                         spi3_clk: spi3-clk {
1124                                 rockchip,pins =
1125                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1126                         };
1127                         spi3_cs0: spi3-cs0 {
1128                                 rockchip,pins =
1129                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1130                         };
1131                         spi3_rx: spi3-rx {
1132                                 rockchip,pins =
1133                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1134                         };
1135                         spi3_tx: spi3-tx {
1136                                 rockchip,pins =
1137                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1138                         };
1139                 };
1140
1141                 spi4 {
1142                         spi4_clk: spi4-clk {
1143                                 rockchip,pins =
1144                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1145                         };
1146                         spi4_cs0: spi4-cs0 {
1147                                 rockchip,pins =
1148                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1149                         };
1150                         spi4_rx: spi4-rx {
1151                                 rockchip,pins =
1152                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1153                         };
1154                         spi4_tx: spi4-tx {
1155                                 rockchip,pins =
1156                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1157                         };
1158                 };
1159
1160                 spi5 {
1161                         spi5_clk: spi5-clk {
1162                                 rockchip,pins =
1163                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1164                         };
1165                         spi5_cs0: spi5-cs0 {
1166                                 rockchip,pins =
1167                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1168                         };
1169                         spi5_rx: spi5-rx {
1170                                 rockchip,pins =
1171                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1172                         };
1173                         spi5_tx: spi5-tx {
1174                                 rockchip,pins =
1175                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1176                         };
1177                 };
1178
1179                 tsadc {
1180                         otp_gpio: otp-gpio {
1181                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1182                         };
1183
1184                         otp_out: otp-out {
1185                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1186                         };
1187                 };
1188
1189                 uart0 {
1190                         uart0_xfer: uart0-xfer {
1191                                 rockchip,pins =
1192                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1193                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1194                         };
1195
1196                         uart0_cts: uart0-cts {
1197                                 rockchip,pins =
1198                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1199                         };
1200
1201                         uart0_rts: uart0-rts {
1202                                 rockchip,pins =
1203                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1204                         };
1205                 };
1206
1207                 uart1 {
1208                         uart1_xfer: uart1-xfer {
1209                                 rockchip,pins =
1210                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1211                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1212                         };
1213                 };
1214
1215                 uart2a {
1216                         uart2a_xfer: uart2a-xfer {
1217                                 rockchip,pins =
1218                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1219                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1220                         };
1221                 };
1222
1223                 uart2b {
1224                         uart2b_xfer: uart2b-xfer {
1225                                 rockchip,pins =
1226                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1227                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1228                         };
1229                 };
1230
1231                 uart2c {
1232                         uart2c_xfer: uart2c-xfer {
1233                                 rockchip,pins =
1234                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1235                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1236                         };
1237                 };
1238
1239                 uart3 {
1240                         uart3_xfer: uart3-xfer {
1241                                 rockchip,pins =
1242                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1243                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1244                         };
1245
1246                         uart3_cts: uart3-cts {
1247                                 rockchip,pins =
1248                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1249                         };
1250
1251                         uart3_rts: uart3-rts {
1252                                 rockchip,pins =
1253                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1254                         };
1255                 };
1256
1257                 uart4 {
1258                         uart4_xfer: uart4-xfer {
1259                                 rockchip,pins =
1260                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1261                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1262                         };
1263                 };
1264
1265                 uarthdcp {
1266                         uarthdcp_xfer: uarthdcp-xfer {
1267                                 rockchip,pins =
1268                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1269                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1270                         };
1271                 };
1272
1273                 pwm0 {
1274                         pwm0_pin: pwm0-pin {
1275                                 rockchip,pins =
1276                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1277                         };
1278
1279                         vop0_pwm_pin: vop0-pwm-pin {
1280                                 rockchip,pins =
1281                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1282                         };
1283                 };
1284
1285                 pwm1 {
1286                         pwm1_pin: pwm1-pin {
1287                                 rockchip,pins =
1288                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1289                         };
1290
1291                         vop1_pwm_pin: vop1-pwm-pin {
1292                                 rockchip,pins =
1293                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1294                         };
1295                 };
1296
1297                 pwm2 {
1298                         pwm2_pin: pwm2-pin {
1299                                 rockchip,pins =
1300                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1301                         };
1302                 };
1303
1304                 pwm3a {
1305                         pwm3a_pin: pwm3a-pin {
1306                                 rockchip,pins =
1307                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1308                         };
1309                 };
1310
1311                 pwm3b {
1312                         pwm3b_pin: pwm3b-pin {
1313                                 rockchip,pins =
1314                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1315                         };
1316                 };
1317         };
1318 };