2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/suspend/rockchip-rk3399.h>
51 #include <dt-bindings/thermal/thermal.h>
53 #include "rk3399-dram-default-timing.dtsi"
56 compatible = "rockchip,rk3399";
58 interrupt-parent = <&gic>;
80 compatible = "arm,psci-1.0";
116 compatible = "arm,cortex-a53", "arm,armv8";
118 enable-method = "psci";
119 #cooling-cells = <2>; /* min followed by max */
120 dynamic-power-coefficient = <100>;
121 clocks = <&cru ARMCLKL>;
122 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
127 compatible = "arm,cortex-a53", "arm,armv8";
129 enable-method = "psci";
130 clocks = <&cru ARMCLKL>;
131 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
136 compatible = "arm,cortex-a53", "arm,armv8";
138 enable-method = "psci";
139 clocks = <&cru ARMCLKL>;
140 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
145 compatible = "arm,cortex-a53", "arm,armv8";
147 enable-method = "psci";
148 clocks = <&cru ARMCLKL>;
149 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
154 compatible = "arm,cortex-a72", "arm,armv8";
156 enable-method = "psci";
157 #cooling-cells = <2>; /* min followed by max */
158 dynamic-power-coefficient = <436>;
159 clocks = <&cru ARMCLKB>;
160 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
165 compatible = "arm,cortex-a72", "arm,armv8";
167 enable-method = "psci";
168 clocks = <&cru ARMCLKB>;
169 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
173 entry-method = "psci";
175 CPU_SLEEP: cpu-sleep {
176 compatible = "arm,idle-state";
178 arm,psci-suspend-param = <0x0010000>;
179 entry-latency-us = <120>;
180 exit-latency-us = <250>;
181 min-residency-us = <900>;
184 CLUSTER_SLEEP: cluster-sleep {
185 compatible = "arm,idle-state";
187 arm,psci-suspend-param = <0x1010000>;
188 entry-latency-us = <400>;
189 exit-latency-us = <500>;
190 min-residency-us = <2000>;
198 min-volt = <800000>; /* uV */
199 min-freq = <408000>; /* KHz */
200 leakage-adjust-volt = <
204 nvmem-cells = <&cpul_leakage>;
205 nvmem-cell-names = "cpu_leakage";
209 min-volt = <800000>; /* uV */
210 min-freq = <408000>; /* KHz */
211 leakage-adjust-volt = <
215 nvmem-cells = <&cpub_leakage>;
216 nvmem-cell-names = "cpu_leakage";
221 compatible = "arm,armv8-timer";
222 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
223 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
224 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
225 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
229 compatible = "arm,cortex-a53-pmu";
230 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
234 compatible = "arm,cortex-a72-pmu";
235 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
239 compatible = "fixed-clock";
241 clock-frequency = <24000000>;
242 clock-output-names = "xin24m";
246 compatible = "arm,amba-bus";
247 #address-cells = <2>;
251 dmac_bus: dma-controller@ff6d0000 {
252 compatible = "arm,pl330", "arm,primecell";
253 reg = <0x0 0xff6d0000 0x0 0x4000>;
254 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
255 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
257 clocks = <&cru ACLK_DMAC0_PERILP>;
258 clock-names = "apb_pclk";
259 peripherals-req-type-burst;
262 dmac_peri: dma-controller@ff6e0000 {
263 compatible = "arm,pl330", "arm,primecell";
264 reg = <0x0 0xff6e0000 0x0 0x4000>;
265 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
266 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
268 clocks = <&cru ACLK_DMAC1_PERILP>;
269 clock-names = "apb_pclk";
270 peripherals-req-type-burst;
275 compatible = "rockchip,rk3399-gmac";
276 reg = <0x0 0xfe300000 0x0 0x10000>;
277 rockchip,grf = <&grf>;
278 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
279 interrupt-names = "macirq";
280 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
281 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
282 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
284 clock-names = "stmmaceth", "mac_clk_rx",
285 "mac_clk_tx", "clk_mac_ref",
286 "clk_mac_refout", "aclk_mac",
288 resets = <&cru SRST_A_GMAC>;
289 reset-names = "stmmaceth";
290 power-domains = <&power RK3399_PD_GMAC>;
294 sdio0: dwmmc@fe310000 {
295 compatible = "rockchip,rk3399-dw-mshc",
296 "rockchip,rk3288-dw-mshc";
297 reg = <0x0 0xfe310000 0x0 0x4000>;
298 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
299 clock-freq-min-max = <400000 150000000>;
300 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
301 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
302 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
303 fifo-depth = <0x100>;
304 power-domains = <&power RK3399_PD_SDIOAUDIO>;
308 sdmmc: dwmmc@fe320000 {
309 compatible = "rockchip,rk3399-dw-mshc",
310 "rockchip,rk3288-dw-mshc";
311 reg = <0x0 0xfe320000 0x0 0x4000>;
312 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
313 clock-freq-min-max = <400000 150000000>;
314 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
315 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
316 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
317 fifo-depth = <0x100>;
318 power-domains = <&power RK3399_PD_SD>;
322 sdhci: sdhci@fe330000 {
323 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
324 reg = <0x0 0xfe330000 0x0 0x10000>;
325 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
326 arasan,soc-ctl-syscon = <&grf>;
327 assigned-clocks = <&cru SCLK_EMMC>;
328 assigned-clock-rates = <200000000>;
329 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
330 clock-names = "clk_xin", "clk_ahb";
331 clock-output-names = "emmc_cardclock";
334 phy-names = "phy_arasan";
335 power-domains = <&power RK3399_PD_EMMC>;
339 usb_host0_ehci: usb@fe380000 {
340 compatible = "generic-ehci";
341 reg = <0x0 0xfe380000 0x0 0x20000>;
342 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
343 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
344 <&cru SCLK_USBPHY0_480M_SRC>;
345 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
346 phys = <&u2phy0_host>;
348 power-domains = <&power RK3399_PD_PERIHP>;
352 usb_host0_ohci: usb@fe3a0000 {
353 compatible = "generic-ohci";
354 reg = <0x0 0xfe3a0000 0x0 0x20000>;
355 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
357 <&cru SCLK_USBPHY0_480M_SRC>;
358 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
359 phys = <&u2phy0_host>;
361 power-domains = <&power RK3399_PD_PERIHP>;
365 usb_host1_ehci: usb@fe3c0000 {
366 compatible = "generic-ehci";
367 reg = <0x0 0xfe3c0000 0x0 0x20000>;
368 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
369 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
370 <&cru SCLK_USBPHY1_480M_SRC>;
371 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
372 phys = <&u2phy1_host>;
374 power-domains = <&power RK3399_PD_PERIHP>;
378 usb_host1_ohci: usb@fe3e0000 {
379 compatible = "generic-ohci";
380 reg = <0x0 0xfe3e0000 0x0 0x20000>;
381 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
382 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
383 <&cru SCLK_USBPHY1_480M_SRC>;
384 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
385 phys = <&u2phy1_host>;
387 power-domains = <&power RK3399_PD_PERIHP>;
391 usbdrd3_0: usb@fe800000 {
392 compatible = "rockchip,rk3399-dwc3";
393 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
394 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
395 clock-names = "ref_clk", "suspend_clk",
396 "bus_clk", "grf_clk";
397 power-domains = <&power RK3399_PD_USB3>;
398 resets = <&cru SRST_A_USB3_OTG0>;
399 reset-names = "usb3-otg";
400 #address-cells = <2>;
404 usbdrd_dwc3_0: dwc3@fe800000 {
405 compatible = "snps,dwc3";
406 reg = <0x0 0xfe800000 0x0 0x100000>;
407 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
409 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
410 phy-names = "usb2-phy", "usb3-phy";
411 phy_type = "utmi_wide";
412 snps,dis_enblslpm_quirk;
413 snps,dis-u2-freeclk-exists-quirk;
414 snps,dis_u2_susphy_quirk;
415 snps,dis-del-phy-power-chg-quirk;
416 snps,xhci-slow-suspend-quirk;
421 usbdrd3_1: usb@fe900000 {
422 compatible = "rockchip,rk3399-dwc3";
423 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
424 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
425 clock-names = "ref_clk", "suspend_clk",
426 "bus_clk", "grf_clk";
427 power-domains = <&power RK3399_PD_USB3>;
428 resets = <&cru SRST_A_USB3_OTG1>;
429 reset-names = "usb3-otg";
430 #address-cells = <2>;
434 usbdrd_dwc3_1: dwc3@fe900000 {
435 compatible = "snps,dwc3";
436 reg = <0x0 0xfe900000 0x0 0x100000>;
437 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
439 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
440 phy-names = "usb2-phy", "usb3-phy";
441 phy_type = "utmi_wide";
442 snps,dis_enblslpm_quirk;
443 snps,dis-u2-freeclk-exists-quirk;
444 snps,dis_u2_susphy_quirk;
445 snps,dis-del-phy-power-chg-quirk;
446 snps,xhci-slow-suspend-quirk;
451 cdn_dp: dp@fec00000 {
452 compatible = "rockchip,rk3399-cdn-dp";
453 reg = <0x0 0xfec00000 0x0 0x100000>;
454 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
456 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
457 clock-names = "core-clk", "pclk", "spdif", "grf";
458 assigned-clocks = <&cru SCLK_DP_CORE>;
459 assigned-clock-rates = <100000000>;
460 power-domains = <&power RK3399_PD_HDCP>;
461 phys = <&tcphy0_dp>, <&tcphy1_dp>;
462 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
463 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
464 reset-names = "spdif", "dptx", "apb", "core";
465 rockchip,grf = <&grf>;
466 #address-cells = <1>;
468 #sound-dai-cells = <1>;
472 #address-cells = <1>;
476 #address-cells = <1>;
478 dp_in_vopb: endpoint@0 {
480 remote-endpoint = <&vopb_out_dp>;
483 dp_in_vopl: endpoint@1 {
485 remote-endpoint = <&vopl_out_dp>;
491 gic: interrupt-controller@fee00000 {
492 compatible = "arm,gic-v3";
493 #interrupt-cells = <4>;
494 #address-cells = <2>;
497 interrupt-controller;
499 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
500 <0x0 0xfef00000 0 0xc0000>, /* GICR */
501 <0x0 0xfff00000 0 0x10000>, /* GICC */
502 <0x0 0xfff10000 0 0x10000>, /* GICH */
503 <0x0 0xfff20000 0 0x10000>; /* GICV */
504 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
505 its: interrupt-controller@fee20000 {
506 compatible = "arm,gic-v3-its";
508 reg = <0x0 0xfee20000 0x0 0x20000>;
512 part0: interrupt-partition-0 {
513 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
516 part1: interrupt-partition-1 {
517 affinity = <&cpu_b0 &cpu_b1>;
522 saradc: saradc@ff100000 {
523 compatible = "rockchip,rk3399-saradc";
524 reg = <0x0 0xff100000 0x0 0x100>;
525 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
526 #io-channel-cells = <1>;
527 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
528 clock-names = "saradc", "apb_pclk";
529 resets = <&cru SRST_P_SARADC>;
530 reset-names = "saradc-apb";
535 compatible = "rockchip,rk3399-i2c";
536 reg = <0x0 0xff3c0000 0x0 0x1000>;
537 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
538 clock-names = "i2c", "pclk";
539 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c0_xfer>;
542 #address-cells = <1>;
548 compatible = "rockchip,rk3399-i2c";
549 reg = <0x0 0xff110000 0x0 0x1000>;
550 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
551 clock-names = "i2c", "pclk";
552 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c1_xfer>;
555 #address-cells = <1>;
561 compatible = "rockchip,rk3399-i2c";
562 reg = <0x0 0xff120000 0x0 0x1000>;
563 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
564 clock-names = "i2c", "pclk";
565 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c2_xfer>;
568 #address-cells = <1>;
574 compatible = "rockchip,rk3399-i2c";
575 reg = <0x0 0xff130000 0x0 0x1000>;
576 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
577 clock-names = "i2c", "pclk";
578 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c3_xfer>;
581 #address-cells = <1>;
587 compatible = "rockchip,rk3399-i2c";
588 reg = <0x0 0xff140000 0x0 0x1000>;
589 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
590 clock-names = "i2c", "pclk";
591 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c5_xfer>;
594 #address-cells = <1>;
600 compatible = "rockchip,rk3399-i2c";
601 reg = <0x0 0xff150000 0x0 0x1000>;
602 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
603 clock-names = "i2c", "pclk";
604 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&i2c6_xfer>;
607 #address-cells = <1>;
613 compatible = "rockchip,rk3399-i2c";
614 reg = <0x0 0xff160000 0x0 0x1000>;
615 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
616 clock-names = "i2c", "pclk";
617 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&i2c7_xfer>;
620 #address-cells = <1>;
625 uart0: serial@ff180000 {
626 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
627 reg = <0x0 0xff180000 0x0 0x100>;
628 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
629 clock-names = "baudclk", "apb_pclk";
630 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
633 pinctrl-names = "default";
634 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
638 uart1: serial@ff190000 {
639 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
640 reg = <0x0 0xff190000 0x0 0x100>;
641 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
642 clock-names = "baudclk", "apb_pclk";
643 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&uart1_xfer>;
651 uart2: serial@ff1a0000 {
652 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
653 reg = <0x0 0xff1a0000 0x0 0x100>;
654 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
655 clock-names = "baudclk", "apb_pclk";
656 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&uart2c_xfer>;
664 uart3: serial@ff1b0000 {
665 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
666 reg = <0x0 0xff1b0000 0x0 0x100>;
667 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
668 clock-names = "baudclk", "apb_pclk";
669 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
678 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
679 reg = <0x0 0xff1c0000 0x0 0x1000>;
680 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
681 clock-names = "spiclk", "apb_pclk";
682 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
685 #address-cells = <1>;
691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
692 reg = <0x0 0xff1d0000 0x0 0x1000>;
693 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
694 clock-names = "spiclk", "apb_pclk";
695 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
696 pinctrl-names = "default";
697 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
698 #address-cells = <1>;
704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
705 reg = <0x0 0xff1e0000 0x0 0x1000>;
706 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
707 clock-names = "spiclk", "apb_pclk";
708 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
711 #address-cells = <1>;
717 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
718 reg = <0x0 0xff1f0000 0x0 0x1000>;
719 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
720 clock-names = "spiclk", "apb_pclk";
721 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
724 #address-cells = <1>;
730 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
731 reg = <0x0 0xff200000 0x0 0x1000>;
732 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
733 clock-names = "spiclk", "apb_pclk";
734 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
737 #address-cells = <1>;
743 soc_thermal: soc-thermal {
744 polling-delay-passive = <20>; /* milliseconds */
745 polling-delay = <1000>; /* milliseconds */
746 sustainable-power = <1000>; /* milliwatts */
748 thermal-sensors = <&tsadc 0>;
751 threshold: trip-point@0 {
752 temperature = <70000>; /* millicelsius */
753 hysteresis = <2000>; /* millicelsius */
756 target: trip-point@1 {
757 temperature = <85000>; /* millicelsius */
758 hysteresis = <2000>; /* millicelsius */
762 temperature = <95000>; /* millicelsius */
763 hysteresis = <2000>; /* millicelsius */
772 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
773 contribution = <4096>;
778 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
779 contribution = <1024>;
784 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
785 contribution = <4096>;
790 gpu_thermal: gpu-thermal {
791 polling-delay-passive = <100>; /* milliseconds */
792 polling-delay = <1000>; /* milliseconds */
794 thermal-sensors = <&tsadc 1>;
798 tsadc: tsadc@ff260000 {
799 compatible = "rockchip,rk3399-tsadc";
800 reg = <0x0 0xff260000 0x0 0x100>;
801 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
802 rockchip,grf = <&grf>;
803 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
804 clock-names = "tsadc", "apb_pclk";
805 assigned-clocks = <&cru SCLK_TSADC>;
806 assigned-clock-rates = <750000>;
807 resets = <&cru SRST_TSADC>;
808 reset-names = "tsadc-apb";
809 pinctrl-names = "init", "default", "sleep";
810 pinctrl-0 = <&otp_gpio>;
811 pinctrl-1 = <&otp_out>;
812 pinctrl-2 = <&otp_gpio>;
813 #thermal-sensor-cells = <1>;
814 rockchip,hw-tshut-temp = <95000>;
818 qos_emmc: qos@ffa58000 {
819 compatible = "syscon";
820 reg = <0x0 0xffa58000 0x0 0x20>;
823 qos_gmac: qos@ffa5c000 {
824 compatible = "syscon";
825 reg = <0x0 0xffa5c000 0x0 0x20>;
828 qos_pcie: qos@ffa60080 {
829 compatible = "syscon";
830 reg = <0x0 0xffa60080 0x0 0x20>;
833 qos_usb_host0: qos@ffa60100 {
834 compatible = "syscon";
835 reg = <0x0 0xffa60100 0x0 0x20>;
838 qos_usb_host1: qos@ffa60180 {
839 compatible = "syscon";
840 reg = <0x0 0xffa60180 0x0 0x20>;
843 qos_usb_otg0: qos@ffa70000 {
844 compatible = "syscon";
845 reg = <0x0 0xffa70000 0x0 0x20>;
848 qos_usb_otg1: qos@ffa70080 {
849 compatible = "syscon";
850 reg = <0x0 0xffa70080 0x0 0x20>;
853 qos_sd: qos@ffa74000 {
854 compatible = "syscon";
855 reg = <0x0 0xffa74000 0x0 0x20>;
858 qos_sdioaudio: qos@ffa76000 {
859 compatible = "syscon";
860 reg = <0x0 0xffa76000 0x0 0x20>;
863 qos_hdcp: qos@ffa90000 {
864 compatible = "syscon";
865 reg = <0x0 0xffa90000 0x0 0x20>;
868 qos_iep: qos@ffa98000 {
869 compatible = "syscon";
870 reg = <0x0 0xffa98000 0x0 0x20>;
873 qos_isp0_m0: qos@ffaa0000 {
874 compatible = "syscon";
875 reg = <0x0 0xffaa0000 0x0 0x20>;
878 qos_isp0_m1: qos@ffaa0080 {
879 compatible = "syscon";
880 reg = <0x0 0xffaa0080 0x0 0x20>;
883 qos_isp1_m0: qos@ffaa8000 {
884 compatible = "syscon";
885 reg = <0x0 0xffaa8000 0x0 0x20>;
888 qos_isp1_m1: qos@ffaa8080 {
889 compatible = "syscon";
890 reg = <0x0 0xffaa8080 0x0 0x20>;
893 qos_rga_r: qos@ffab0000 {
894 compatible = "syscon";
895 reg = <0x0 0xffab0000 0x0 0x20>;
898 qos_rga_w: qos@ffab0080 {
899 compatible = "syscon";
900 reg = <0x0 0xffab0080 0x0 0x20>;
903 qos_video_m0: qos@ffab8000 {
904 compatible = "syscon";
905 reg = <0x0 0xffab8000 0x0 0x20>;
908 qos_video_m1_r: qos@ffac0000 {
909 compatible = "syscon";
910 reg = <0x0 0xffac0000 0x0 0x20>;
913 qos_video_m1_w: qos@ffac0080 {
914 compatible = "syscon";
915 reg = <0x0 0xffac0080 0x0 0x20>;
918 qos_vop_big_r: qos@ffac8000 {
919 compatible = "syscon";
920 reg = <0x0 0xffac8000 0x0 0x20>;
923 qos_vop_big_w: qos@ffac8080 {
924 compatible = "syscon";
925 reg = <0x0 0xffac8080 0x0 0x20>;
928 qos_vop_little: qos@ffad0000 {
929 compatible = "syscon";
930 reg = <0x0 0xffad0000 0x0 0x20>;
933 qos_perihp: qos@ffad8080 {
934 compatible = "syscon";
935 reg = <0x0 0xffad8080 0x0 0x20>;
938 qos_gpu: qos@ffae0000 {
939 compatible = "syscon";
940 reg = <0x0 0xffae0000 0x0 0x20>;
943 pmu: power-management@ff310000 {
944 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
945 reg = <0x0 0xff310000 0x0 0x1000>;
948 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
949 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
950 * Some of the power domains are grouped together for every
952 * The detail contents as below.
954 power: power-controller {
955 compatible = "rockchip,rk3399-power-controller";
956 #power-domain-cells = <1>;
957 #address-cells = <1>;
960 /* These power domains are grouped by VD_CENTER */
961 pd_iep@RK3399_PD_IEP {
962 reg = <RK3399_PD_IEP>;
963 clocks = <&cru ACLK_IEP>,
967 pd_rga@RK3399_PD_RGA {
968 reg = <RK3399_PD_RGA>;
969 clocks = <&cru ACLK_RGA>,
971 pm_qos = <&qos_rga_r>,
974 pd_vcodec@RK3399_PD_VCODEC {
975 reg = <RK3399_PD_VCODEC>;
976 clocks = <&cru ACLK_VCODEC>,
978 pm_qos = <&qos_video_m0>;
980 pd_vdu@RK3399_PD_VDU {
981 reg = <RK3399_PD_VDU>;
982 clocks = <&cru ACLK_VDU>,
984 pm_qos = <&qos_video_m1_r>,
988 /* These power domains are grouped by VD_GPU */
989 pd_gpu@RK3399_PD_GPU {
990 reg = <RK3399_PD_GPU>;
991 clocks = <&cru ACLK_GPU>;
995 /* These power domains are grouped by VD_LOGIC */
996 pd_edp@RK3399_PD_EDP {
997 reg = <RK3399_PD_EDP>;
998 clocks = <&cru PCLK_EDP_CTRL>;
1000 pd_emmc@RK3399_PD_EMMC {
1001 reg = <RK3399_PD_EMMC>;
1002 clocks = <&cru ACLK_EMMC>;
1003 pm_qos = <&qos_emmc>;
1005 pd_gmac@RK3399_PD_GMAC {
1006 reg = <RK3399_PD_GMAC>;
1007 clocks = <&cru ACLK_GMAC>,
1009 pm_qos = <&qos_gmac>;
1011 pd_perihp@RK3399_PD_PERIHP {
1012 reg = <RK3399_PD_PERIHP>;
1013 #address-cells = <1>;
1015 clocks = <&cru ACLK_PERIHP>;
1016 pm_qos = <&qos_perihp>,
1021 pd_sd@RK3399_PD_SD {
1022 reg = <RK3399_PD_SD>;
1023 clocks = <&cru HCLK_SDMMC>,
1028 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1029 reg = <RK3399_PD_SDIOAUDIO>;
1030 clocks = <&cru HCLK_SDIO>;
1031 pm_qos = <&qos_sdioaudio>;
1033 pd_usb3@RK3399_PD_USB3 {
1034 reg = <RK3399_PD_USB3>;
1035 clocks = <&cru ACLK_USB3>;
1036 pm_qos = <&qos_usb_otg0>,
1039 pd_vio@RK3399_PD_VIO {
1040 reg = <RK3399_PD_VIO>;
1041 #address-cells = <1>;
1044 pd_hdcp@RK3399_PD_HDCP {
1045 reg = <RK3399_PD_HDCP>;
1046 clocks = <&cru ACLK_HDCP>,
1049 pm_qos = <&qos_hdcp>;
1051 pd_isp0@RK3399_PD_ISP0 {
1052 reg = <RK3399_PD_ISP0>;
1053 clocks = <&cru ACLK_ISP0>,
1055 pm_qos = <&qos_isp0_m0>,
1058 pd_isp1@RK3399_PD_ISP1 {
1059 reg = <RK3399_PD_ISP1>;
1060 clocks = <&cru ACLK_ISP1>,
1062 pm_qos = <&qos_isp1_m0>,
1065 pd_tcpc0@RK3399_PD_TCPC0 {
1066 reg = <RK3399_PD_TCPD0>;
1067 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1068 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1070 pd_tcpc1@RK3399_PD_TCPC1 {
1071 reg = <RK3399_PD_TCPD1>;
1072 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1073 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1075 pd_vo@RK3399_PD_VO {
1076 reg = <RK3399_PD_VO>;
1077 #address-cells = <1>;
1080 pd_vopb@RK3399_PD_VOPB {
1081 reg = <RK3399_PD_VOPB>;
1082 clocks = <&cru ACLK_VOP0>,
1084 pm_qos = <&qos_vop_big_r>,
1087 pd_vopl@RK3399_PD_VOPL {
1088 reg = <RK3399_PD_VOPL>;
1089 clocks = <&cru ACLK_VOP1>,
1091 pm_qos = <&qos_vop_little>;
1098 pmugrf: syscon@ff320000 {
1099 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1100 reg = <0x0 0xff320000 0x0 0x1000>;
1102 pmu_io_domains: pmu-io-domains {
1103 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1104 status = "disabled";
1108 compatible = "syscon-reboot-mode";
1110 mode-bootloader = <BOOT_BL_DOWNLOAD>;
1111 mode-charge = <BOOT_CHARGING>;
1112 mode-fastboot = <BOOT_FASTBOOT>;
1113 mode-loader = <BOOT_BL_DOWNLOAD>;
1114 mode-normal = <BOOT_NORMAL>;
1115 mode-recovery = <BOOT_RECOVERY>;
1116 mode-ums = <BOOT_UMS>;
1119 pmu_pvtm: pmu-pvtm {
1120 compatible = "rockchip,rk3399-pmu-pvtm";
1121 clocks = <&pmucru SCLK_PVTM_PMU>;
1122 clock-names = "pmu";
1123 status = "disabled";
1127 spi3: spi@ff350000 {
1128 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1129 reg = <0x0 0xff350000 0x0 0x1000>;
1130 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1131 clock-names = "spiclk", "apb_pclk";
1132 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1135 #address-cells = <1>;
1137 status = "disabled";
1140 uart4: serial@ff370000 {
1141 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1142 reg = <0x0 0xff370000 0x0 0x100>;
1143 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1144 clock-names = "baudclk", "apb_pclk";
1145 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&uart4_xfer>;
1150 status = "disabled";
1153 i2c4: i2c@ff3d0000 {
1154 compatible = "rockchip,rk3399-i2c";
1155 reg = <0x0 0xff3d0000 0x0 0x1000>;
1156 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1157 clock-names = "i2c", "pclk";
1158 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1159 pinctrl-names = "default";
1160 pinctrl-0 = <&i2c4_xfer>;
1161 #address-cells = <1>;
1163 status = "disabled";
1166 i2c8: i2c@ff3e0000 {
1167 compatible = "rockchip,rk3399-i2c";
1168 reg = <0x0 0xff3e0000 0x0 0x1000>;
1169 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1170 clock-names = "i2c", "pclk";
1171 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1172 pinctrl-names = "default";
1173 pinctrl-0 = <&i2c8_xfer>;
1174 #address-cells = <1>;
1176 status = "disabled";
1179 pcie_phy: phy@e220 {
1180 compatible = "rockchip,rk3399-pcie-phy";
1182 rockchip,grf = <&grf>;
1183 clocks = <&cru SCLK_PCIEPHY_REF>;
1184 clock-names = "refclk";
1185 resets = <&cru SRST_PCIEPHY>;
1186 reset-names = "phy";
1187 status = "disabled";
1190 pcie0: pcie@f8000000 {
1191 compatible = "rockchip,rk3399-pcie";
1192 #address-cells = <3>;
1195 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1196 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1197 clock-names = "aclk", "aclk-perf",
1199 bus-range = <0x0 0x1>;
1200 max-link-speed = <1>;
1201 msi-map = <0x0 &its 0x0 0x1000>;
1202 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1203 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1204 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1205 interrupt-names = "sys", "legacy", "client";
1206 #interrupt-cells = <1>;
1207 interrupt-map-mask = <0 0 0 7>;
1208 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1209 <0 0 0 2 &pcie0_intc 1>,
1210 <0 0 0 3 &pcie0_intc 2>,
1211 <0 0 0 4 &pcie0_intc 3>;
1213 phy-names = "pcie-phy";
1214 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1215 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1216 reg = <0x0 0xf8000000 0x0 0x2000000>,
1217 <0x0 0xfd000000 0x0 0x1000000>;
1218 reg-names = "axi-base", "apb-base";
1219 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1220 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1221 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1223 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1224 "pm", "pclk", "aclk";
1225 status = "disabled";
1226 pcie0_intc: interrupt-controller {
1227 interrupt-controller;
1228 #address-cells = <0>;
1229 #interrupt-cells = <1>;
1233 pwm0: pwm@ff420000 {
1234 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1235 reg = <0x0 0xff420000 0x0 0x10>;
1237 pinctrl-names = "default";
1238 pinctrl-0 = <&pwm0_pin>;
1239 clocks = <&pmucru PCLK_RKPWM_PMU>;
1240 clock-names = "pwm";
1241 status = "disabled";
1244 pwm1: pwm@ff420010 {
1245 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1246 reg = <0x0 0xff420010 0x0 0x10>;
1248 pinctrl-names = "default";
1249 pinctrl-0 = <&pwm1_pin>;
1250 clocks = <&pmucru PCLK_RKPWM_PMU>;
1251 clock-names = "pwm";
1252 status = "disabled";
1255 pwm2: pwm@ff420020 {
1256 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1257 reg = <0x0 0xff420020 0x0 0x10>;
1259 pinctrl-names = "default";
1260 pinctrl-0 = <&pwm2_pin>;
1261 clocks = <&pmucru PCLK_RKPWM_PMU>;
1262 clock-names = "pwm";
1263 status = "disabled";
1266 pwm3: pwm@ff420030 {
1267 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1268 reg = <0x0 0xff420030 0x0 0x10>;
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&pwm3a_pin>;
1272 clocks = <&pmucru PCLK_RKPWM_PMU>;
1273 clock-names = "pwm";
1274 status = "disabled";
1278 reg = <0x00 0xff630000 0x00 0x4000>;
1279 compatible = "rockchip,rk3399-dfi";
1280 rockchip,pmu = <&pmugrf>;
1281 clocks = <&cru PCLK_DDR_MON>;
1282 clock-names = "pclk_ddr_mon";
1283 status = "disabled";
1287 compatible = "rockchip,rk3399-dmc";
1288 devfreq-events = <&dfi>;
1289 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1290 clocks = <&cru SCLK_DDRCLK>;
1291 clock-names = "dmc_clk";
1292 ddr_timing = <&ddr_timing>;
1293 status = "disabled";
1296 vpu: vpu_service@ff650000 {
1297 compatible = "rockchip,vpu_service";
1298 rockchip,grf = <&grf>;
1299 iommus = <&vpu_mmu>;
1300 iommu_enabled = <1>;
1301 reg = <0x0 0xff650000 0x0 0x800>;
1302 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1303 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1304 interrupt-names = "irq_dec", "irq_enc";
1305 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1306 clock-names = "aclk_vcodec", "hclk_vcodec";
1307 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1308 reset-names = "video_h", "video_a";
1309 power-domains = <&power RK3399_PD_VCODEC>;
1310 name = "vpu_service";
1312 /* 0 means ion, 1 means drm */
1314 status = "disabled";
1317 vpu_mmu: iommu@ff650800 {
1318 compatible = "rockchip,iommu";
1319 reg = <0x0 0xff650800 0x0 0x40>;
1320 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1321 interrupt-names = "vpu_mmu";
1325 rkvdec: rkvdec@ff660000 {
1326 compatible = "rockchip,rkvdec";
1327 rockchip,grf = <&grf>;
1328 iommus = <&vdec_mmu>;
1329 iommu_enabled = <1>;
1330 reg = <0x0 0xff660000 0x0 0x400>;
1331 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1332 interrupt-names = "irq_dec";
1333 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1334 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1335 clock-names = "aclk_vcodec", "hclk_vcodec",
1336 "clk_cabac", "clk_core";
1337 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
1338 reset-names = "video_h", "video_a";
1339 power-domains = <&power RK3399_PD_VDU>;
1342 /* 0 means ion, 1 means drm */
1344 status = "disabled";
1347 vdec_mmu: iommu@ff660480 {
1348 compatible = "rockchip,iommu";
1349 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1350 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1351 interrupt-names = "vdec_mmu";
1356 compatible = "rockchip,rk3399-rga";
1357 reg = <0x0 0xff680000 0x0 0x10000>;
1358 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1359 interrupt-names = "rga";
1360 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1361 clock-names = "aclk", "hclk", "sclk";
1362 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1363 reset-names = "core", "axi", "ahb";
1364 power-domains = <&power RK3399_PD_RGA>;
1365 status = "disabled";
1368 efuse0: efuse@ff690000 {
1369 compatible = "rockchip,rk3399-efuse";
1370 reg = <0x0 0xff690000 0x0 0x80>;
1371 #address-cells = <1>;
1373 clocks = <&cru PCLK_EFUSE1024NS>;
1374 clock-names = "pclk_efuse";
1377 cpul_leakage: cpul-leakage {
1380 cpub_leakage: cpub-leakage {
1383 gpu_leakage: gpu-leakage {
1386 center_leakage: center-leakage {
1389 logic_leakage: logic-leakage {
1392 wafer_info: wafer-info {
1397 pmucru: pmu-clock-controller@ff750000 {
1398 compatible = "rockchip,rk3399-pmucru";
1399 reg = <0x0 0xff750000 0x0 0x1000>;
1402 assigned-clocks = <&pmucru PLL_PPLL>;
1403 assigned-clock-rates = <676000000>;
1406 cru: clock-controller@ff760000 {
1407 compatible = "rockchip,rk3399-cru";
1408 reg = <0x0 0xff760000 0x0 0x1000>;
1412 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1413 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1414 <&cru ARMCLKL>, <&cru ARMCLKB>,
1415 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1416 <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1417 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1419 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1420 <&cru PCLK_PERILP0>,
1421 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1422 assigned-clock-rates =
1423 <400000000>, <200000000>,
1424 <400000000>, <200000000>,
1425 <816000000>, <816000000>,
1426 <594000000>, <800000000>,
1427 <200000000>, <1000000000>,
1428 <150000000>, <75000000>,
1430 <100000000>, <100000000>,
1432 <100000000>, <50000000>;
1435 grf: syscon@ff770000 {
1436 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1437 reg = <0x0 0xff770000 0x0 0x10000>;
1438 #address-cells = <1>;
1441 io_domains: io-domains {
1442 compatible = "rockchip,rk3399-io-voltage-domain";
1443 status = "disabled";
1446 emmc_phy: phy@f780 {
1447 compatible = "rockchip,rk3399-emmc-phy";
1448 reg = <0xf780 0x24>;
1450 clock-names = "emmcclk";
1452 status = "disabled";
1455 u2phy0: usb2-phy@e450 {
1456 compatible = "rockchip,rk3399-usb2phy";
1457 reg = <0xe450 0x10>;
1458 clocks = <&cru SCLK_USB2PHY0_REF>;
1459 clock-names = "phyclk";
1461 clock-output-names = "clk_usbphy0_480m";
1462 status = "disabled";
1464 u2phy0_otg: otg-port {
1466 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1467 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1468 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1469 interrupt-names = "otg-bvalid", "otg-id",
1471 status = "disabled";
1474 u2phy0_host: host-port {
1476 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1477 interrupt-names = "linestate";
1478 status = "disabled";
1482 u2phy1: usb2-phy@e460 {
1483 compatible = "rockchip,rk3399-usb2phy";
1484 reg = <0xe460 0x10>;
1485 clocks = <&cru SCLK_USB2PHY1_REF>;
1486 clock-names = "phyclk";
1488 clock-output-names = "clk_usbphy1_480m";
1489 status = "disabled";
1491 u2phy1_otg: otg-port {
1493 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1494 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1495 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1496 interrupt-names = "otg-bvalid", "otg-id",
1498 status = "disabled";
1501 u2phy1_host: host-port {
1503 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1504 interrupt-names = "linestate";
1505 status = "disabled";
1510 compatible = "rockchip,rk3399-pvtm";
1511 clocks = <&cru SCLK_PVTM_CORE_L>,
1512 <&cru SCLK_PVTM_CORE_B>,
1513 <&cru SCLK_PVTM_GPU>,
1514 <&cru SCLK_PVTM_DDR>;
1515 clock-names = "core_l", "core_b", "gpu", "ddr";
1516 status = "disabled";
1520 tcphy0: phy@ff7c0000 {
1521 compatible = "rockchip,rk3399-typec-phy";
1522 reg = <0x0 0xff7c0000 0x0 0x40000>;
1523 rockchip,grf = <&grf>;
1525 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1526 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1527 clock-names = "tcpdcore", "tcpdphy-ref";
1528 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1529 assigned-clock-rates = <50000000>;
1530 power-domains = <&power RK3399_PD_TCPD0>;
1531 resets = <&cru SRST_UPHY0>,
1532 <&cru SRST_UPHY0_PIPE_L00>,
1533 <&cru SRST_P_UPHY0_TCPHY>;
1534 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1535 rockchip,typec-conn-dir = <0xe580 0 16>;
1536 rockchip,usb3tousb2-en = <0xe580 3 19>;
1537 rockchip,usb3-host-disable = <0x2434 0 16>;
1538 rockchip,usb3-host-port = <0x2434 12 28>;
1539 rockchip,external-psm = <0xe588 14 30>;
1540 rockchip,pipe-status = <0xe5c0 0 0>;
1541 rockchip,uphy-dp-sel = <0x6268 19 19>;
1542 status = "disabled";
1544 tcphy0_dp: dp-port {
1548 tcphy0_usb3: usb3-port {
1553 tcphy1: phy@ff800000 {
1554 compatible = "rockchip,rk3399-typec-phy";
1555 reg = <0x0 0xff800000 0x0 0x40000>;
1556 rockchip,grf = <&grf>;
1558 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1559 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1560 clock-names = "tcpdcore", "tcpdphy-ref";
1561 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1562 assigned-clock-rates = <50000000>;
1563 power-domains = <&power RK3399_PD_TCPD1>;
1564 resets = <&cru SRST_UPHY1>,
1565 <&cru SRST_UPHY1_PIPE_L00>,
1566 <&cru SRST_P_UPHY1_TCPHY>;
1567 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1568 rockchip,typec-conn-dir = <0xe58c 0 16>;
1569 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1570 rockchip,usb3-host-disable = <0x2444 0 16>;
1571 rockchip,usb3-host-port = <0x2444 12 28>;
1572 rockchip,external-psm = <0xe594 14 30>;
1573 rockchip,pipe-status = <0xe5c0 16 16>;
1574 rockchip,uphy-dp-sel = <0x6268 3 19>;
1575 status = "disabled";
1577 tcphy1_dp: dp-port {
1581 tcphy1_usb3: usb3-port {
1587 compatible = "snps,dw-wdt";
1588 reg = <0x0 0xff848000 0x0 0x100>;
1589 clocks = <&cru PCLK_WDT>;
1590 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1593 rktimer: rktimer@ff850000 {
1594 compatible = "rockchip,rk3399-timer";
1595 reg = <0x0 0xff850000 0x0 0x1000>;
1596 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1597 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1598 clock-names = "pclk", "timer";
1601 spdif: spdif@ff870000 {
1602 compatible = "rockchip,rk3399-spdif";
1603 reg = <0x0 0xff870000 0x0 0x1000>;
1604 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1605 dmas = <&dmac_bus 7>;
1607 clock-names = "mclk", "hclk";
1608 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1609 pinctrl-names = "default";
1610 pinctrl-0 = <&spdif_bus>;
1611 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1612 status = "disabled";
1615 i2s0: i2s@ff880000 {
1616 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1617 reg = <0x0 0xff880000 0x0 0x1000>;
1618 rockchip,grf = <&grf>;
1619 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1620 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1621 dma-names = "tx", "rx";
1622 clock-names = "i2s_clk", "i2s_hclk";
1623 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1624 pinctrl-names = "default";
1625 pinctrl-0 = <&i2s0_8ch_bus>;
1626 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1627 status = "disabled";
1630 i2s1: i2s@ff890000 {
1631 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1632 reg = <0x0 0xff890000 0x0 0x1000>;
1633 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1634 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1635 dma-names = "tx", "rx";
1636 clock-names = "i2s_clk", "i2s_hclk";
1637 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1638 pinctrl-names = "default";
1639 pinctrl-0 = <&i2s1_2ch_bus>;
1640 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1641 status = "disabled";
1644 i2s2: i2s@ff8a0000 {
1645 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1646 reg = <0x0 0xff8a0000 0x0 0x1000>;
1647 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1648 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1649 dma-names = "tx", "rx";
1650 clock-names = "i2s_clk", "i2s_hclk";
1651 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1652 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1653 status = "disabled";
1657 compatible = "arm,malit860",
1662 reg = <0x0 0xff9a0000 0x0 0x10000>;
1664 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1665 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1666 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1667 interrupt-names = "GPU", "JOB", "MMU";
1669 clocks = <&cru ACLK_GPU>;
1670 clock-names = "clk_mali";
1671 #cooling-cells = <2>; /* min followed by max */
1672 power-domains = <&power RK3399_PD_GPU>;
1673 power-off-delay-ms = <200>;
1674 status = "disabled";
1676 gpu_power_model: power_model {
1677 compatible = "arm,mali-simple-power-model";
1680 static-power = <300>;
1681 dynamic-power = <396>;
1682 ts = <32000 4700 (-80) 2>;
1683 thermal-zone = "gpu-thermal";
1687 vopl: vop@ff8f0000 {
1688 compatible = "rockchip,rk3399-vop-lit";
1689 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1690 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1691 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1692 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1693 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1694 reset-names = "axi", "ahb", "dclk";
1695 power-domains = <&power RK3399_PD_VOPL>;
1696 iommus = <&vopl_mmu>;
1697 status = "disabled";
1700 #address-cells = <1>;
1703 vopl_out_mipi: endpoint@0 {
1705 remote-endpoint = <&mipi_in_vopl>;
1708 vopl_out_edp: endpoint@1 {
1710 remote-endpoint = <&edp_in_vopl>;
1713 vopl_out_hdmi: endpoint@2 {
1715 remote-endpoint = <&hdmi_in_vopl>;
1718 vopl_out_dp: endpoint@3 {
1720 remote-endpoint = <&dp_in_vopl>;
1725 vop1_pwm: voppwm@ff8f01a0 {
1726 compatible = "rockchip,vop-pwm";
1727 reg = <0x0 0xff8f01a0 0x0 0x10>;
1729 pinctrl-names = "default";
1730 pinctrl-0 = <&vop1_pwm_pin>;
1731 clocks = <&cru SCLK_VOP1_PWM>;
1732 clock-names = "pwm";
1733 status = "disabled";
1736 vopl_mmu: iommu@ff8f3f00 {
1737 compatible = "rockchip,iommu";
1738 reg = <0x0 0xff8f3f00 0x0 0x100>;
1739 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1740 interrupt-names = "vopl_mmu";
1742 status = "disabled";
1745 vopb: vop@ff900000 {
1746 compatible = "rockchip,rk3399-vop-big";
1747 reg = <0x0 0xff900000 0x0 0x3efc>;
1748 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1749 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1750 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1751 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1752 reset-names = "axi", "ahb", "dclk";
1753 power-domains = <&power RK3399_PD_VOPB>;
1754 iommus = <&vopb_mmu>;
1755 status = "disabled";
1758 #address-cells = <1>;
1761 vopb_out_edp: endpoint@0 {
1763 remote-endpoint = <&edp_in_vopb>;
1766 vopb_out_mipi: endpoint@1 {
1768 remote-endpoint = <&mipi_in_vopb>;
1771 vopb_out_hdmi: endpoint@2 {
1773 remote-endpoint = <&hdmi_in_vopb>;
1776 vopb_out_dp: endpoint@3 {
1778 remote-endpoint = <&dp_in_vopb>;
1783 vop0_pwm: voppwm@ff9001a0 {
1784 compatible = "rockchip,vop-pwm";
1785 reg = <0x0 0xff9001a0 0x0 0x10>;
1787 pinctrl-names = "default";
1788 pinctrl-0 = <&vop0_pwm_pin>;
1789 clocks = <&cru SCLK_VOP0_PWM>;
1790 clock-names = "pwm";
1791 status = "disabled";
1794 vopb_mmu: iommu@ff903f00 {
1795 compatible = "rockchip,iommu";
1796 reg = <0x0 0xff903f00 0x0 0x100>;
1797 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1798 interrupt-names = "vopb_mmu";
1800 status = "disabled";
1803 isp0_mmu: iommu@ff914000 {
1804 compatible = "rockchip,iommu";
1805 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1806 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1807 interrupt-names = "isp0_mmu";
1809 rk_iommu,disable_reset_quirk;
1810 status = "disabled";
1813 isp1_mmu: iommu@ff924000 {
1814 compatible = "rockchip,iommu";
1815 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1816 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1817 interrupt-names = "isp1_mmu";
1819 rk_iommu,disable_reset_quirk;
1820 status = "disabled";
1823 hdmi: hdmi@ff940000 {
1824 compatible = "rockchip,rk3399-dw-hdmi";
1825 reg = <0x0 0xff940000 0x0 0x20000>;
1827 rockchip,grf = <&grf>;
1828 power-domains = <&power RK3399_PD_HDCP>;
1829 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1830 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1831 clock-names = "iahb", "isfr", "vpll", "grf";
1832 status = "disabled";
1836 #address-cells = <1>;
1838 hdmi_in_vopb: endpoint@0 {
1840 remote-endpoint = <&vopb_out_hdmi>;
1842 hdmi_in_vopl: endpoint@1 {
1844 remote-endpoint = <&vopl_out_hdmi>;
1850 mipi_dsi: mipi@ff960000 {
1851 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1852 reg = <0x0 0xff960000 0x0 0x8000>;
1853 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1854 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1855 <&cru SCLK_DPHY_TX0_CFG>;
1856 clock-names = "ref", "pclk", "phy_cfg";
1857 power-domains = <&power RK3399_PD_VIO>;
1858 rockchip,grf = <&grf>;
1859 #address-cells = <1>;
1861 status = "disabled";
1864 #address-cells = <1>;
1869 #address-cells = <1>;
1872 mipi_in_vopb: endpoint@0 {
1874 remote-endpoint = <&vopb_out_mipi>;
1876 mipi_in_vopl: endpoint@1 {
1878 remote-endpoint = <&vopl_out_mipi>;
1885 compatible = "rockchip,rk3399-edp";
1886 reg = <0x0 0xff970000 0x0 0x8000>;
1887 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1888 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1889 clock-names = "dp", "pclk";
1890 power-domains = <&power RK3399_PD_EDP>;
1891 resets = <&cru SRST_P_EDP_CTRL>;
1893 rockchip,grf = <&grf>;
1894 status = "disabled";
1895 pinctrl-names = "default";
1896 pinctrl-0 = <&edp_hpd>;
1899 #address-cells = <1>;
1904 #address-cells = <1>;
1907 edp_in_vopb: endpoint@0 {
1909 remote-endpoint = <&vopb_out_edp>;
1912 edp_in_vopl: endpoint@1 {
1914 remote-endpoint = <&vopl_out_edp>;
1920 display_subsystem: display-subsystem {
1921 compatible = "rockchip,display-subsystem";
1922 ports = <&vopl_out>, <&vopb_out>;
1923 status = "disabled";
1927 compatible = "rockchip,rk3399-pinctrl";
1928 rockchip,grf = <&grf>;
1929 rockchip,pmu = <&pmugrf>;
1930 #address-cells = <0x2>;
1931 #size-cells = <0x2>;
1934 gpio0: gpio0@ff720000 {
1935 compatible = "rockchip,gpio-bank";
1936 reg = <0x0 0xff720000 0x0 0x100>;
1937 clocks = <&pmucru PCLK_GPIO0_PMU>;
1938 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1941 #gpio-cells = <0x2>;
1943 interrupt-controller;
1944 #interrupt-cells = <0x2>;
1947 gpio1: gpio1@ff730000 {
1948 compatible = "rockchip,gpio-bank";
1949 reg = <0x0 0xff730000 0x0 0x100>;
1950 clocks = <&pmucru PCLK_GPIO1_PMU>;
1951 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1954 #gpio-cells = <0x2>;
1956 interrupt-controller;
1957 #interrupt-cells = <0x2>;
1960 gpio2: gpio2@ff780000 {
1961 compatible = "rockchip,gpio-bank";
1962 reg = <0x0 0xff780000 0x0 0x100>;
1963 clocks = <&cru PCLK_GPIO2>;
1964 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1967 #gpio-cells = <0x2>;
1969 interrupt-controller;
1970 #interrupt-cells = <0x2>;
1973 gpio3: gpio3@ff788000 {
1974 compatible = "rockchip,gpio-bank";
1975 reg = <0x0 0xff788000 0x0 0x100>;
1976 clocks = <&cru PCLK_GPIO3>;
1977 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1980 #gpio-cells = <0x2>;
1982 interrupt-controller;
1983 #interrupt-cells = <0x2>;
1986 gpio4: gpio4@ff790000 {
1987 compatible = "rockchip,gpio-bank";
1988 reg = <0x0 0xff790000 0x0 0x100>;
1989 clocks = <&cru PCLK_GPIO4>;
1990 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1993 #gpio-cells = <0x2>;
1995 interrupt-controller;
1996 #interrupt-cells = <0x2>;
1999 pcfg_pull_up: pcfg-pull-up {
2003 pcfg_pull_down: pcfg-pull-down {
2007 pcfg_pull_none: pcfg-pull-none {
2011 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2013 drive-strength = <20>;
2016 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2018 drive-strength = <20>;
2021 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2023 drive-strength = <18>;
2026 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2028 drive-strength = <12>;
2031 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2033 drive-strength = <8>;
2036 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2038 drive-strength = <4>;
2041 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2043 drive-strength = <2>;
2046 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2048 drive-strength = <12>;
2051 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2053 drive-strength = <13>;
2056 pcfg_output_high: pcfg-output-high {
2060 pcfg_output_low: pcfg-output-low {
2064 pcfg_input: pcfg-input {
2069 emmc_pwr: emmc-pwr {
2071 <0 5 RK_FUNC_1 &pcfg_pull_up>;
2076 rgmii_pins: rgmii-pins {
2079 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2081 <3 14 RK_FUNC_1 &pcfg_pull_none>,
2083 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2085 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2087 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2089 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2091 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2093 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2095 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2097 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2099 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2101 <3 3 RK_FUNC_1 &pcfg_pull_none>,
2103 <3 2 RK_FUNC_1 &pcfg_pull_none>,
2105 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2107 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2110 rmii_pins: rmii-pins {
2113 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2115 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2117 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2119 <3 10 RK_FUNC_1 &pcfg_pull_none>,
2121 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2123 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2125 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2127 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2129 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2131 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2136 i2c0_xfer: i2c0-xfer {
2138 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2139 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2144 i2c1_xfer: i2c1-xfer {
2146 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2147 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2152 i2c2_xfer: i2c2-xfer {
2154 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2155 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2160 i2c3_xfer: i2c3-xfer {
2162 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2163 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2166 i2c3_gpio: i2c3_gpio {
2168 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2169 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2175 i2c4_xfer: i2c4-xfer {
2177 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2178 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2183 i2c5_xfer: i2c5-xfer {
2185 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2186 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2191 i2c6_xfer: i2c6-xfer {
2193 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2194 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2199 i2c7_xfer: i2c7-xfer {
2201 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2202 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2207 i2c8_xfer: i2c8-xfer {
2209 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2210 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2215 i2s0_8ch_bus: i2s0-8ch-bus {
2217 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2218 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2219 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2220 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2221 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2222 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2223 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2224 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2225 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2230 i2s1_2ch_bus: i2s1-2ch-bus {
2232 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2233 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2234 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2235 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2236 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2241 sdio0_bus1: sdio0-bus1 {
2243 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2246 sdio0_bus4: sdio0-bus4 {
2248 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2249 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2250 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2251 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2254 sdio0_cmd: sdio0-cmd {
2256 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2259 sdio0_clk: sdio0-clk {
2261 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2264 sdio0_cd: sdio0-cd {
2266 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2269 sdio0_pwr: sdio0-pwr {
2271 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2274 sdio0_bkpwr: sdio0-bkpwr {
2276 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2279 sdio0_wp: sdio0-wp {
2281 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2284 sdio0_int: sdio0-int {
2286 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2291 sdmmc_bus1: sdmmc-bus1 {
2293 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2296 sdmmc_bus4: sdmmc-bus4 {
2298 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2299 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2300 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2301 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2304 sdmmc_clk: sdmmc-clk {
2306 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2309 sdmmc_cmd: sdmmc-cmd {
2311 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2314 sdmmc_cd: sdmcc-cd {
2316 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2319 sdmmc_wp: sdmmc-wp {
2321 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2326 spdif_bus: spdif-bus {
2328 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2331 spdif_bus_1: spdif-bus-1 {
2333 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2338 spi0_clk: spi0-clk {
2340 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2342 spi0_cs0: spi0-cs0 {
2344 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2346 spi0_cs1: spi0-cs1 {
2348 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2352 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2356 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2361 spi1_clk: spi1-clk {
2363 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2365 spi1_cs0: spi1-cs0 {
2367 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2371 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2375 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2380 spi2_clk: spi2-clk {
2382 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2384 spi2_cs0: spi2-cs0 {
2386 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2390 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2394 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2399 spi3_clk: spi3-clk {
2401 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2403 spi3_cs0: spi3-cs0 {
2405 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2409 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2413 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2418 spi4_clk: spi4-clk {
2420 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2422 spi4_cs0: spi4-cs0 {
2424 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2428 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2432 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2437 spi5_clk: spi5-clk {
2439 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2441 spi5_cs0: spi5-cs0 {
2443 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2447 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2451 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2456 otp_gpio: otp-gpio {
2457 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2461 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2466 uart0_xfer: uart0-xfer {
2468 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2469 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2472 uart0_cts: uart0-cts {
2474 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2477 uart0_rts: uart0-rts {
2479 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2484 uart1_xfer: uart1-xfer {
2486 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2487 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2492 uart2a_xfer: uart2a-xfer {
2494 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2495 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2500 uart2b_xfer: uart2b-xfer {
2502 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2503 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2508 uart2c_xfer: uart2c-xfer {
2510 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2511 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2516 uart3_xfer: uart3-xfer {
2518 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2519 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2522 uart3_cts: uart3-cts {
2524 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2527 uart3_rts: uart3-rts {
2529 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2534 uart4_xfer: uart4-xfer {
2536 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2537 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2542 uarthdcp_xfer: uarthdcp-xfer {
2544 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2545 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2550 pwm0_pin: pwm0-pin {
2552 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2555 vop0_pwm_pin: vop0-pwm-pin {
2557 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2562 pwm1_pin: pwm1-pin {
2564 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2567 vop1_pwm_pin: vop1-pwm-pin {
2569 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2574 pwm2_pin: pwm2-pin {
2576 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2581 pwm3a_pin: pwm3a-pin {
2583 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2588 pwm3b_pin: pwm3b-pin {
2590 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2597 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2602 hdmi_i2c_xfer: hdmi-i2c-xfer {
2604 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2605 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2608 hdmi_cec: hdmi-cec {
2610 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2615 pcie_clkreqn: pci-clkreqn {
2617 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2620 pcie_clkreqnb: pci-clkreqnb {
2622 <4 24 RK_FUNC_1 &pcfg_pull_none>;
2625 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2627 * Since our pcie doesn't support
2628 * ClockPM(CPM), we want to hack this as
2629 * gpio, so the EP could be able to
2630 * de-assert it along and make ClockPM(CPM)
2634 <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2637 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2639 <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2644 rockchip_suspend: rockchip-suspend {
2645 compatible = "rockchip,pm-rk3399";
2646 status = "disabled";
2647 rockchip,sleep-debug-en = <0>;
2648 rockchip,virtual-poweroff = <0>;
2649 rockchip,sleep-mode-config = <
2656 | RKPM_SLP_CENTER_PD
2657 | RKPM_SLP_AP_PWROFF
2660 rockchip,wakeup-config = <