2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
75 compatible = "arm,psci-1.0";
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 clocks = <&cru ARMCLKL>;
116 operating-points-v2 = <&cluster0_opp>;
121 compatible = "arm,cortex-a53", "arm,armv8";
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 operating-points-v2 = <&cluster0_opp>;
130 compatible = "arm,cortex-a53", "arm,armv8";
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster0_opp>;
148 compatible = "arm,cortex-a72", "arm,armv8";
150 enable-method = "psci";
151 #cooling-cells = <2>; /* min followed by max */
152 clocks = <&cru ARMCLKB>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a72", "arm,armv8";
160 enable-method = "psci";
161 clocks = <&cru ARMCLKB>;
162 operating-points-v2 = <&cluster1_opp>;
166 cluster0_opp: opp_table0 {
167 compatible = "operating-points-v2";
171 opp-hz = /bits/ 64 <408000000>;
172 opp-microvolt = <900000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <600000000>;
177 opp-microvolt = <900000>;
180 opp-hz = /bits/ 64 <816000000>;
181 opp-microvolt = <900000>;
184 opp-hz = /bits/ 64 <1008000000>;
185 opp-microvolt = <900000>;
189 cluster1_opp: opp_table1 {
190 compatible = "operating-points-v2";
194 opp-hz = /bits/ 64 <408000000>;
195 opp-microvolt = <900000>;
196 clock-latency-ns = <40000>;
199 opp-hz = /bits/ 64 <600000000>;
200 opp-microvolt = <900000>;
203 opp-hz = /bits/ 64 <816000000>;
204 opp-microvolt = <900000>;
207 opp-hz = /bits/ 64 <1008000000>;
208 opp-microvolt = <900000>;
211 opp-hz = /bits/ 64 <1200000000>;
212 opp-microvolt = <900000>;
217 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
219 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
220 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
221 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
225 compatible = "arm,armv8-pmuv3";
226 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
230 compatible = "fixed-clock";
232 clock-frequency = <24000000>;
233 clock-output-names = "xin24m";
237 compatible = "arm,amba-bus";
238 #address-cells = <2>;
242 dmac_bus: dma-controller@ff6d0000 {
243 compatible = "arm,pl330", "arm,primecell";
244 reg = <0x0 0xff6d0000 0x0 0x4000>;
245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cru ACLK_DMAC0_PERILP>;
249 clock-names = "apb_pclk";
252 dmac_peri: dma-controller@ff6e0000 {
253 compatible = "arm,pl330", "arm,primecell";
254 reg = <0x0 0xff6e0000 0x0 0x4000>;
255 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cru ACLK_DMAC1_PERILP>;
259 clock-names = "apb_pclk";
264 compatible = "rockchip,rk3399-gmac";
265 reg = <0x0 0xfe300000 0x0 0x10000>;
266 rockchip,grf = <&grf>;
267 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-names = "macirq";
269 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
270 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
271 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
273 clock-names = "stmmaceth", "mac_clk_rx",
274 "mac_clk_tx", "clk_mac_ref",
275 "clk_mac_refout", "aclk_mac",
277 resets = <&cru SRST_A_GMAC>;
278 reset-names = "stmmaceth";
283 compatible = "rockchip,rk3399-emmc-phy";
284 reg-offset = <0xf780>;
286 rockchip,grf = <&grf>;
290 sdio0: dwmmc@fe310000 {
291 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
292 reg = <0x0 0xfe310000 0x0 0x4000>;
293 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
294 clock-freq-min-max = <400000 150000000>;
295 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
296 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
297 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
298 fifo-depth = <0x100>;
302 sdmmc: dwmmc@fe320000 {
303 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
304 reg = <0x0 0xfe320000 0x0 0x4000>;
305 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
306 clock-freq-min-max = <400000 150000000>;
307 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
308 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
309 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
310 fifo-depth = <0x100>;
314 sdhci: sdhci@fe330000 {
315 compatible = "arasan,sdhci-5.1";
316 reg = <0x0 0xfe330000 0x0 0x10000>;
317 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
319 clock-names = "clk_xin", "clk_ahb";
321 phy-names = "phy_arasan";
326 compatible = "rockchip,rk3399-usb-phy";
327 rockchip,grf = <&grf>;
328 vbus_drv-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
329 #address-cells = <1>;
332 usb2phy0: usb2-phy0 {
338 usb2phy1: usb2-phy1 {
345 usb_host0_echi: usb@fe380000 {
346 compatible = "generic-ehci";
347 reg = <0x0 0xfe380000 0x0 0x20000>;
348 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
350 clock-names = "hclk_host0", "hclk_host0_arb";
352 phy-names = "usb2_phy0";
356 usb_host0_ohci: usb@fe3a0000 {
357 compatible = "generic-ohci";
358 reg = <0x0 0xfe3a0000 0x0 0x20000>;
359 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
361 clock-names = "hclk_host0", "hclk_host0_arb";
365 usb_host1_echi: usb@fe3c0000 {
366 compatible = "generic-ehci";
367 reg = <0x0 0xfe3c0000 0x0 0x20000>;
368 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
370 clock-names = "hclk_host1", "hclk_host1_arb";
372 phy-names = "usb2_phy1";
376 usb_host1_ohci: usb@fe3e0000 {
377 compatible = "generic-ohci";
378 reg = <0x0 0xfe3e0000 0x0 0x20000>;
379 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
381 clock-names = "hclk_host1", "hclk_host1_arb";
385 usbdrd3_0: usb@fe800000 {
386 compatible = "rockchip,dwc3";
387 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
388 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
389 <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
390 <&cru ACLK_USB3_GRF>;
391 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
392 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
393 "aclk_usb3", "aclk_usb3_noc",
395 #address-cells = <2>;
399 usbdrd_dwc3_0: dwc3 {
400 compatible = "snps,dwc3";
401 reg = <0x0 0xfe800000 0x0 0x100000>;
402 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
405 snps,dis_enblslpm_quirk;
406 snps,phyif_utmi_16_bits;
407 snps,dis_u2_freeclk_exists_quirk;
408 snps,dis_del_phy_power_chg_quirk;
413 usbdrd3_1: usb@fe900000 {
414 compatible = "rockchip,dwc3";
415 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
416 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
417 <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
418 <&cru ACLK_USB3_GRF>;
419 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
420 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
421 "aclk_usb3", "aclk_usb3_noc",
423 #address-cells = <2>;
427 usbdrd_dwc3_1: dwc3 {
428 compatible = "snps,dwc3";
429 reg = <0x0 0xfe900000 0x0 0x100000>;
430 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
433 snps,dis_enblslpm_quirk;
434 snps,phyif_utmi_16_bits;
435 snps,dis_u2_freeclk_exists_quirk;
436 snps,dis_del_phy_power_chg_quirk;
441 gic: interrupt-controller@fee00000 {
442 compatible = "arm,gic-v3";
443 #interrupt-cells = <3>;
444 #address-cells = <2>;
447 interrupt-controller;
449 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
450 <0x0 0xfef00000 0 0xc0000>, /* GICR */
451 <0x0 0xfff00000 0 0x10000>, /* GICC */
452 <0x0 0xfff10000 0 0x10000>, /* GICH */
453 <0x0 0xfff20000 0 0x10000>; /* GICV */
454 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
455 its: interrupt-controller@fee20000 {
456 compatible = "arm,gic-v3-its";
458 reg = <0x0 0xfee20000 0x0 0x20000>;
462 saradc: saradc@ff100000 {
463 compatible = "rockchip,rk3399-saradc";
464 reg = <0x0 0xff100000 0x0 0x100>;
465 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
466 #io-channel-cells = <1>;
467 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
468 clock-names = "saradc", "apb_pclk";
473 compatible = "rockchip,rk3399-i2c";
474 reg = <0x0 0xff3c0000 0x0 0x1000>;
475 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
476 clock-names = "i2c", "pclk";
477 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&i2c0_xfer>;
480 #address-cells = <1>;
486 compatible = "rockchip,rk3399-i2c";
487 reg = <0x0 0xff110000 0x0 0x1000>;
488 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
489 clock-names = "i2c", "pclk";
490 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&i2c1_xfer>;
493 #address-cells = <1>;
499 compatible = "rockchip,rk3399-i2c";
500 reg = <0x0 0xff120000 0x0 0x1000>;
501 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
502 clock-names = "i2c", "pclk";
503 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&i2c2_xfer>;
506 #address-cells = <1>;
512 compatible = "rockchip,rk3399-i2c";
513 reg = <0x0 0xff130000 0x0 0x1000>;
514 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
515 clock-names = "i2c", "pclk";
516 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&i2c3_xfer>;
519 #address-cells = <1>;
525 compatible = "rockchip,rk3399-i2c";
526 reg = <0x0 0xff140000 0x0 0x1000>;
527 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
528 clock-names = "i2c", "pclk";
529 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&i2c5_xfer>;
532 #address-cells = <1>;
538 compatible = "rockchip,rk3399-i2c";
539 reg = <0x0 0xff150000 0x0 0x1000>;
540 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
541 clock-names = "i2c", "pclk";
542 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&i2c6_xfer>;
545 #address-cells = <1>;
551 compatible = "rockchip,rk3399-i2c";
552 reg = <0x0 0xff160000 0x0 0x1000>;
553 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
554 clock-names = "i2c", "pclk";
555 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c7_xfer>;
558 #address-cells = <1>;
563 uart0: serial@ff180000 {
564 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
565 reg = <0x0 0xff180000 0x0 0x100>;
566 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
567 clock-names = "baudclk", "apb_pclk";
568 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
576 uart1: serial@ff190000 {
577 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
578 reg = <0x0 0xff190000 0x0 0x100>;
579 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
580 clock-names = "baudclk", "apb_pclk";
581 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&uart1_xfer>;
589 uart2: serial@ff1a0000 {
590 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
591 reg = <0x0 0xff1a0000 0x0 0x100>;
592 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
593 clock-names = "baudclk", "apb_pclk";
594 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&uart2c_xfer>;
602 uart3: serial@ff1b0000 {
603 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
604 reg = <0x0 0xff1b0000 0x0 0x100>;
605 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
606 clock-names = "baudclk", "apb_pclk";
607 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
616 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
617 reg = <0x0 0xff1c0000 0x0 0x1000>;
618 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
619 clock-names = "spiclk", "apb_pclk";
620 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
623 #address-cells = <1>;
629 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
630 reg = <0x0 0xff1d0000 0x0 0x1000>;
631 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
632 clock-names = "spiclk", "apb_pclk";
633 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
636 #address-cells = <1>;
642 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
643 reg = <0x0 0xff1e0000 0x0 0x1000>;
644 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
645 clock-names = "spiclk", "apb_pclk";
646 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
649 #address-cells = <1>;
655 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
656 reg = <0x0 0xff1f0000 0x0 0x1000>;
657 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
658 clock-names = "spiclk", "apb_pclk";
659 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
662 #address-cells = <1>;
668 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
669 reg = <0x0 0xff200000 0x0 0x1000>;
670 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
671 clock-names = "spiclk", "apb_pclk";
672 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
675 #address-cells = <1>;
681 #include "rk3368-thermal.dtsi"
684 tsadc: tsadc@ff260000 {
685 compatible = "rockchip,rk3399-tsadc";
686 reg = <0x0 0xff260000 0x0 0x100>;
687 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
688 rockchip,grf = <&grf>;
689 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
690 clock-names = "tsadc", "apb_pclk";
691 assigned-clocks = <&cru SCLK_TSADC>;
692 assigned-clock-rates = <750000>;
693 resets = <&cru SRST_TSADC>;
694 reset-names = "tsadc-apb";
695 pinctrl-names = "init", "default", "sleep";
696 pinctrl-0 = <&otp_gpio>;
697 pinctrl-1 = <&otp_out>;
698 pinctrl-2 = <&otp_gpio>;
699 #thermal-sensor-cells = <1>;
700 rockchip,hw-tshut-temp = <95000>;
704 pmu: power-management@ff31000 {
705 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
706 reg = <0x0 0xff310000 0x0 0x1000>;
708 power: power-controller {
710 compatible = "rockchip,rk3399-power-controller";
711 #power-domain-cells = <1>;
712 #address-cells = <1>;
716 reg = <RK3399_PD_CENTER>;
717 #address-cells = <1>;
721 reg = <RK3399_PD_VDU>;
724 reg = <RK3399_PD_VCODEC>;
727 reg = <RK3399_PD_IEP>;
730 reg = <RK3399_PD_RGA>;
734 reg = <RK3399_PD_VIO>;
735 #address-cells = <1>;
739 reg = <RK3399_PD_ISP0>;
742 reg = <RK3399_PD_ISP1>;
745 reg = <RK3399_PD_HDCP>;
748 reg = <RK3399_PD_VO>;
749 #address-cells = <1>;
753 reg = <RK3399_PD_VOPB>;
756 reg = <RK3399_PD_VOPL>;
761 reg = <RK3399_PD_GPU>;
766 pmugrf: syscon@ff320000 {
767 compatible = "rockchip,rk3399-pmugrf", "syscon";
768 reg = <0x0 0xff320000 0x0 0x1000>;
772 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
773 reg = <0x0 0xff350000 0x0 0x1000>;
774 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
775 clock-names = "spiclk", "apb_pclk";
776 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
777 pinctrl-names = "default";
778 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
779 #address-cells = <1>;
784 uart4: serial@ff370000 {
785 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
786 reg = <0x0 0xff370000 0x0 0x100>;
787 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
788 clock-names = "baudclk", "apb_pclk";
789 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
792 pinctrl-names = "default";
793 pinctrl-0 = <&uart4_xfer>;
798 compatible = "rockchip,rk3399-i2c";
799 reg = <0x0 0xff3d0000 0x0 0x1000>;
800 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
801 clock-names = "i2c", "pclk";
802 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
803 pinctrl-names = "default";
804 pinctrl-0 = <&i2c4_xfer>;
805 #address-cells = <1>;
811 compatible = "rockchip,rk3399-i2c";
812 reg = <0x0 0xff3e0000 0x0 0x1000>;
813 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
814 clock-names = "i2c", "pclk";
815 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
816 pinctrl-names = "default";
817 pinctrl-0 = <&i2c8_xfer>;
818 #address-cells = <1>;
824 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
825 reg = <0x0 0xff420000 0x0 0x10>;
827 pinctrl-names = "default";
828 pinctrl-0 = <&pwm0_pin>;
829 clocks = <&pmucru PCLK_RKPWM_PMU>;
835 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
836 reg = <0x0 0xff420010 0x0 0x10>;
838 pinctrl-names = "default";
839 pinctrl-0 = <&pwm1_pin>;
840 clocks = <&pmucru PCLK_RKPWM_PMU>;
846 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
847 reg = <0x0 0xff420020 0x0 0x10>;
849 pinctrl-names = "default";
850 pinctrl-0 = <&pwm2_pin>;
851 clocks = <&pmucru PCLK_RKPWM_PMU>;
857 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
858 reg = <0x0 0xff420030 0x0 0x10>;
860 pinctrl-names = "default";
861 pinctrl-0 = <&pwm3a_pin>;
862 clocks = <&pmucru PCLK_RKPWM_PMU>;
867 pmucru: pmu-clock-controller@ff750000 {
868 compatible = "rockchip,rk3399-pmucru";
869 reg = <0x0 0xff750000 0x0 0x1000>;
872 assigned-clocks = <&pmucru PLL_PPLL>;
873 assigned-clock-rates = <676000000>;
876 cru: clock-controller@ff760000 {
877 compatible = "rockchip,rk3399-cru";
878 reg = <0x0 0xff760000 0x0 0x1000>;
882 <&cru ARMCLKL>, <&cru ARMCLKB>,
883 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
885 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
887 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
889 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
890 assigned-clock-rates =
891 <816000000>, <1008000000>,
892 <594000000>, <800000000>,
894 <150000000>, <75000000>,
896 <100000000>, <100000000>,
898 <100000000>, <50000000>;
901 grf: syscon@ff770000 {
902 compatible = "rockchip,rk3399-grf", "syscon";
903 reg = <0x0 0xff770000 0x0 0x10000>;
906 wdt0: watchdog@ff840000 {
907 compatible = "snps,dw-wdt";
908 reg = <0x0 0xff840000 0x0 0x100>;
909 clocks = <&cru PCLK_WDT>;
910 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
914 spdif: spdif@ff870000 {
915 compatible = "rockchip,rk3399-spdif";
916 reg = <0x0 0xff870000 0x0 0x1000>;
917 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
918 dmas = <&dmac_bus 7>;
920 clock-names = "mclk", "hclk";
921 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
922 pinctrl-names = "default";
923 pinctrl-0 = <&spdif_bus>;
928 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
929 reg = <0x0 0xff880000 0x0 0x1000>;
930 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
931 #address-cells = <1>;
933 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
934 dma-names = "tx", "rx";
935 clock-names = "i2s_clk", "i2s_hclk";
936 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
937 pinctrl-names = "default";
938 pinctrl-0 = <&i2s0_8ch_bus>;
943 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
944 reg = <0x0 0xff890000 0x0 0x1000>;
945 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
946 #address-cells = <1>;
948 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
949 dma-names = "tx", "rx";
950 clock-names = "i2s_clk", "i2s_hclk";
951 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
952 pinctrl-names = "default";
953 pinctrl-0 = <&i2s1_2ch_bus>;
958 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
959 reg = <0x0 0xff8a0000 0x0 0x1000>;
960 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
961 #address-cells = <1>;
963 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
964 dma-names = "tx", "rx";
965 clock-names = "i2s_clk", "i2s_hclk";
966 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
971 compatible = "arm,malit860",
976 reg = <0x0 0xff9a0000 0x0 0x10000>;
978 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
981 interrupt-names = "GPU", "JOB", "MMU";
983 clocks = <&cru ACLK_GPU>;
984 clock-names = "clk_mali";
985 operating-points-v2 = <&gpu_opp_table>;
989 gpu_opp_table: gpu_opp_table {
990 compatible = "operating-points-v2";
994 opp-hz = /bits/ 64 <200000000>;
995 opp-microvolt = <900000>;
998 opp-hz = /bits/ 64 <300000000>;
999 opp-microvolt = <900000>;
1002 opp-hz = /bits/ 64 <400000000>;
1003 opp-microvolt = <900000>;
1006 opp-hz = /bits/ 64 <500000000>;
1007 opp-microvolt = <900000>;
1011 vopl: vop@ff8f0000 {
1012 compatible = "rockchip,rk3399-vop-lit";
1013 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1014 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1016 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1017 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1018 reset-names = "axi", "ahb", "dclk";
1019 iommus = <&vopl_mmu>;
1020 status = "disabled";
1023 #address-cells = <1>;
1028 vopl_mmu: iommu@ff8f3f00 {
1029 compatible = "rockchip,iommu";
1030 reg = <0x0 0xff8f3f00 0x0 0x100>;
1031 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1032 interrupt-names = "vopl_mmu";
1034 status = "disabled";
1037 vopb: vop@ff900000 {
1038 compatible = "rockchip,rk3399-vop-big";
1039 reg = <0x0 0xff900000 0x0 0x3efc>;
1040 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1042 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1043 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1044 reset-names = "axi", "ahb", "dclk";
1045 iommus = <&vopb_mmu>;
1046 status = "disabled";
1049 #address-cells = <1>;
1054 vopb_mmu: iommu@ff903f00 {
1055 compatible = "rockchip,iommu";
1056 reg = <0x0 0xff903f00 0x0 0x100>;
1057 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1058 interrupt-names = "vopb_mmu";
1060 status = "disabled";
1063 display_subsystem: display-subsystem {
1064 compatible = "rockchip,display-subsystem";
1065 ports = <&vopl_out>, <&vopb_out>;
1066 status = "disabled";
1070 compatible = "rockchip,rk3399-pinctrl";
1071 rockchip,grf = <&grf>;
1072 rockchip,pmu = <&pmugrf>;
1073 #address-cells = <0x2>;
1074 #size-cells = <0x2>;
1077 gpio0: gpio0@ff720000 {
1078 compatible = "rockchip,gpio-bank";
1079 reg = <0x0 0xff720000 0x0 0x100>;
1080 clocks = <&pmucru PCLK_GPIO0_PMU>;
1081 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1084 #gpio-cells = <0x2>;
1086 interrupt-controller;
1087 #interrupt-cells = <0x2>;
1090 gpio1: gpio1@ff730000 {
1091 compatible = "rockchip,gpio-bank";
1092 reg = <0x0 0xff730000 0x0 0x100>;
1093 clocks = <&pmucru PCLK_GPIO1_PMU>;
1094 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1097 #gpio-cells = <0x2>;
1099 interrupt-controller;
1100 #interrupt-cells = <0x2>;
1103 gpio2: gpio2@ff780000 {
1104 compatible = "rockchip,gpio-bank";
1105 reg = <0x0 0xff780000 0x0 0x100>;
1106 clocks = <&cru PCLK_GPIO2>;
1107 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1110 #gpio-cells = <0x2>;
1112 interrupt-controller;
1113 #interrupt-cells = <0x2>;
1116 gpio3: gpio3@ff788000 {
1117 compatible = "rockchip,gpio-bank";
1118 reg = <0x0 0xff788000 0x0 0x100>;
1119 clocks = <&cru PCLK_GPIO3>;
1120 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1123 #gpio-cells = <0x2>;
1125 interrupt-controller;
1126 #interrupt-cells = <0x2>;
1129 gpio4: gpio4@ff790000 {
1130 compatible = "rockchip,gpio-bank";
1131 reg = <0x0 0xff790000 0x0 0x100>;
1132 clocks = <&cru PCLK_GPIO4>;
1133 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1136 #gpio-cells = <0x2>;
1138 interrupt-controller;
1139 #interrupt-cells = <0x2>;
1142 pcfg_pull_up: pcfg-pull-up {
1146 pcfg_pull_down: pcfg-pull-down {
1150 pcfg_pull_none: pcfg-pull-none {
1154 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1156 drive-strength = <12>;
1159 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1161 drive-strength = <8>;
1164 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1166 drive-strength = <4>;
1169 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1171 drive-strength = <2>;
1174 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1176 drive-strength = <12>;
1180 emmc_pwr: emmc-pwr {
1182 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1187 rgmii_pins: rgmii-pins {
1190 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1192 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1194 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1196 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1198 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1200 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1202 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1204 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1206 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1208 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1210 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1212 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1214 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1216 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1218 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>;
1221 rmii_pins: rmii-pins {
1224 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1226 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1228 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1230 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1232 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1234 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1236 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1238 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1240 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1242 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>;
1247 i2c0_xfer: i2c0-xfer {
1249 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1250 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1255 i2c1_xfer: i2c1-xfer {
1257 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1258 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1263 i2c2_xfer: i2c2-xfer {
1265 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1266 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1271 i2c3_xfer: i2c3-xfer {
1273 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1274 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1279 i2c4_xfer: i2c4-xfer {
1281 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1282 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1287 i2c5_xfer: i2c5-xfer {
1289 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1290 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1295 i2c6_xfer: i2c6-xfer {
1297 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1298 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1303 i2c7_xfer: i2c7-xfer {
1305 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1306 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1311 i2c8_xfer: i2c8-xfer {
1313 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1314 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1319 i2s0_8ch_bus: i2s0-8ch-bus {
1321 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1322 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1323 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1324 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1325 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1326 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1327 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1328 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1329 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1334 i2s1_2ch_bus: i2s1-2ch-bus {
1336 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1337 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1338 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1339 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1340 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1345 sdio0_bus1: sdio0-bus1 {
1347 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1350 sdio0_bus4: sdio0-bus4 {
1352 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1353 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1354 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1355 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1358 sdio0_cmd: sdio0-cmd {
1360 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1363 sdio0_clk: sdio0-clk {
1365 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1368 sdio0_cd: sdio0-cd {
1370 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1373 sdio0_pwr: sdio0-pwr {
1375 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1378 sdio0_bkpwr: sdio0-bkpwr {
1380 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1383 sdio0_wp: sdio0-wp {
1385 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1388 sdio0_int: sdio0-int {
1390 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1395 sdmmc_bus1: sdmmc-bus1 {
1397 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1400 sdmmc_bus4: sdmmc-bus4 {
1402 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1403 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1404 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1405 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1408 sdmmc_clk: sdmmc-clk {
1410 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1413 sdmmc_cmd: sdmmc-cmd {
1415 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1418 sdmmc_cd: sdmcc-cd {
1420 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1423 sdmmc_wp: sdmmc-wp {
1425 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1430 spdif_bus: spdif-bus {
1432 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1437 spi0_clk: spi0-clk {
1439 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1441 spi0_cs0: spi0-cs0 {
1443 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1445 spi0_cs1: spi0-cs1 {
1447 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1451 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1455 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1460 spi1_clk: spi1-clk {
1462 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1464 spi1_cs0: spi1-cs0 {
1466 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1470 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1474 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1479 spi2_clk: spi2-clk {
1481 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1483 spi2_cs0: spi2-cs0 {
1485 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1489 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1493 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1498 spi3_clk: spi3-clk {
1500 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1502 spi3_cs0: spi3-cs0 {
1504 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1508 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1512 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1517 spi4_clk: spi4-clk {
1519 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1521 spi4_cs0: spi4-cs0 {
1523 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1527 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1531 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1536 spi5_clk: spi5-clk {
1538 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1540 spi5_cs0: spi5-cs0 {
1542 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1546 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1550 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1555 otp_gpio: otp-gpio {
1556 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1560 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1565 uart0_xfer: uart0-xfer {
1567 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1568 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1571 uart0_cts: uart0-cts {
1573 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1576 uart0_rts: uart0-rts {
1578 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1583 uart1_xfer: uart1-xfer {
1585 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1586 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1591 uart2a_xfer: uart2a-xfer {
1593 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1594 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1599 uart2b_xfer: uart2b-xfer {
1601 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1602 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1607 uart2c_xfer: uart2c-xfer {
1609 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1610 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1615 uart3_xfer: uart3-xfer {
1617 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1618 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1621 uart3_cts: uart3-cts {
1623 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1626 uart3_rts: uart3-rts {
1628 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1633 uart4_xfer: uart4-xfer {
1635 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1636 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1641 uarthdcp_xfer: uarthdcp-xfer {
1643 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1644 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1649 pwm0_pin: pwm0-pin {
1651 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1654 vop0_pwm_pin: vop0-pwm-pin {
1656 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1661 pwm1_pin: pwm1-pin {
1663 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1666 vop1_pwm_pin: vop1-pwm-pin {
1668 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1673 pwm2_pin: pwm2-pin {
1675 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1680 pwm3a_pin: pwm3a-pin {
1682 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1687 pwm3b_pin: pwm3b-pin {
1689 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1694 pmic_int_l: pmic-int-l {
1696 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;