2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
52 #include "rk3399-dram-default-timing.dtsi"
55 compatible = "rockchip,rk3399";
57 interrupt-parent = <&gic>;
79 compatible = "arm,psci-1.0";
115 compatible = "arm,cortex-a53", "arm,armv8";
117 enable-method = "psci";
118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <100>;
120 clocks = <&cru ARMCLKL>;
121 cpu-idle-states = <&cpu_sleep>;
122 operating-points-v2 = <&cluster0_opp>;
123 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
128 compatible = "arm,cortex-a53", "arm,armv8";
130 enable-method = "psci";
131 clocks = <&cru ARMCLKL>;
132 cpu-idle-states = <&cpu_sleep>;
133 operating-points-v2 = <&cluster0_opp>;
134 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 cpu-idle-states = <&cpu_sleep>;
144 operating-points-v2 = <&cluster0_opp>;
145 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
150 compatible = "arm,cortex-a53", "arm,armv8";
152 enable-method = "psci";
153 clocks = <&cru ARMCLKL>;
154 cpu-idle-states = <&cpu_sleep>;
155 operating-points-v2 = <&cluster0_opp>;
156 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
161 compatible = "arm,cortex-a72", "arm,armv8";
163 enable-method = "psci";
164 #cooling-cells = <2>; /* min followed by max */
165 dynamic-power-coefficient = <436>;
166 clocks = <&cru ARMCLKB>;
167 cpu-idle-states = <&cpu_sleep>;
168 operating-points-v2 = <&cluster1_opp>;
169 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
174 compatible = "arm,cortex-a72", "arm,armv8";
176 enable-method = "psci";
177 clocks = <&cru ARMCLKB>;
178 cpu-idle-states = <&cpu_sleep>;
179 operating-points-v2 = <&cluster1_opp>;
180 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
184 entry-method = "psci";
185 cpu_sleep: cpu-sleep-0 {
186 compatible = "arm,idle-state";
188 arm,psci-suspend-param = <0x0010000>;
189 entry-latency-us = <350>;
190 exit-latency-us = <600>;
191 min-residency-us = <1150>;
195 /include/ "rk3399-sched-energy.dtsi"
199 cluster0_opp: opp_table0 {
200 compatible = "operating-points-v2";
204 opp-hz = /bits/ 64 <408000000>;
205 opp-microvolt = <800000>;
206 clock-latency-ns = <40000>;
209 opp-hz = /bits/ 64 <600000000>;
210 opp-microvolt = <800000>;
213 opp-hz = /bits/ 64 <816000000>;
214 opp-microvolt = <800000>;
217 opp-hz = /bits/ 64 <1008000000>;
218 opp-microvolt = <875000>;
221 opp-hz = /bits/ 64 <1200000000>;
222 opp-microvolt = <925000>;
225 opp-hz = /bits/ 64 <1416000000>;
226 opp-microvolt = <1025000>;
230 cluster1_opp: opp_table1 {
231 compatible = "operating-points-v2";
235 opp-hz = /bits/ 64 <408000000>;
236 opp-microvolt = <800000>;
237 clock-latency-ns = <40000>;
240 opp-hz = /bits/ 64 <600000000>;
241 opp-microvolt = <800000>;
244 opp-hz = /bits/ 64 <816000000>;
245 opp-microvolt = <800000>;
248 opp-hz = /bits/ 64 <1008000000>;
249 opp-microvolt = <850000>;
252 opp-hz = /bits/ 64 <1200000000>;
253 opp-microvolt = <925000>;
258 compatible = "arm,armv8-timer";
259 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
260 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
261 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
262 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
266 compatible = "arm,cortex-a53-pmu";
267 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
271 compatible = "arm,cortex-a72-pmu";
272 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
276 compatible = "fixed-clock";
278 clock-frequency = <24000000>;
279 clock-output-names = "xin24m";
283 compatible = "arm,amba-bus";
284 #address-cells = <2>;
288 dmac_bus: dma-controller@ff6d0000 {
289 compatible = "arm,pl330", "arm,primecell";
290 reg = <0x0 0xff6d0000 0x0 0x4000>;
291 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
292 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
294 clocks = <&cru ACLK_DMAC0_PERILP>;
295 clock-names = "apb_pclk";
296 peripherals-req-type-burst;
299 dmac_peri: dma-controller@ff6e0000 {
300 compatible = "arm,pl330", "arm,primecell";
301 reg = <0x0 0xff6e0000 0x0 0x4000>;
302 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
303 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
305 clocks = <&cru ACLK_DMAC1_PERILP>;
306 clock-names = "apb_pclk";
307 peripherals-req-type-burst;
312 compatible = "rockchip,rk3399-gmac";
313 reg = <0x0 0xfe300000 0x0 0x10000>;
314 rockchip,grf = <&grf>;
315 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
316 interrupt-names = "macirq";
317 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
318 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
319 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
321 clock-names = "stmmaceth", "mac_clk_rx",
322 "mac_clk_tx", "clk_mac_ref",
323 "clk_mac_refout", "aclk_mac",
325 resets = <&cru SRST_A_GMAC>;
326 reset-names = "stmmaceth";
327 power-domains = <&power RK3399_PD_GMAC>;
332 compatible = "rockchip,rk3399-emmc-phy";
333 reg-offset = <0xf780>;
335 rockchip,grf = <&grf>;
336 ctrl-base = <0xfe330000>;
340 sdio0: dwmmc@fe310000 {
341 compatible = "rockchip,rk3399-dw-mshc",
342 "rockchip,rk3288-dw-mshc";
343 reg = <0x0 0xfe310000 0x0 0x4000>;
344 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
345 clock-freq-min-max = <400000 150000000>;
346 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
347 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
348 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
349 fifo-depth = <0x100>;
350 power-domains = <&power RK3399_PD_SDIOAUDIO>;
354 sdmmc: dwmmc@fe320000 {
355 compatible = "rockchip,rk3399-dw-mshc",
356 "rockchip,rk3288-dw-mshc";
357 reg = <0x0 0xfe320000 0x0 0x4000>;
358 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
359 clock-freq-min-max = <400000 150000000>;
360 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
361 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
362 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
363 fifo-depth = <0x100>;
364 power-domains = <&power RK3399_PD_SD>;
368 sdhci: sdhci@fe330000 {
369 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
370 reg = <0x0 0xfe330000 0x0 0x10000>;
371 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
372 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
373 clock-names = "clk_xin", "clk_ahb";
374 assigned-clocks = <&cru SCLK_EMMC>;
375 assigned-clock-parents = <&cru PLL_CPLL>;
376 assigned-clock-rates = <200000000>;
378 phy-names = "phy_arasan";
379 power-domains = <&power RK3399_PD_EMMC>;
383 usb_host0_ehci: usb@fe380000 {
384 compatible = "generic-ehci";
385 reg = <0x0 0xfe380000 0x0 0x20000>;
386 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
387 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
388 <&cru SCLK_USBPHY0_480M_SRC>;
389 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
390 phys = <&u2phy0_host>;
392 power-domains = <&power RK3399_PD_PERIHP>;
396 usb_host0_ohci: usb@fe3a0000 {
397 compatible = "generic-ohci";
398 reg = <0x0 0xfe3a0000 0x0 0x20000>;
399 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
400 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
401 <&cru SCLK_USBPHY0_480M_SRC>;
402 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
403 phys = <&u2phy0_host>;
405 power-domains = <&power RK3399_PD_PERIHP>;
409 usb_host1_ehci: usb@fe3c0000 {
410 compatible = "generic-ehci";
411 reg = <0x0 0xfe3c0000 0x0 0x20000>;
412 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
413 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
414 <&cru SCLK_USBPHY1_480M_SRC>;
415 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
416 phys = <&u2phy1_host>;
418 power-domains = <&power RK3399_PD_PERIHP>;
422 usb_host1_ohci: usb@fe3e0000 {
423 compatible = "generic-ohci";
424 reg = <0x0 0xfe3e0000 0x0 0x20000>;
425 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
426 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
427 <&cru SCLK_USBPHY1_480M_SRC>;
428 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
429 phys = <&u2phy1_host>;
431 power-domains = <&power RK3399_PD_PERIHP>;
435 usbdrd3_0: usb@fe800000 {
436 compatible = "rockchip,rk3399-dwc3";
437 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
438 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
439 clock-names = "ref_clk", "suspend_clk",
440 "bus_clk", "grf_clk";
441 power-domains = <&power RK3399_PD_USB3>;
442 resets = <&cru SRST_A_USB3_OTG0>;
443 reset-names = "usb3-otg";
444 #address-cells = <2>;
448 usbdrd_dwc3_0: dwc3@fe800000 {
449 compatible = "snps,dwc3";
450 reg = <0x0 0xfe800000 0x0 0x100000>;
451 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
453 phys = <&u2phy0_otg>, <&tcphy0 1>;
454 phy-names = "usb2-phy", "usb3-phy";
455 phy_type = "utmi_wide";
456 snps,dis_enblslpm_quirk;
457 snps,dis-u2-freeclk-exists-quirk;
458 snps,dis-del-phy-power-chg-quirk;
459 snps,xhci-slow-suspend-quirk;
464 usbdrd3_1: usb@fe900000 {
465 compatible = "rockchip,rk3399-dwc3";
466 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
467 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
468 clock-names = "ref_clk", "suspend_clk",
469 "bus_clk", "grf_clk";
470 power-domains = <&power RK3399_PD_USB3>;
471 resets = <&cru SRST_A_USB3_OTG1>;
472 reset-names = "usb3-otg";
473 #address-cells = <2>;
477 usbdrd_dwc3_1: dwc3@fe900000 {
478 compatible = "snps,dwc3";
479 reg = <0x0 0xfe900000 0x0 0x100000>;
480 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
482 phys = <&u2phy1_otg>, <&tcphy1 1>;
483 phy-names = "usb2-phy", "usb3-phy";
484 phy_type = "utmi_wide";
485 snps,dis_enblslpm_quirk;
486 snps,dis-u2-freeclk-exists-quirk;
487 snps,dis-del-phy-power-chg-quirk;
488 snps,xhci-slow-suspend-quirk;
493 gic: interrupt-controller@fee00000 {
494 compatible = "arm,gic-v3";
495 #interrupt-cells = <4>;
496 #address-cells = <2>;
499 interrupt-controller;
501 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
502 <0x0 0xfef00000 0 0xc0000>, /* GICR */
503 <0x0 0xfff00000 0 0x10000>, /* GICC */
504 <0x0 0xfff10000 0 0x10000>, /* GICH */
505 <0x0 0xfff20000 0 0x10000>; /* GICV */
506 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
507 its: interrupt-controller@fee20000 {
508 compatible = "arm,gic-v3-its";
510 reg = <0x0 0xfee20000 0x0 0x20000>;
514 part0: interrupt-partition-0 {
515 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
518 part1: interrupt-partition-1 {
519 affinity = <&cpu_b0 &cpu_b1>;
524 saradc: saradc@ff100000 {
525 compatible = "rockchip,rk3399-saradc";
526 reg = <0x0 0xff100000 0x0 0x100>;
527 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
528 #io-channel-cells = <1>;
529 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
530 clock-names = "saradc", "apb_pclk";
535 compatible = "rockchip,rk3399-i2c";
536 reg = <0x0 0xff3c0000 0x0 0x1000>;
537 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
538 clock-names = "i2c", "pclk";
539 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c0_xfer>;
542 #address-cells = <1>;
548 compatible = "rockchip,rk3399-i2c";
549 reg = <0x0 0xff110000 0x0 0x1000>;
550 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
551 clock-names = "i2c", "pclk";
552 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c1_xfer>;
555 #address-cells = <1>;
561 compatible = "rockchip,rk3399-i2c";
562 reg = <0x0 0xff120000 0x0 0x1000>;
563 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
564 clock-names = "i2c", "pclk";
565 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c2_xfer>;
568 #address-cells = <1>;
574 compatible = "rockchip,rk3399-i2c";
575 reg = <0x0 0xff130000 0x0 0x1000>;
576 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
577 clock-names = "i2c", "pclk";
578 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c3_xfer>;
581 #address-cells = <1>;
587 compatible = "rockchip,rk3399-i2c";
588 reg = <0x0 0xff140000 0x0 0x1000>;
589 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
590 clock-names = "i2c", "pclk";
591 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c5_xfer>;
594 #address-cells = <1>;
600 compatible = "rockchip,rk3399-i2c";
601 reg = <0x0 0xff150000 0x0 0x1000>;
602 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
603 clock-names = "i2c", "pclk";
604 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&i2c6_xfer>;
607 #address-cells = <1>;
613 compatible = "rockchip,rk3399-i2c";
614 reg = <0x0 0xff160000 0x0 0x1000>;
615 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
616 clock-names = "i2c", "pclk";
617 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&i2c7_xfer>;
620 #address-cells = <1>;
625 uart0: serial@ff180000 {
626 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
627 reg = <0x0 0xff180000 0x0 0x100>;
628 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
629 clock-names = "baudclk", "apb_pclk";
630 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
633 pinctrl-names = "default";
634 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
638 uart1: serial@ff190000 {
639 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
640 reg = <0x0 0xff190000 0x0 0x100>;
641 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
642 clock-names = "baudclk", "apb_pclk";
643 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&uart1_xfer>;
651 uart2: serial@ff1a0000 {
652 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
653 reg = <0x0 0xff1a0000 0x0 0x100>;
654 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
655 clock-names = "baudclk", "apb_pclk";
656 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&uart2c_xfer>;
664 uart3: serial@ff1b0000 {
665 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
666 reg = <0x0 0xff1b0000 0x0 0x100>;
667 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
668 clock-names = "baudclk", "apb_pclk";
669 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
678 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
679 reg = <0x0 0xff1c0000 0x0 0x1000>;
680 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
681 clock-names = "spiclk", "apb_pclk";
682 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
685 #address-cells = <1>;
691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
692 reg = <0x0 0xff1d0000 0x0 0x1000>;
693 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
694 clock-names = "spiclk", "apb_pclk";
695 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
696 pinctrl-names = "default";
697 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
698 #address-cells = <1>;
704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
705 reg = <0x0 0xff1e0000 0x0 0x1000>;
706 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
707 clock-names = "spiclk", "apb_pclk";
708 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
711 #address-cells = <1>;
717 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
718 reg = <0x0 0xff1f0000 0x0 0x1000>;
719 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
720 clock-names = "spiclk", "apb_pclk";
721 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
724 #address-cells = <1>;
730 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
731 reg = <0x0 0xff200000 0x0 0x1000>;
732 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
733 clock-names = "spiclk", "apb_pclk";
734 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
737 #address-cells = <1>;
743 soc_thermal: soc-thermal {
744 polling-delay-passive = <20>; /* milliseconds */
745 polling-delay = <1000>; /* milliseconds */
746 sustainable-power = <1000>; /* milliwatts */
748 thermal-sensors = <&tsadc 0>;
751 threshold: trip-point@0 {
752 temperature = <70000>; /* millicelsius */
753 hysteresis = <2000>; /* millicelsius */
756 target: trip-point@1 {
757 temperature = <85000>; /* millicelsius */
758 hysteresis = <2000>; /* millicelsius */
762 temperature = <95000>; /* millicelsius */
763 hysteresis = <2000>; /* millicelsius */
772 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
773 contribution = <4096>;
778 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
779 contribution = <1024>;
784 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
785 contribution = <4096>;
790 gpu_thermal: gpu-thermal {
791 polling-delay-passive = <100>; /* milliseconds */
792 polling-delay = <1000>; /* milliseconds */
794 thermal-sensors = <&tsadc 1>;
798 tsadc: tsadc@ff260000 {
799 compatible = "rockchip,rk3399-tsadc";
800 reg = <0x0 0xff260000 0x0 0x100>;
801 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
802 rockchip,grf = <&grf>;
803 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
804 clock-names = "tsadc", "apb_pclk";
805 assigned-clocks = <&cru SCLK_TSADC>;
806 assigned-clock-rates = <750000>;
807 resets = <&cru SRST_TSADC>;
808 reset-names = "tsadc-apb";
809 pinctrl-names = "init", "default", "sleep";
810 pinctrl-0 = <&otp_gpio>;
811 pinctrl-1 = <&otp_out>;
812 pinctrl-2 = <&otp_gpio>;
813 #thermal-sensor-cells = <1>;
814 rockchip,hw-tshut-temp = <95000>;
818 qos_emmc: qos@ffa58000 {
819 compatible = "syscon";
820 reg = <0x0 0xffa58000 0x0 0x20>;
823 qos_gmac: qos@ffa5c000 {
824 compatible = "syscon";
825 reg = <0x0 0xffa5c000 0x0 0x20>;
828 qos_pcie: qos@ffa60080 {
829 compatible = "syscon";
830 reg = <0x0 0xffa60080 0x0 0x20>;
833 qos_usb_host0: qos@ffa60100 {
834 compatible = "syscon";
835 reg = <0x0 0xffa60100 0x0 0x20>;
838 qos_usb_host1: qos@ffa60180 {
839 compatible = "syscon";
840 reg = <0x0 0xffa60180 0x0 0x20>;
843 qos_usb_otg0: qos@ffa70000 {
844 compatible = "syscon";
845 reg = <0x0 0xffa70000 0x0 0x20>;
848 qos_usb_otg1: qos@ffa70080 {
849 compatible = "syscon";
850 reg = <0x0 0xffa70080 0x0 0x20>;
853 qos_sd: qos@ffa74000 {
854 compatible = "syscon";
855 reg = <0x0 0xffa74000 0x0 0x20>;
858 qos_sdioaudio: qos@ffa76000 {
859 compatible = "syscon";
860 reg = <0x0 0xffa76000 0x0 0x20>;
863 qos_hdcp: qos@ffa90000 {
864 compatible = "syscon";
865 reg = <0x0 0xffa90000 0x0 0x20>;
868 qos_iep: qos@ffa98000 {
869 compatible = "syscon";
870 reg = <0x0 0xffa98000 0x0 0x20>;
873 qos_isp0_m0: qos@ffaa0000 {
874 compatible = "syscon";
875 reg = <0x0 0xffaa0000 0x0 0x20>;
878 qos_isp0_m1: qos@ffaa0080 {
879 compatible = "syscon";
880 reg = <0x0 0xffaa0080 0x0 0x20>;
883 qos_isp1_m0: qos@ffaa8000 {
884 compatible = "syscon";
885 reg = <0x0 0xffaa8000 0x0 0x20>;
888 qos_isp1_m1: qos@ffaa8080 {
889 compatible = "syscon";
890 reg = <0x0 0xffaa8080 0x0 0x20>;
893 qos_rga_r: qos@ffab0000 {
894 compatible = "syscon";
895 reg = <0x0 0xffab0000 0x0 0x20>;
898 qos_rga_w: qos@ffab0080 {
899 compatible = "syscon";
900 reg = <0x0 0xffab0080 0x0 0x20>;
903 qos_video_m0: qos@ffab8000 {
904 compatible = "syscon";
905 reg = <0x0 0xffab8000 0x0 0x20>;
908 qos_video_m1_r: qos@ffac0000 {
909 compatible = "syscon";
910 reg = <0x0 0xffac0000 0x0 0x20>;
913 qos_video_m1_w: qos@ffac0080 {
914 compatible = "syscon";
915 reg = <0x0 0xffac0080 0x0 0x20>;
918 qos_vop_big_r: qos@ffac8000 {
919 compatible = "syscon";
920 reg = <0x0 0xffac8000 0x0 0x20>;
923 qos_vop_big_w: qos@ffac8080 {
924 compatible = "syscon";
925 reg = <0x0 0xffac8080 0x0 0x20>;
928 qos_vop_little: qos@ffad0000 {
929 compatible = "syscon";
930 reg = <0x0 0xffad0000 0x0 0x20>;
933 qos_perihp: qos@ffad8080 {
934 compatible = "syscon";
935 reg = <0x0 0xffad8080 0x0 0x20>;
938 qos_gpu: qos@ffae0000 {
939 compatible = "syscon";
940 reg = <0x0 0xffae0000 0x0 0x20>;
943 pmu: power-management@ff310000 {
944 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
945 reg = <0x0 0xff310000 0x0 0x1000>;
948 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
949 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
950 * Some of the power domains are grouped together for every
952 * The detail contents as below.
954 power: power-controller {
955 compatible = "rockchip,rk3399-power-controller";
956 #power-domain-cells = <1>;
957 #address-cells = <1>;
960 /* These power domains are grouped by VD_CENTER */
961 pd_iep@RK3399_PD_IEP {
962 reg = <RK3399_PD_IEP>;
963 clocks = <&cru ACLK_IEP>,
967 pd_rga@RK3399_PD_RGA {
968 reg = <RK3399_PD_RGA>;
969 clocks = <&cru ACLK_RGA>,
971 pm_qos = <&qos_rga_r>,
974 pd_vcodec@RK3399_PD_VCODEC {
975 reg = <RK3399_PD_VCODEC>;
976 clocks = <&cru ACLK_VCODEC>,
978 pm_qos = <&qos_video_m0>;
980 pd_vdu@RK3399_PD_VDU {
981 reg = <RK3399_PD_VDU>;
982 clocks = <&cru ACLK_VDU>,
984 pm_qos = <&qos_video_m1_r>,
988 /* These power domains are grouped by VD_GPU */
989 pd_gpu@RK3399_PD_GPU {
990 reg = <RK3399_PD_GPU>;
991 clocks = <&cru ACLK_GPU>;
995 /* These power domains are grouped by VD_LOGIC */
996 pd_emmc@RK3399_PD_EMMC {
997 reg = <RK3399_PD_EMMC>;
998 clocks = <&cru ACLK_EMMC>;
999 pm_qos = <&qos_emmc>;
1001 pd_gmac@RK3399_PD_GMAC {
1002 reg = <RK3399_PD_GMAC>;
1003 clocks = <&cru ACLK_GMAC>;
1004 pm_qos = <&qos_gmac>;
1006 pd_perihp@RK3399_PD_PERIHP {
1007 reg = <RK3399_PD_PERIHP>;
1008 #address-cells = <1>;
1010 clocks = <&cru ACLK_PERIHP>;
1011 pm_qos = <&qos_perihp>,
1016 pd_sd@RK3399_PD_SD {
1017 reg = <RK3399_PD_SD>;
1018 clocks = <&cru HCLK_SDMMC>,
1023 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1024 reg = <RK3399_PD_SDIOAUDIO>;
1025 clocks = <&cru HCLK_SDIO>;
1026 pm_qos = <&qos_sdioaudio>;
1028 pd_usb3@RK3399_PD_USB3 {
1029 reg = <RK3399_PD_USB3>;
1030 clocks = <&cru ACLK_USB3>;
1031 pm_qos = <&qos_usb_otg0>,
1034 pd_vio@RK3399_PD_VIO {
1035 reg = <RK3399_PD_VIO>;
1036 #address-cells = <1>;
1039 pd_hdcp@RK3399_PD_HDCP {
1040 reg = <RK3399_PD_HDCP>;
1041 clocks = <&cru ACLK_HDCP>,
1044 pm_qos = <&qos_hdcp>;
1046 pd_isp0@RK3399_PD_ISP0 {
1047 reg = <RK3399_PD_ISP0>;
1048 clocks = <&cru ACLK_ISP0>,
1050 pm_qos = <&qos_isp0_m0>,
1053 pd_isp1@RK3399_PD_ISP1 {
1054 reg = <RK3399_PD_ISP1>;
1055 clocks = <&cru ACLK_ISP1>,
1057 pm_qos = <&qos_isp1_m0>,
1060 pd_vo@RK3399_PD_VO {
1061 reg = <RK3399_PD_VO>;
1062 #address-cells = <1>;
1065 pd_vopb@RK3399_PD_VOPB {
1066 reg = <RK3399_PD_VOPB>;
1067 clocks = <&cru ACLK_VOP0>,
1069 pm_qos = <&qos_vop_big_r>,
1072 pd_vopl@RK3399_PD_VOPL {
1073 reg = <RK3399_PD_VOPL>;
1074 clocks = <&cru ACLK_VOP1>,
1076 pm_qos = <&qos_vop_little>;
1083 pmugrf: syscon@ff320000 {
1084 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1085 reg = <0x0 0xff320000 0x0 0x1000>;
1088 compatible = "syscon-reboot-mode";
1090 mode-bootloader = <BOOT_LOADER>;
1091 mode-charge = <BOOT_CHARGING>;
1092 mode-fastboot = <BOOT_FASTBOOT>;
1093 mode-loader = <BOOT_LOADER>;
1094 mode-normal = <BOOT_NORMAL>;
1095 mode-recovery = <BOOT_RECOVERY>;
1099 spi3: spi@ff350000 {
1100 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1101 reg = <0x0 0xff350000 0x0 0x1000>;
1102 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1103 clock-names = "spiclk", "apb_pclk";
1104 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1105 pinctrl-names = "default";
1106 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1107 #address-cells = <1>;
1109 status = "disabled";
1112 uart4: serial@ff370000 {
1113 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1114 reg = <0x0 0xff370000 0x0 0x100>;
1115 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1116 clock-names = "baudclk", "apb_pclk";
1117 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&uart4_xfer>;
1122 status = "disabled";
1125 i2c4: i2c@ff3d0000 {
1126 compatible = "rockchip,rk3399-i2c";
1127 reg = <0x0 0xff3d0000 0x0 0x1000>;
1128 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1129 clock-names = "i2c", "pclk";
1130 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1131 pinctrl-names = "default";
1132 pinctrl-0 = <&i2c4_xfer>;
1133 #address-cells = <1>;
1135 status = "disabled";
1138 i2c8: i2c@ff3e0000 {
1139 compatible = "rockchip,rk3399-i2c";
1140 reg = <0x0 0xff3e0000 0x0 0x1000>;
1141 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1142 clock-names = "i2c", "pclk";
1143 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1144 pinctrl-names = "default";
1145 pinctrl-0 = <&i2c8_xfer>;
1146 #address-cells = <1>;
1148 status = "disabled";
1151 pcie_phy: phy@e220 {
1152 compatible = "rockchip,rk3399-pcie-phy";
1154 rockchip,grf = <&grf>;
1155 clocks = <&cru SCLK_PCIEPHY_REF>;
1156 clock-names = "refclk";
1157 resets = <&cru SRST_PCIEPHY>;
1158 reset-names = "phy";
1159 status = "disabled";
1162 pcie0: pcie@f8000000 {
1163 compatible = "rockchip,rk3399-pcie";
1164 #address-cells = <3>;
1166 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1167 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1168 clock-names = "aclk", "aclk-perf",
1170 bus-range = <0x0 0x1>;
1171 msi-map = <0x0 &its 0x0 0x1000>;
1172 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1173 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1174 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1175 interrupt-names = "sys", "legacy", "client";
1176 #interrupt-cells = <1>;
1177 interrupt-map-mask = <0 0 0 7>;
1178 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1179 <0 0 0 2 &pcie0_intc 1>,
1180 <0 0 0 3 &pcie0_intc 2>,
1181 <0 0 0 4 &pcie0_intc 3>;
1183 phy-names = "pcie-phy";
1184 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1185 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1186 reg = <0x0 0xf8000000 0x0 0x2000000>,
1187 <0x0 0xfd000000 0x0 0x1000000>;
1188 reg-names = "axi-base", "apb-base";
1189 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1190 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1191 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1192 status = "disabled";
1193 pcie0_intc: interrupt-controller {
1194 interrupt-controller;
1195 #address-cells = <0>;
1196 #interrupt-cells = <1>;
1200 pwm0: pwm@ff420000 {
1201 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1202 reg = <0x0 0xff420000 0x0 0x10>;
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&pwm0_pin>;
1206 clocks = <&pmucru PCLK_RKPWM_PMU>;
1207 clock-names = "pwm";
1208 status = "disabled";
1211 pwm1: pwm@ff420010 {
1212 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1213 reg = <0x0 0xff420010 0x0 0x10>;
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&pwm1_pin>;
1217 clocks = <&pmucru PCLK_RKPWM_PMU>;
1218 clock-names = "pwm";
1219 status = "disabled";
1222 pwm2: pwm@ff420020 {
1223 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1224 reg = <0x0 0xff420020 0x0 0x10>;
1226 pinctrl-names = "default";
1227 pinctrl-0 = <&pwm2_pin>;
1228 clocks = <&pmucru PCLK_RKPWM_PMU>;
1229 clock-names = "pwm";
1230 status = "disabled";
1233 pwm3: pwm@ff420030 {
1234 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1235 reg = <0x0 0xff420030 0x0 0x10>;
1237 pinctrl-names = "default";
1238 pinctrl-0 = <&pwm3a_pin>;
1239 clocks = <&pmucru PCLK_RKPWM_PMU>;
1240 clock-names = "pwm";
1241 status = "disabled";
1245 reg = <0x00 0xff630000 0x00 0x4000>;
1246 compatible = "rockchip,rk3399-dfi";
1247 rockchip,pmu = <&pmugrf>;
1248 clocks = <&cru PCLK_DDR_MON>;
1249 clock-names = "pclk_ddr_mon";
1250 status = "disabled";
1254 compatible = "rockchip,rk3399-dmc";
1255 devfreq-events = <&dfi>;
1256 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1257 clocks = <&cru SCLK_DDRCLK>;
1258 clock-names = "dmc_clk";
1259 ddr_timing = <&ddr_timing>;
1260 operating-points-v2 = <&dmc_opp_table>;
1261 status = "disabled";
1264 dmc_opp_table: dmc_opp_table {
1265 compatible = "operating-points-v2";
1268 opp-hz = /bits/ 64 <666000000>;
1269 opp-microvolt = <900000>;
1274 compatible = "rockchip,rk3399-rga";
1275 reg = <0x0 0xff680000 0x0 0x10000>;
1276 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1277 interrupt-names = "rga";
1278 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1279 clock-names = "aclk", "hclk", "sclk";
1280 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1281 reset-names = "core", "axi", "ahb";
1282 power-domains = <&power RK3399_PD_RGA>;
1283 status = "disabled";
1286 efuse0: efuse@ff690000 {
1287 compatible = "rockchip,rk3399-efuse";
1288 reg = <0x0 0xff690000 0x0 0x80>;
1289 #address-cells = <1>;
1291 clocks = <&cru PCLK_EFUSE1024NS>;
1292 clock-names = "pclk_efuse";
1295 cpul_leakage: cpul-leakage {
1298 cpub_leakage: cpub-leakage {
1301 gpu_leakage: gpu-leakage {
1304 center_leakage: center-leakage {
1307 logic_leakage: logic-leakage {
1310 wafer_info: wafer-info {
1315 pmucru: pmu-clock-controller@ff750000 {
1316 compatible = "rockchip,rk3399-pmucru";
1317 reg = <0x0 0xff750000 0x0 0x1000>;
1320 assigned-clocks = <&pmucru PLL_PPLL>;
1321 assigned-clock-rates = <676000000>;
1324 cru: clock-controller@ff760000 {
1325 compatible = "rockchip,rk3399-cru";
1326 reg = <0x0 0xff760000 0x0 0x1000>;
1330 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1331 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1332 <&cru ARMCLKL>, <&cru ARMCLKB>,
1333 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1335 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1337 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1338 <&cru PCLK_PERILP0>,
1339 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1340 assigned-clock-rates =
1341 <400000000>, <200000000>,
1342 <400000000>, <200000000>,
1343 <816000000>, <816000000>,
1344 <594000000>, <800000000>,
1346 <150000000>, <75000000>,
1348 <100000000>, <100000000>,
1350 <100000000>, <50000000>;
1353 grf: syscon@ff770000 {
1354 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1355 reg = <0x0 0xff770000 0x0 0x10000>;
1356 #address-cells = <1>;
1359 u2phy0: usb2-phy@e450 {
1360 compatible = "rockchip,rk3399-usb2phy";
1361 reg = <0xe450 0x10>;
1362 clocks = <&cru SCLK_USB2PHY0_REF>;
1363 clock-names = "phyclk";
1365 clock-output-names = "clk_usbphy0_480m";
1366 status = "disabled";
1368 u2phy0_otg: otg-port {
1370 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1371 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1372 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1373 interrupt-names = "otg-bvalid", "otg-id",
1375 status = "disabled";
1378 u2phy0_host: host-port {
1380 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1381 interrupt-names = "linestate";
1382 status = "disabled";
1386 u2phy1: usb2-phy@e460 {
1387 compatible = "rockchip,rk3399-usb2phy";
1388 reg = <0xe460 0x10>;
1389 clocks = <&cru SCLK_USB2PHY1_REF>;
1390 clock-names = "phyclk";
1392 clock-output-names = "clk_usbphy1_480m";
1393 status = "disabled";
1395 u2phy1_otg: otg-port {
1397 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1400 interrupt-names = "otg-bvalid", "otg-id",
1402 status = "disabled";
1405 u2phy1_host: host-port {
1407 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1408 interrupt-names = "linestate";
1409 status = "disabled";
1414 tcphy0: phy@ff7c0000 {
1415 compatible = "rockchip,rk3399-typec-phy";
1416 reg = <0x0 0xff7c0000 0x0 0x40000>;
1417 rockchip,grf = <&grf>;
1419 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1420 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1421 clock-names = "tcpdcore", "tcpdphy-ref";
1422 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1423 assigned-clock-rates = <50000000>;
1424 resets = <&cru SRST_UPHY0>,
1425 <&cru SRST_UPHY0_PIPE_L00>,
1426 <&cru SRST_P_UPHY0_TCPHY>;
1427 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1428 rockchip,typec-conn-dir = <0xe580 0 16>;
1429 rockchip,usb3tousb2-en = <0xe580 3 19>;
1430 rockchip,external-psm = <0xe588 14 30>;
1431 rockchip,pipe-status = <0xe5c0 0 0>;
1432 rockchip,uphy-dp-sel = <0x6268 19 19>;
1433 status = "disabled";
1436 tcphy1: phy@ff800000 {
1437 compatible = "rockchip,rk3399-typec-phy";
1438 reg = <0x0 0xff800000 0x0 0x40000>;
1439 rockchip,grf = <&grf>;
1441 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1442 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1443 clock-names = "tcpdcore", "tcpdphy-ref";
1444 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1445 assigned-clock-rates = <50000000>;
1446 resets = <&cru SRST_UPHY1>,
1447 <&cru SRST_UPHY1_PIPE_L00>,
1448 <&cru SRST_P_UPHY1_TCPHY>;
1449 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1450 rockchip,typec-conn-dir = <0xe58c 0 16>;
1451 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1452 rockchip,external-psm = <0xe594 14 30>;
1453 rockchip,pipe-status = <0xe5c0 16 16>;
1454 rockchip,uphy-dp-sel = <0x6268 3 19>;
1455 status = "disabled";
1459 compatible = "snps,dw-wdt";
1460 reg = <0x0 0xff848000 0x0 0x100>;
1461 clocks = <&cru PCLK_WDT>;
1462 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1465 rktimer: rktimer@ff850000 {
1466 compatible = "rockchip,rk3399-timer";
1467 reg = <0x0 0xff850000 0x0 0x1000>;
1468 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1469 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1470 clock-names = "pclk", "timer";
1473 spdif: spdif@ff870000 {
1474 compatible = "rockchip,rk3399-spdif";
1475 reg = <0x0 0xff870000 0x0 0x1000>;
1476 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1477 dmas = <&dmac_bus 7>;
1479 clock-names = "mclk", "hclk";
1480 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1481 pinctrl-names = "default";
1482 pinctrl-0 = <&spdif_bus>;
1483 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1484 status = "disabled";
1487 i2s0: i2s@ff880000 {
1488 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1489 reg = <0x0 0xff880000 0x0 0x1000>;
1490 rockchip,grf = <&grf>;
1491 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1492 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1493 dma-names = "tx", "rx";
1494 clock-names = "i2s_clk", "i2s_hclk";
1495 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1496 pinctrl-names = "default";
1497 pinctrl-0 = <&i2s0_8ch_bus>;
1498 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1499 status = "disabled";
1502 i2s1: i2s@ff890000 {
1503 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1504 reg = <0x0 0xff890000 0x0 0x1000>;
1505 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1506 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1507 dma-names = "tx", "rx";
1508 clock-names = "i2s_clk", "i2s_hclk";
1509 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1510 pinctrl-names = "default";
1511 pinctrl-0 = <&i2s1_2ch_bus>;
1512 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1513 status = "disabled";
1516 i2s2: i2s@ff8a0000 {
1517 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1518 reg = <0x0 0xff8a0000 0x0 0x1000>;
1519 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1520 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1521 dma-names = "tx", "rx";
1522 clock-names = "i2s_clk", "i2s_hclk";
1523 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1524 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1525 status = "disabled";
1529 compatible = "arm,malit860",
1534 reg = <0x0 0xff9a0000 0x0 0x10000>;
1536 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1537 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1538 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1539 interrupt-names = "GPU", "JOB", "MMU";
1541 clocks = <&cru ACLK_GPU>;
1542 clock-names = "clk_mali";
1543 #cooling-cells = <2>; /* min followed by max */
1544 operating-points-v2 = <&gpu_opp_table>;
1545 power-domains = <&power RK3399_PD_GPU>;
1546 power-off-delay-ms = <200>;
1547 status = "disabled";
1549 gpu_power_model: power_model {
1550 compatible = "arm,mali-simple-power-model";
1553 static-power = <300>;
1554 dynamic-power = <396>;
1555 ts = <32000 4700 (-80) 2>;
1556 thermal-zone = "gpu-thermal";
1560 gpu_opp_table: gpu_opp_table {
1561 compatible = "operating-points-v2";
1565 opp-hz = /bits/ 64 <200000000>;
1566 opp-microvolt = <900000>;
1569 opp-hz = /bits/ 64 <300000000>;
1570 opp-microvolt = <900000>;
1573 opp-hz = /bits/ 64 <400000000>;
1574 opp-microvolt = <900000>;
1579 vopl: vop@ff8f0000 {
1580 compatible = "rockchip,rk3399-vop-lit";
1581 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1582 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1583 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1584 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1585 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1586 reset-names = "axi", "ahb", "dclk";
1587 power-domains = <&power RK3399_PD_VOPL>;
1588 iommus = <&vopl_mmu>;
1589 status = "disabled";
1592 #address-cells = <1>;
1595 vopl_out_mipi: endpoint@0 {
1597 remote-endpoint = <&mipi_in_vopl>;
1600 vopl_out_edp: endpoint@1 {
1602 remote-endpoint = <&edp_in_vopl>;
1605 vopl_out_hdmi: endpoint@2 {
1607 remote-endpoint = <&hdmi_in_vopl>;
1612 vop1_pwm: voppwm@ff8f01a0 {
1613 compatible = "rockchip,vop-pwm";
1614 reg = <0x0 0xff8f01a0 0x0 0x10>;
1616 pinctrl-names = "default";
1617 pinctrl-0 = <&vop1_pwm_pin>;
1618 clocks = <&cru SCLK_VOP1_PWM>;
1619 clock-names = "pwm";
1620 status = "disabled";
1623 vopl_mmu: iommu@ff8f3f00 {
1624 compatible = "rockchip,iommu";
1625 reg = <0x0 0xff8f3f00 0x0 0x100>;
1626 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1627 interrupt-names = "vopl_mmu";
1629 status = "disabled";
1632 vopb: vop@ff900000 {
1633 compatible = "rockchip,rk3399-vop-big";
1634 reg = <0x0 0xff900000 0x0 0x3efc>;
1635 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1636 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1637 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1638 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1639 reset-names = "axi", "ahb", "dclk";
1640 power-domains = <&power RK3399_PD_VOPB>;
1641 iommus = <&vopb_mmu>;
1642 status = "disabled";
1645 #address-cells = <1>;
1648 vopb_out_edp: endpoint@0 {
1650 remote-endpoint = <&edp_in_vopb>;
1653 vopb_out_mipi: endpoint@1 {
1655 remote-endpoint = <&mipi_in_vopb>;
1658 vopb_out_hdmi: endpoint@2 {
1660 remote-endpoint = <&hdmi_in_vopb>;
1665 vop0_pwm: voppwm@ff9001a0 {
1666 compatible = "rockchip,vop-pwm";
1667 reg = <0x0 0xff9001a0 0x0 0x10>;
1669 pinctrl-names = "default";
1670 pinctrl-0 = <&vop0_pwm_pin>;
1671 clocks = <&cru SCLK_VOP0_PWM>;
1672 clock-names = "pwm";
1673 status = "disabled";
1676 vopb_mmu: iommu@ff903f00 {
1677 compatible = "rockchip,iommu";
1678 reg = <0x0 0xff903f00 0x0 0x100>;
1679 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1680 interrupt-names = "vopb_mmu";
1682 status = "disabled";
1685 hdmi: hdmi@ff940000 {
1686 compatible = "rockchip,rk3399-dw-hdmi";
1687 reg = <0x0 0xff940000 0x0 0x20000>;
1689 rockchip,grf = <&grf>;
1690 power-domains = <&power RK3399_PD_HDCP>;
1691 pinctrl-names = "default";
1692 pinctrl-0 = <&hdmi_i2c_xfer>;
1693 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1694 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1695 clock-names = "iahb", "isfr", "vpll", "grf";
1696 status = "disabled";
1700 #address-cells = <1>;
1702 hdmi_in_vopb: endpoint@0 {
1704 remote-endpoint = <&vopb_out_hdmi>;
1706 hdmi_in_vopl: endpoint@1 {
1708 remote-endpoint = <&vopl_out_hdmi>;
1714 mipi_dsi: mipi@ff960000 {
1715 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1716 reg = <0x0 0xff960000 0x0 0x8000>;
1717 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1718 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1719 <&cru SCLK_DPHY_TX0_CFG>;
1720 clock-names = "ref", "pclk", "phy_cfg";
1721 power-domains = <&power RK3399_PD_VIO>;
1722 rockchip,grf = <&grf>;
1723 #address-cells = <1>;
1725 status = "disabled";
1728 #address-cells = <1>;
1733 #address-cells = <1>;
1736 mipi_in_vopb: endpoint@0 {
1738 remote-endpoint = <&vopb_out_mipi>;
1740 mipi_in_vopl: endpoint@1 {
1742 remote-endpoint = <&vopl_out_mipi>;
1749 compatible = "rockchip,rk3399-edp";
1750 reg = <0x0 0xff970000 0x0 0x8000>;
1751 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1752 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1753 clock-names = "dp", "pclk";
1754 resets = <&cru SRST_P_EDP_CTRL>;
1756 rockchip,grf = <&grf>;
1757 status = "disabled";
1758 pinctrl-names = "default";
1759 pinctrl-0 = <&edp_hpd>;
1762 #address-cells = <1>;
1767 #address-cells = <1>;
1770 edp_in_vopb: endpoint@0 {
1772 remote-endpoint = <&vopb_out_edp>;
1775 edp_in_vopl: endpoint@1 {
1777 remote-endpoint = <&vopl_out_edp>;
1783 display_subsystem: display-subsystem {
1784 compatible = "rockchip,display-subsystem";
1785 ports = <&vopl_out>, <&vopb_out>;
1786 status = "disabled";
1790 compatible = "rockchip,rk3399-pinctrl";
1791 rockchip,grf = <&grf>;
1792 rockchip,pmu = <&pmugrf>;
1793 #address-cells = <0x2>;
1794 #size-cells = <0x2>;
1797 gpio0: gpio0@ff720000 {
1798 compatible = "rockchip,gpio-bank";
1799 reg = <0x0 0xff720000 0x0 0x100>;
1800 clocks = <&pmucru PCLK_GPIO0_PMU>;
1801 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1804 #gpio-cells = <0x2>;
1806 interrupt-controller;
1807 #interrupt-cells = <0x2>;
1810 gpio1: gpio1@ff730000 {
1811 compatible = "rockchip,gpio-bank";
1812 reg = <0x0 0xff730000 0x0 0x100>;
1813 clocks = <&pmucru PCLK_GPIO1_PMU>;
1814 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1817 #gpio-cells = <0x2>;
1819 interrupt-controller;
1820 #interrupt-cells = <0x2>;
1823 gpio2: gpio2@ff780000 {
1824 compatible = "rockchip,gpio-bank";
1825 reg = <0x0 0xff780000 0x0 0x100>;
1826 clocks = <&cru PCLK_GPIO2>;
1827 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1830 #gpio-cells = <0x2>;
1832 interrupt-controller;
1833 #interrupt-cells = <0x2>;
1836 gpio3: gpio3@ff788000 {
1837 compatible = "rockchip,gpio-bank";
1838 reg = <0x0 0xff788000 0x0 0x100>;
1839 clocks = <&cru PCLK_GPIO3>;
1840 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1843 #gpio-cells = <0x2>;
1845 interrupt-controller;
1846 #interrupt-cells = <0x2>;
1849 gpio4: gpio4@ff790000 {
1850 compatible = "rockchip,gpio-bank";
1851 reg = <0x0 0xff790000 0x0 0x100>;
1852 clocks = <&cru PCLK_GPIO4>;
1853 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1856 #gpio-cells = <0x2>;
1858 interrupt-controller;
1859 #interrupt-cells = <0x2>;
1862 pcfg_pull_up: pcfg-pull-up {
1866 pcfg_pull_down: pcfg-pull-down {
1870 pcfg_pull_none: pcfg-pull-none {
1874 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1876 drive-strength = <20>;
1879 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1881 drive-strength = <20>;
1884 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1886 drive-strength = <18>;
1889 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1891 drive-strength = <12>;
1894 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1896 drive-strength = <8>;
1899 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1901 drive-strength = <4>;
1904 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1906 drive-strength = <2>;
1909 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1911 drive-strength = <12>;
1914 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1916 drive-strength = <13>;
1919 pcfg_output_high: pcfg-output-high {
1923 pcfg_output_low: pcfg-output-low {
1927 pcfg_input: pcfg-input {
1932 emmc_pwr: emmc-pwr {
1934 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1939 rgmii_pins: rgmii-pins {
1942 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1944 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1946 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1948 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1950 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1952 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1954 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1956 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1958 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1960 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1962 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1964 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1966 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1968 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1970 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1973 rmii_pins: rmii-pins {
1976 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1978 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1980 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1982 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1984 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1986 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1988 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1990 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1992 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1994 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1999 i2c0_xfer: i2c0-xfer {
2001 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2002 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2007 i2c1_xfer: i2c1-xfer {
2009 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2010 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2015 i2c2_xfer: i2c2-xfer {
2017 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2018 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2023 i2c3_xfer: i2c3-xfer {
2025 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2026 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2029 i2c3_gpio: i2c3_gpio {
2031 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2032 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2038 i2c4_xfer: i2c4-xfer {
2040 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2041 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2046 i2c5_xfer: i2c5-xfer {
2048 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2049 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2054 i2c6_xfer: i2c6-xfer {
2056 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2057 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2062 i2c7_xfer: i2c7-xfer {
2064 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2065 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2070 i2c8_xfer: i2c8-xfer {
2072 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2073 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2078 i2s0_8ch_bus: i2s0-8ch-bus {
2080 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2081 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2082 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2083 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2084 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2085 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2086 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2087 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2088 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2093 i2s1_2ch_bus: i2s1-2ch-bus {
2095 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2096 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2097 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2098 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2099 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2104 sdio0_bus1: sdio0-bus1 {
2106 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2109 sdio0_bus4: sdio0-bus4 {
2111 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2112 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2113 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2114 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2117 sdio0_cmd: sdio0-cmd {
2119 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2122 sdio0_clk: sdio0-clk {
2124 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2127 sdio0_cd: sdio0-cd {
2129 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2132 sdio0_pwr: sdio0-pwr {
2134 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2137 sdio0_bkpwr: sdio0-bkpwr {
2139 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2142 sdio0_wp: sdio0-wp {
2144 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2147 sdio0_int: sdio0-int {
2149 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2154 sdmmc_bus1: sdmmc-bus1 {
2156 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2159 sdmmc_bus4: sdmmc-bus4 {
2161 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2162 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2163 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2164 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2167 sdmmc_clk: sdmmc-clk {
2169 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2172 sdmmc_cmd: sdmmc-cmd {
2174 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2177 sdmmc_cd: sdmcc-cd {
2179 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2182 sdmmc_wp: sdmmc-wp {
2184 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2189 spdif_bus: spdif-bus {
2191 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2194 spdif_bus_1: spdif-bus-1 {
2196 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2201 spi0_clk: spi0-clk {
2203 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2205 spi0_cs0: spi0-cs0 {
2207 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2209 spi0_cs1: spi0-cs1 {
2211 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2215 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2219 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2224 spi1_clk: spi1-clk {
2226 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2228 spi1_cs0: spi1-cs0 {
2230 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2234 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2238 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2243 spi2_clk: spi2-clk {
2245 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2247 spi2_cs0: spi2-cs0 {
2249 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2253 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2257 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2262 spi3_clk: spi3-clk {
2264 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2266 spi3_cs0: spi3-cs0 {
2268 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2272 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2276 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2281 spi4_clk: spi4-clk {
2283 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2285 spi4_cs0: spi4-cs0 {
2287 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2291 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2295 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2300 spi5_clk: spi5-clk {
2302 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2304 spi5_cs0: spi5-cs0 {
2306 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2310 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2314 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2319 otp_gpio: otp-gpio {
2320 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2324 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2329 uart0_xfer: uart0-xfer {
2331 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2332 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2335 uart0_cts: uart0-cts {
2337 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2340 uart0_rts: uart0-rts {
2342 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2347 uart1_xfer: uart1-xfer {
2349 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2350 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2355 uart2a_xfer: uart2a-xfer {
2357 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2358 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2363 uart2b_xfer: uart2b-xfer {
2365 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2366 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2371 uart2c_xfer: uart2c-xfer {
2373 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2374 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2379 uart3_xfer: uart3-xfer {
2381 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2382 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2385 uart3_cts: uart3-cts {
2387 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2390 uart3_rts: uart3-rts {
2392 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2397 uart4_xfer: uart4-xfer {
2399 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2400 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2405 uarthdcp_xfer: uarthdcp-xfer {
2407 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2408 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2413 pwm0_pin: pwm0-pin {
2415 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2418 vop0_pwm_pin: vop0-pwm-pin {
2420 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2425 pwm1_pin: pwm1-pin {
2427 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2430 vop1_pwm_pin: vop1-pwm-pin {
2432 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2437 pwm2_pin: pwm2-pin {
2439 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2444 pwm3a_pin: pwm3a-pin {
2446 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2451 pwm3b_pin: pwm3b-pin {
2453 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2460 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2465 hdmi_i2c_xfer: hdmi-i2c-xfer {
2467 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2468 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2471 hdmi_cec: hdmi-cec {
2473 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2478 pcie_clkreqn: pci-clkreqn {
2480 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2483 pcie_clkreqnb: pci-clkreqnb {
2485 <4 24 RK_FUNC_1 &pcfg_pull_none>;