arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <121>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                 };
 122
 123                 cpu_l1: cpu@1 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a53", "arm,armv8";
 126                         reg = <0x0 0x1>;
 127                         enable-method = "psci";
 128                         clocks = <&cru ARMCLKL>;
 129                         cpu-idle-states = <&cpu_sleep>;
 130                         operating-points-v2 = <&cluster0_opp>;
 131                 };
 132
 133                 cpu_l2: cpu@2 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a53", "arm,armv8";
 136                         reg = <0x0 0x2>;
 137                         enable-method = "psci";
 138                         clocks = <&cru ARMCLKL>;
 139                         cpu-idle-states = <&cpu_sleep>;
 140                         operating-points-v2 = <&cluster0_opp>;
 141                 };
 142
 143                 cpu_l3: cpu@3 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a53", "arm,armv8";
 146                         reg = <0x0 0x3>;
 147                         enable-method = "psci";
 148                         clocks = <&cru ARMCLKL>;
 149                         cpu-idle-states = <&cpu_sleep>;
 150                         operating-points-v2 = <&cluster0_opp>;
 151                 };
 152
 153                 cpu_b0: cpu@100 {
 154                         device_type = "cpu";
 155                         compatible = "arm,cortex-a72", "arm,armv8";
 156                         reg = <0x0 0x100>;
 157                         enable-method = "psci";
 158                         #cooling-cells = <2>; /* min followed by max */
 159                         dynamic-power-coefficient = <1068>;
 160                         clocks = <&cru ARMCLKB>;
 161                         cpu-idle-states = <&cpu_sleep>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164
 165                 cpu_b1: cpu@101 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a72", "arm,armv8";
 168                         reg = <0x0 0x101>;
 169                         enable-method = "psci";
 170                         clocks = <&cru ARMCLKB>;
 171                         cpu-idle-states = <&cpu_sleep>;
 172                         operating-points-v2 = <&cluster1_opp>;
 173                 };
 174
 175                 idle-states {
 176                         entry-method = "psci";
 177                         cpu_sleep: cpu-sleep-0 {
 178                                 compatible = "arm,idle-state";
 179                                 local-timer-stop;
 180                                 arm,psci-suspend-param = <0x0010000>;
 181                                 entry-latency-us = <350>;
 182                                 exit-latency-us = <600>;
 183                                 min-residency-us = <1150>;
 184                         };
 185                 };
 186         };
 187
 188         cluster0_opp: opp_table0 {
 189                 compatible = "operating-points-v2";
 190                 opp-shared;
 191
 192                 opp00 {
 193                         opp-hz = /bits/ 64 <408000000>;
 194                         opp-microvolt = <800000>;
 195                         clock-latency-ns = <40000>;
 196                 };
 197                 opp01 {
 198                         opp-hz = /bits/ 64 <600000000>;
 199                         opp-microvolt = <800000>;
 200                 };
 201                 opp02 {
 202                         opp-hz = /bits/ 64 <816000000>;
 203                         opp-microvolt = <800000>;
 204                 };
 205                 opp03 {
 206                         opp-hz = /bits/ 64 <1008000000>;
 207                         opp-microvolt = <875000>;
 208                 };
 209                 opp04 {
 210                         opp-hz = /bits/ 64 <1200000000>;
 211                         opp-microvolt = <925000>;
 212                 };
 213                 opp05 {
 214                         opp-hz = /bits/ 64 <1416000000>;
 215                         opp-microvolt = <1025000>;
 216                 };
 217         };
 218
 219         cluster1_opp: opp_table1 {
 220                 compatible = "operating-points-v2";
 221                 opp-shared;
 222
 223                 opp00 {
 224                         opp-hz = /bits/ 64 <408000000>;
 225                         opp-microvolt = <800000>;
 226                         clock-latency-ns = <40000>;
 227                 };
 228                 opp01 {
 229                         opp-hz = /bits/ 64 <600000000>;
 230                         opp-microvolt = <800000>;
 231                 };
 232                 opp02 {
 233                         opp-hz = /bits/ 64 <816000000>;
 234                         opp-microvolt = <800000>;
 235                 };
 236                 opp03 {
 237                         opp-hz = /bits/ 64 <1008000000>;
 238                         opp-microvolt = <850000>;
 239                 };
 240                 opp04 {
 241                         opp-hz = /bits/ 64 <1200000000>;
 242                         opp-microvolt = <925000>;
 243                 };
 244         };
 245
 246         timer {
 247                 compatible = "arm,armv8-timer";
 248                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 249                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 250                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 251                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 252         };
 253
 254         arm-pmu {
 255                 compatible = "arm,armv8-pmuv3";
 256                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 257         };
 258
 259         xin24m: xin24m {
 260                 compatible = "fixed-clock";
 261                 #clock-cells = <0>;
 262                 clock-frequency = <24000000>;
 263                 clock-output-names = "xin24m";
 264         };
 265
 266         amba {
 267                 compatible = "arm,amba-bus";
 268                 #address-cells = <2>;
 269                 #size-cells = <2>;
 270                 ranges;
 271
 272                 dmac_bus: dma-controller@ff6d0000 {
 273                         compatible = "arm,pl330", "arm,primecell";
 274                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 275                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 277                         #dma-cells = <1>;
 278                         clocks = <&cru ACLK_DMAC0_PERILP>;
 279                         clock-names = "apb_pclk";
 280                 };
 281
 282                 dmac_peri: dma-controller@ff6e0000 {
 283                         compatible = "arm,pl330", "arm,primecell";
 284                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 285                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 287                         #dma-cells = <1>;
 288                         clocks = <&cru ACLK_DMAC1_PERILP>;
 289                         clock-names = "apb_pclk";
 290                 };
 291         };
 292
 293         gmac: eth@fe300000 {
 294                 compatible = "rockchip,rk3399-gmac";
 295                 reg = <0x0 0xfe300000 0x0 0x10000>;
 296                 rockchip,grf = <&grf>;
 297                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 298                 interrupt-names = "macirq";
 299                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 300                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 301                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 302                          <&cru PCLK_GMAC>;
 303                 clock-names = "stmmaceth", "mac_clk_rx",
 304                               "mac_clk_tx", "clk_mac_ref",
 305                               "clk_mac_refout", "aclk_mac",
 306                               "pclk_mac";
 307                 resets = <&cru SRST_A_GMAC>;
 308                 reset-names = "stmmaceth";
 309                 status = "disabled";
 310         };
 311
 312         emmc_phy: phy {
 313                 compatible = "rockchip,rk3399-emmc-phy";
 314                 reg-offset = <0xf780>;
 315                 #phy-cells = <0>;
 316                 rockchip,grf = <&grf>;
 317                 ctrl-base = <0xfe330000>;
 318                 status = "disabled";
 319         };
 320
 321         sdio0: dwmmc@fe310000 {
 322                 compatible = "rockchip,rk3399-dw-mshc",
 323                              "rockchip,rk3288-dw-mshc";
 324                 reg = <0x0 0xfe310000 0x0 0x4000>;
 325                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 326                 clock-freq-min-max = <400000 150000000>;
 327                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 328                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 329                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 330                 fifo-depth = <0x100>;
 331                 status = "disabled";
 332         };
 333
 334         sdmmc: dwmmc@fe320000 {
 335                 compatible = "rockchip,rk3399-dw-mshc",
 336                              "rockchip,rk3288-dw-mshc";
 337                 reg = <0x0 0xfe320000 0x0 0x4000>;
 338                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 339                 clock-freq-min-max = <400000 150000000>;
 340                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 341                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 342                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 343                 fifo-depth = <0x100>;
 344                 status = "disabled";
 345         };
 346
 347         sdhci: sdhci@fe330000 {
 348                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 349                 reg = <0x0 0xfe330000 0x0 0x10000>;
 350                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 352                 clock-names = "clk_xin", "clk_ahb";
 353                 assigned-clocks = <&cru SCLK_EMMC>;
 354                 assigned-clock-parents = <&cru PLL_CPLL>;
 355                 assigned-clock-rates = <200000000>;
 356                 phys = <&emmc_phy>;
 357                 phy-names = "phy_arasan";
 358                 status = "disabled";
 359         };
 360
 361         usb2phy: usb2phy {
 362                 compatible = "rockchip,rk3399-usb-phy";
 363                 rockchip,grf = <&grf>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366
 367                 usb2phy0: usb2-phy0 {
 368                         #phy-cells = <0>;
 369                         #clock-cells = <0>;
 370                         reg = <0xe458>;
 371                 };
 372
 373                 usb2phy1: usb2-phy1 {
 374                         #phy-cells = <0>;
 375                         #clock-cells = <0>;
 376                         reg = <0xe468>;
 377                 };
 378         };
 379
 380         usb_host0_ehci: usb@fe380000 {
 381                 compatible = "generic-ehci";
 382                 reg = <0x0 0xfe380000 0x0 0x20000>;
 383                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 384                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 385                 clock-names = "hclk_host0", "hclk_host0_arb";
 386                 phys = <&usb2phy0>;
 387                 phy-names = "usb2_phy0";
 388                 status = "disabled";
 389         };
 390
 391         usb_host0_ohci: usb@fe3a0000 {
 392                 compatible = "generic-ohci";
 393                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 394                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 396                 clock-names = "hclk_host0", "hclk_host0_arb";
 397                 status = "disabled";
 398         };
 399
 400         usb_host1_ehci: usb@fe3c0000 {
 401                 compatible = "generic-ehci";
 402                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 403                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 404                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 405                 clock-names = "hclk_host1", "hclk_host1_arb";
 406                 phys = <&usb2phy1>;
 407                 phy-names = "usb2_phy1";
 408                 status = "disabled";
 409         };
 410
 411         usb_host1_ohci: usb@fe3e0000 {
 412                 compatible = "generic-ohci";
 413                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 414                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 416                 clock-names = "hclk_host1", "hclk_host1_arb";
 417                 status = "disabled";
 418         };
 419
 420         usbdrd3_0: usb@fe800000 {
 421                 compatible = "rockchip,dwc3";
 422                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 423                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 424                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 425                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 426                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 427                               "aclk_usb3", "aclk_usb3_grf";
 428                 #address-cells = <2>;
 429                 #size-cells = <2>;
 430                 ranges;
 431                 status = "disabled";
 432                 usbdrd_dwc3_0: dwc3 {
 433                         compatible = "snps,dwc3";
 434                         reg = <0x0 0xfe800000 0x0 0x100000>;
 435                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 436                         dr_mode = "otg";
 437                         tx-fifo-resize;
 438                         snps,dis_enblslpm_quirk;
 439                         snps,phyif_utmi_16_bits;
 440                         snps,dis_u2_freeclk_exists_quirk;
 441                         snps,dis_del_phy_power_chg_quirk;
 442                         snps,xhci_slow_suspend_quirk;
 443                         status = "disabled";
 444                 };
 445         };
 446
 447         usbdrd3_1: usb@fe900000 {
 448                 compatible = "rockchip,dwc3";
 449                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 450                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 451                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 452                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 453                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 454                               "aclk_usb3", "aclk_usb3_grf";
 455                 #address-cells = <2>;
 456                 #size-cells = <2>;
 457                 ranges;
 458                 status = "disabled";
 459                 usbdrd_dwc3_1: dwc3 {
 460                         compatible = "snps,dwc3";
 461                         reg = <0x0 0xfe900000 0x0 0x100000>;
 462                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 463                         dr_mode = "otg";
 464                         tx-fifo-resize;
 465                         snps,dis_enblslpm_quirk;
 466                         snps,phyif_utmi_16_bits;
 467                         snps,dis_u2_freeclk_exists_quirk;
 468                         snps,dis_del_phy_power_chg_quirk;
 469                         snps,xhci_slow_suspend_quirk;
 470                         status = "disabled";
 471                 };
 472         };
 473
 474         gic: interrupt-controller@fee00000 {
 475                 compatible = "arm,gic-v3";
 476                 #interrupt-cells = <3>;
 477                 #address-cells = <2>;
 478                 #size-cells = <2>;
 479                 ranges;
 480                 interrupt-controller;
 481
 482                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 483                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 484                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 485                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 486                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 487                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 488                 its: interrupt-controller@fee20000 {
 489                         compatible = "arm,gic-v3-its";
 490                         msi-controller;
 491                         reg = <0x0 0xfee20000 0x0 0x20000>;
 492                 };
 493         };
 494
 495         saradc: saradc@ff100000 {
 496                 compatible = "rockchip,rk3399-saradc";
 497                 reg = <0x0 0xff100000 0x0 0x100>;
 498                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 499                 #io-channel-cells = <1>;
 500                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 501                 clock-names = "saradc", "apb_pclk";
 502                 status = "disabled";
 503         };
 504
 505         i2c0: i2c@ff3c0000 {
 506                 compatible = "rockchip,rk3399-i2c";
 507                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 508                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 509                 clock-names = "i2c", "pclk";
 510                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 511                 pinctrl-names = "default";
 512                 pinctrl-0 = <&i2c0_xfer>;
 513                 #address-cells = <1>;
 514                 #size-cells = <0>;
 515                 status = "disabled";
 516         };
 517
 518         i2c1: i2c@ff110000 {
 519                 compatible = "rockchip,rk3399-i2c";
 520                 reg = <0x0 0xff110000 0x0 0x1000>;
 521                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 522                 clock-names = "i2c", "pclk";
 523                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&i2c1_xfer>;
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 status = "disabled";
 529         };
 530
 531         i2c2: i2c@ff120000 {
 532                 compatible = "rockchip,rk3399-i2c";
 533                 reg = <0x0 0xff120000 0x0 0x1000>;
 534                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 535                 clock-names = "i2c", "pclk";
 536                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c2_xfer>;
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 status = "disabled";
 542         };
 543
 544         i2c3: i2c@ff130000 {
 545                 compatible = "rockchip,rk3399-i2c";
 546                 reg = <0x0 0xff130000 0x0 0x1000>;
 547                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 548                 clock-names = "i2c", "pclk";
 549                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c3_xfer>;
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 status = "disabled";
 555         };
 556
 557         i2c5: i2c@ff140000 {
 558                 compatible = "rockchip,rk3399-i2c";
 559                 reg = <0x0 0xff140000 0x0 0x1000>;
 560                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 561                 clock-names = "i2c", "pclk";
 562                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&i2c5_xfer>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         i2c6: i2c@ff150000 {
 571                 compatible = "rockchip,rk3399-i2c";
 572                 reg = <0x0 0xff150000 0x0 0x1000>;
 573                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 574                 clock-names = "i2c", "pclk";
 575                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c6_xfer>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         i2c7: i2c@ff160000 {
 584                 compatible = "rockchip,rk3399-i2c";
 585                 reg = <0x0 0xff160000 0x0 0x1000>;
 586                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 587                 clock-names = "i2c", "pclk";
 588                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 589                 pinctrl-names = "default";
 590                 pinctrl-0 = <&i2c7_xfer>;
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593                 status = "disabled";
 594         };
 595
 596         uart0: serial@ff180000 {
 597                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 598                 reg = <0x0 0xff180000 0x0 0x100>;
 599                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 600                 clock-names = "baudclk", "apb_pclk";
 601                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 602                 reg-shift = <2>;
 603                 reg-io-width = <4>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 606                 status = "disabled";
 607         };
 608
 609         uart1: serial@ff190000 {
 610                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 611                 reg = <0x0 0xff190000 0x0 0x100>;
 612                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 613                 clock-names = "baudclk", "apb_pclk";
 614                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 615                 reg-shift = <2>;
 616                 reg-io-width = <4>;
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&uart1_xfer>;
 619                 status = "disabled";
 620         };
 621
 622         uart2: serial@ff1a0000 {
 623                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 624                 reg = <0x0 0xff1a0000 0x0 0x100>;
 625                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 626                 clock-names = "baudclk", "apb_pclk";
 627                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 628                 reg-shift = <2>;
 629                 reg-io-width = <4>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&uart2c_xfer>;
 632                 status = "disabled";
 633         };
 634
 635         uart3: serial@ff1b0000 {
 636                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 637                 reg = <0x0 0xff1b0000 0x0 0x100>;
 638                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 639                 clock-names = "baudclk", "apb_pclk";
 640                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 641                 reg-shift = <2>;
 642                 reg-io-width = <4>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 645                 status = "disabled";
 646         };
 647
 648         spi0: spi@ff1c0000 {
 649                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 650                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 651                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 652                 clock-names = "spiclk", "apb_pclk";
 653                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 654                 pinctrl-names = "default";
 655                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 status = "disabled";
 659         };
 660
 661         spi1: spi@ff1d0000 {
 662                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 663                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 664                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 665                 clock-names = "spiclk", "apb_pclk";
 666                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 669                 #address-cells = <1>;
 670                 #size-cells = <0>;
 671                 status = "disabled";
 672         };
 673
 674         spi2: spi@ff1e0000 {
 675                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 676                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 677                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 678                 clock-names = "spiclk", "apb_pclk";
 679                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 status = "disabled";
 685         };
 686
 687         spi4: spi@ff1f0000 {
 688                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 689                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 690                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 691                 clock-names = "spiclk", "apb_pclk";
 692                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 693                 pinctrl-names = "default";
 694                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 695                 #address-cells = <1>;
 696                 #size-cells = <0>;
 697                 status = "disabled";
 698         };
 699
 700         spi5: spi@ff200000 {
 701                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 702                 reg = <0x0 0xff200000 0x0 0x1000>;
 703                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 704                 clock-names = "spiclk", "apb_pclk";
 705                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 708                 #address-cells = <1>;
 709                 #size-cells = <0>;
 710                 status = "disabled";
 711         };
 712
 713         thermal-zones {
 714                 soc_thermal: soc-thermal {
 715                         polling-delay-passive = <100>; /* milliseconds */
 716                         polling-delay = <1000>; /* milliseconds */
 717                         sustainable-power = <2600>; /* milliwatts */
 718
 719                         thermal-sensors = <&tsadc 0>;
 720
 721                         trips {
 722                                 threshold: trip-point@0 {
 723                                         temperature = <70000>; /* millicelsius */
 724                                         hysteresis = <2000>; /* millicelsius */
 725                                         type = "passive";
 726                                 };
 727                                 target: trip-point@1 {
 728                                         temperature = <85000>; /* millicelsius */
 729                                         hysteresis = <2000>; /* millicelsius */
 730                                         type = "passive";
 731                                 };
 732                                 soc_crit: soc-crit {
 733                                         temperature = <95000>; /* millicelsius */
 734                                         hysteresis = <2000>; /* millicelsius */
 735                                         type = "critical";
 736                                 };
 737                         };
 738
 739                         cooling-maps {
 740                                 map0 {
 741                                         trip = <&target>;
 742                                         cooling-device =
 743                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 744                                 };
 745                                 map1 {
 746                                         trip = <&target>;
 747                                         cooling-device =
 748                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 749                                 };
 750                                 map2 {
 751                                         trip = <&target>;
 752                                         cooling-device =
 753                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 754                                 };
 755                         };
 756                 };
 757
 758                 gpu_thermal: gpu-thermal {
 759                         polling-delay-passive = <100>; /* milliseconds */
 760                         polling-delay = <1000>; /* milliseconds */
 761
 762                         thermal-sensors = <&tsadc 1>;
 763                 };
 764         };
 765
 766         tsadc: tsadc@ff260000 {
 767                 compatible = "rockchip,rk3399-tsadc";
 768                 reg = <0x0 0xff260000 0x0 0x100>;
 769                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 770                 rockchip,grf = <&grf>;
 771                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 772                 clock-names = "tsadc", "apb_pclk";
 773                 assigned-clocks = <&cru SCLK_TSADC>;
 774                 assigned-clock-rates = <750000>;
 775                 resets = <&cru SRST_TSADC>;
 776                 reset-names = "tsadc-apb";
 777                 pinctrl-names = "init", "default", "sleep";
 778                 pinctrl-0 = <&otp_gpio>;
 779                 pinctrl-1 = <&otp_out>;
 780                 pinctrl-2 = <&otp_gpio>;
 781                 #thermal-sensor-cells = <1>;
 782                 rockchip,hw-tshut-temp = <95000>;
 783                 status = "disabled";
 784         };
 785
 786         qos_gpu: qos_gpu@0xffae0000 {
 787                 compatible ="syscon";
 788                 reg = <0x0 0xffae0000 0x0 0x20>;
 789         };
 790         qos_video_m0: qos_video_m0@0xffab8000 {
 791                 compatible ="syscon";
 792                 reg = <0x0 0xffab8000 0x0 0x20>;
 793         };
 794         qos_video_m1_r: qos_video_m1_r@0xffac0000 {
 795                 compatible ="syscon";
 796                 reg = <0x0 0xffac0000 0x0 0x20>;
 797         };
 798         qos_video_m1_w: qos_video_m1_w@0xffac0080 {
 799                 compatible ="syscon";
 800                 reg = <0x0 0xffac0080 0x0 0x20>;
 801         };
 802         qos_rga_r: qos_rga_r@0xffab0000 {
 803                 compatible ="syscon";
 804                 reg = <0x0 0xffab0000 0x0 0x20>;
 805         };
 806         qos_rga_w: qos_rga_w@0xffab0080 {
 807                 compatible ="syscon";
 808                 reg = <0x0 0xffab0000 0x0 0x20>;
 809         };
 810         qos_iep: qos_iep@0xffa98000 {
 811                 compatible ="syscon";
 812                 reg = <0x0 0xffa98000 0x0 0x20>;
 813         };
 814         qos_vop_big_r: qos_vop_big_r@0xffac8000 {
 815                 compatible ="syscon";
 816                 reg = <0x0 0xffac8000 0x0 0x20>;
 817         };
 818         qos_vop_big_w: qos_vop_big_w@0xffac8080 {
 819                 compatible ="syscon";
 820                 reg = <0x0 0xffac8080 0x0 0x20>;
 821         };
 822         qos_vop_little: qos_vop_little@0xffad0000 {
 823                 compatible ="syscon";
 824                 reg = <0x0 0xffad0000 0x0 0x20>;
 825         };
 826         qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
 827                 compatible ="syscon";
 828                 reg = <0x0 0xffaa0000 0x0 0x20>;
 829         };
 830         qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
 831                 compatible ="syscon";
 832                 reg = <0x0 0xffaa0080 0x0 0x20>;
 833         };
 834         qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
 835                 compatible ="syscon";
 836                 reg = <0x0 0xffaa8000 0x0 0x20>;
 837         };
 838         qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
 839                 compatible ="syscon";
 840                 reg = <0x0 0xffaa8080 0x0 0x20>;
 841         };
 842         qos_hdcp: qos_hdcp@0xffa90000 {
 843                 compatible ="syscon";
 844                 reg = <0x0 0xffa90000 0x0 0x20>;
 845         };
 846
 847         pmu: power-management@ff310000 {
 848                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 849                 reg = <0x0 0xff310000 0x0 0x1000>;
 850
 851                 power: power-controller {
 852                         status = "okay";
 853                         compatible = "rockchip,rk3399-power-controller";
 854                         #power-domain-cells = <1>;
 855                         #address-cells = <1>;
 856                         #size-cells = <0>;
 857
 858
 859                         pd_vdu {
 860                                 reg = <RK3399_PD_VDU>;
 861                                 pm_qos = <&qos_video_m1_r>,
 862                                          <&qos_video_m1_w>;
 863                         };
 864                         pd_vcodec {
 865                                 reg = <RK3399_PD_VCODEC>;
 866                                 pm_qos = <&qos_video_m0>;
 867                         };
 868                         pd_iep {
 869                                 reg = <RK3399_PD_IEP>;
 870                                 pm_qos = <&qos_iep>;
 871                         };
 872                         pd_rga {
 873                                 reg = <RK3399_PD_RGA>;
 874                                 pm_qos = <&qos_rga_r>,
 875                                          <&qos_rga_w>;
 876                         };
 877                         pd_vio {
 878                                 reg = <RK3399_PD_VIO>;
 879                                 #address-cells = <1>;
 880                                 #size-cells = <0>;
 881
 882                                 pd_isp0 {
 883                                         reg = <RK3399_PD_ISP0>;
 884                                         pm_qos = <&qos_isp0_m0>,
 885                                                  <&qos_isp0_m1>;
 886                                 };
 887                                 pd_isp1 {
 888                                         reg = <RK3399_PD_ISP1>;
 889                                         pm_qos = <&qos_isp1_m0>,
 890                                                  <&qos_isp1_m1>;
 891                                 };
 892                                 pd_hdcp {
 893                                         reg = <RK3399_PD_HDCP>;
 894                                         pm_qos = <&qos_hdcp>;
 895                                 };
 896                                 pd_vo {
 897                                         reg = <RK3399_PD_VO>;
 898                                         #address-cells = <1>;
 899                                         #size-cells = <0>;
 900
 901                                         pd_vopb {
 902                                                 reg = <RK3399_PD_VOPB>;
 903                                                 pm_qos = <&qos_vop_big_r>,
 904                                                          <&qos_vop_big_w>;
 905                                         };
 906                                         pd_vopl {
 907                                                 reg = <RK3399_PD_VOPL>;
 908                                                 pm_qos = <&qos_vop_little>;
 909                                         };
 910                                 };
 911                         };
 912                         pd_gpu {
 913                                 reg = <RK3399_PD_GPU>;
 914                                 pm_qos = <&qos_gpu>;
 915                         };
 916                 };
 917         };
 918
 919         pmugrf: syscon@ff320000 {
 920                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 921                 reg = <0x0 0xff320000 0x0 0x1000>;
 922
 923                 reboot-mode {
 924                         compatible = "syscon-reboot-mode";
 925                         offset = <0x300>;
 926                         mode-normal = <BOOT_NORMAL>;
 927                         mode-recovery = <BOOT_RECOVERY>;
 928                         mode-bootloader = <BOOT_FASTBOOT>;
 929                         mode-loader = <BOOT_LOADER>;
 930                 };
 931         };
 932
 933         spi3: spi@ff350000 {
 934                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 935                 reg = <0x0 0xff350000 0x0 0x1000>;
 936                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 937                 clock-names = "spiclk", "apb_pclk";
 938                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 939                 pinctrl-names = "default";
 940                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 941                 #address-cells = <1>;
 942                 #size-cells = <0>;
 943                 status = "disabled";
 944         };
 945
 946         uart4: serial@ff370000 {
 947                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 948                 reg = <0x0 0xff370000 0x0 0x100>;
 949                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 950                 clock-names = "baudclk", "apb_pclk";
 951                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 952                 reg-shift = <2>;
 953                 reg-io-width = <4>;
 954                 pinctrl-names = "default";
 955                 pinctrl-0 = <&uart4_xfer>;
 956                 status = "disabled";
 957         };
 958
 959         i2c4: i2c@ff3d0000 {
 960                 compatible = "rockchip,rk3399-i2c";
 961                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 962                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 963                 clock-names = "i2c", "pclk";
 964                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 965                 pinctrl-names = "default";
 966                 pinctrl-0 = <&i2c4_xfer>;
 967                 #address-cells = <1>;
 968                 #size-cells = <0>;
 969                 status = "disabled";
 970         };
 971
 972         i2c8: i2c@ff3e0000 {
 973                 compatible = "rockchip,rk3399-i2c";
 974                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 975                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 976                 clock-names = "i2c", "pclk";
 977                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 978                 pinctrl-names = "default";
 979                 pinctrl-0 = <&i2c8_xfer>;
 980                 #address-cells = <1>;
 981                 #size-cells = <0>;
 982                 status = "disabled";
 983         };
 984
 985         pcie0: pcie@f8000000 {
 986                 compatible = "rockchip,rk3399-pcie";
 987                 #address-cells = <3>;
 988                 #size-cells = <2>;
 989                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 990                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
 991                 clock-names = "aclk_pcie", "aclk_perf_pcie",
 992                               "hclk_pcie", "clk_pciephy_ref";
 993                 bus-range = <0x0 0x1>;
 994                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 995                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 996                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 997                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
 998                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
 999                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1000                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1001                       < 0x0 0xfd000000 0x0 0x1000000 >;
1002                 reg-name = "axi-base", "apb-base";
1003                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1004                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1005                          <&cru SRST_PCIE_PIPE>;
1006                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1007                               "mgmt-sticky-rst", "pipe-rst";
1008                 rockchip,grf = <&grf>;
1009                 pcie-conf = <0xe220>;
1010                 pcie-status = <0xe2a4>;
1011                 pcie-laneoff = <0xe214>;
1012                 msi-parent = <&its>;
1013                 #interrupt-cells = <1>;
1014                 interrupt-map-mask = <0 0 0 7>;
1015                 interrupt-map = <0 0 0 1 &pcie0 1>,
1016                                 <0 0 0 2 &pcie0 2>,
1017                                 <0 0 0 3 &pcie0 3>,
1018                                 <0 0 0 4 &pcie0 4>;
1019                 status = "disabled";
1020                 pcie_intc: interrupt-controller {
1021                         interrupt-controller;
1022                         #address-cells = <0>;
1023                         #interrupt-cells = <1>;
1024                 };
1025         };
1026
1027         pwm0: pwm@ff420000 {
1028                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1029                 reg = <0x0 0xff420000 0x0 0x10>;
1030                 #pwm-cells = <3>;
1031                 pinctrl-names = "default";
1032                 pinctrl-0 = <&pwm0_pin>;
1033                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1034                 clock-names = "pwm";
1035                 status = "disabled";
1036         };
1037
1038         pwm1: pwm@ff420010 {
1039                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1040                 reg = <0x0 0xff420010 0x0 0x10>;
1041                 #pwm-cells = <3>;
1042                 pinctrl-names = "default";
1043                 pinctrl-0 = <&pwm1_pin>;
1044                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1045                 clock-names = "pwm";
1046                 status = "disabled";
1047         };
1048
1049         pwm2: pwm@ff420020 {
1050                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1051                 reg = <0x0 0xff420020 0x0 0x10>;
1052                 #pwm-cells = <3>;
1053                 pinctrl-names = "default";
1054                 pinctrl-0 = <&pwm2_pin>;
1055                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1056                 clock-names = "pwm";
1057                 status = "disabled";
1058         };
1059
1060         pwm3: pwm@ff420030 {
1061                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1062                 reg = <0x0 0xff420030 0x0 0x10>;
1063                 #pwm-cells = <3>;
1064                 pinctrl-names = "default";
1065                 pinctrl-0 = <&pwm3a_pin>;
1066                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1067                 clock-names = "pwm";
1068                 status = "disabled";
1069         };
1070
1071         rga: rga@ff680000 {
1072                 compatible = "rockchip,rk3399-rga";
1073                 reg = <0x0 0xff680000 0x0 0x10000>;
1074                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1075                 interrupt-names = "rga";
1076                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1077                 clock-names = "aclk", "hclk", "sclk";
1078                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1079                 reset-names = "core", "axi", "ahb";
1080                 status = "disabled";
1081         };
1082
1083         pmucru: pmu-clock-controller@ff750000 {
1084                 compatible = "rockchip,rk3399-pmucru";
1085                 reg = <0x0 0xff750000 0x0 0x1000>;
1086                 #clock-cells = <1>;
1087                 #reset-cells = <1>;
1088                 assigned-clocks = <&pmucru PLL_PPLL>;
1089                 assigned-clock-rates = <676000000>;
1090         };
1091
1092         cru: clock-controller@ff760000 {
1093                 compatible = "rockchip,rk3399-cru";
1094                 reg = <0x0 0xff760000 0x0 0x1000>;
1095                 #clock-cells = <1>;
1096                 #reset-cells = <1>;
1097                 assigned-clocks =
1098                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1099                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1100                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1101                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1102                         <&cru PLL_NPLL>,
1103                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1104                         <&cru PCLK_PERIHP>,
1105                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1106                         <&cru PCLK_PERILP0>,
1107                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1108                 assigned-clock-rates =
1109                          <400000000>,  <200000000>,
1110                          <400000000>,  <200000000>,
1111                          <816000000>, <816000000>,
1112                          <594000000>,  <800000000>,
1113                         <1000000000>,
1114                          <150000000>,   <75000000>,
1115                           <37500000>,
1116                          <100000000>,  <100000000>,
1117                           <50000000>,
1118                          <100000000>,   <50000000>;
1119         };
1120
1121         grf: syscon@ff770000 {
1122                 compatible = "rockchip,rk3399-grf", "syscon";
1123                 reg = <0x0 0xff770000 0x0 0x10000>;
1124         };
1125
1126         watchdog@ff840000 {
1127                 compatible = "snps,dw-wdt";
1128                 reg = <0x0 0xff840000 0x0 0x100>;
1129                 clocks = <&cru PCLK_WDT>;
1130                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1131         };
1132
1133         rktimer: rktimer@ff850000 {
1134                 compatible = "rockchip,rk3399-timer";
1135                 reg = <0x0 0xff850000 0x0 0x1000>;
1136                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1137                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1138                 clock-names = "pclk", "timer";
1139         };
1140
1141         spdif: spdif@ff870000 {
1142                 compatible = "rockchip,rk3399-spdif";
1143                 reg = <0x0 0xff870000 0x0 0x1000>;
1144                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1145                 dmas = <&dmac_bus 7>;
1146                 dma-names = "tx";
1147                 clock-names = "mclk", "hclk";
1148                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1149                 pinctrl-names = "default";
1150                 pinctrl-0 = <&spdif_bus>;
1151                 status = "disabled";
1152         };
1153
1154         i2s0: i2s@ff880000 {
1155                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1156                 reg = <0x0 0xff880000 0x0 0x1000>;
1157                 rockchip,grf = <&grf>;
1158                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1159                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1160                 dma-names = "tx", "rx";
1161                 clock-names = "i2s_clk", "i2s_hclk";
1162                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1163                 pinctrl-names = "default";
1164                 pinctrl-0 = <&i2s0_8ch_bus>;
1165                 status = "disabled";
1166         };
1167
1168         i2s1: i2s@ff890000 {
1169                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1170                 reg = <0x0 0xff890000 0x0 0x1000>;
1171                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1172                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1173                 dma-names = "tx", "rx";
1174                 clock-names = "i2s_clk", "i2s_hclk";
1175                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1176                 pinctrl-names = "default";
1177                 pinctrl-0 = <&i2s1_2ch_bus>;
1178                 status = "disabled";
1179         };
1180
1181         i2s2: i2s@ff8a0000 {
1182                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1183                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1184                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1185                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1186                 dma-names = "tx", "rx";
1187                 clock-names = "i2s_clk", "i2s_hclk";
1188                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1189                 status = "disabled";
1190         };
1191
1192         gpu: gpu@ff9a0000 {
1193                 compatible = "arm,malit860",
1194                              "arm,malit86x",
1195                              "arm,malit8xx",
1196                              "arm,mali-midgard";
1197
1198                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1199
1200                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1201                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1202                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1203                 interrupt-names = "GPU", "JOB", "MMU";
1204
1205                 clocks = <&cru ACLK_GPU>;
1206                 clock-names = "clk_mali";
1207                 #cooling-cells = <2>; /* min followed by max */
1208                 operating-points-v2 = <&gpu_opp_table>;
1209
1210                 status = "disabled";
1211
1212                 power_model {
1213                         compatible = "arm,mali-simple-power-model";
1214                         voltage = <900>;
1215                         frequency = <500>;
1216                         static-power = <300>;
1217                         dynamic-power = <1780>;
1218                         ts = <32000 4700 (-80) 2>;
1219                         thermal-zone = "gpu-thermal";
1220                 };
1221         };
1222
1223         gpu_opp_table: gpu_opp_table {
1224                 compatible = "operating-points-v2";
1225                 opp-shared;
1226
1227                 opp00 {
1228                         opp-hz = /bits/ 64 <200000000>;
1229                         opp-microvolt = <900000>;
1230                 };
1231                 opp01 {
1232                         opp-hz = /bits/ 64 <300000000>;
1233                         opp-microvolt = <900000>;
1234                 };
1235                 opp02 {
1236                         opp-hz = /bits/ 64 <400000000>;
1237                         opp-microvolt = <900000>;
1238                 };
1239
1240         };
1241
1242         vopl: vop@ff8f0000 {
1243                 compatible = "rockchip,rk3399-vop-lit";
1244                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1245                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1246                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1247                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1248                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1249                 reset-names = "axi", "ahb", "dclk";
1250                 iommus = <&vopl_mmu>;
1251                 status = "disabled";
1252
1253                 vopl_out: port {
1254                         #address-cells = <1>;
1255                         #size-cells = <0>;
1256
1257                         vopl_out_mipi: endpoint@0 {
1258                                 reg = <0>;
1259                                 remote-endpoint = <&mipi_in_vopl>;
1260                         };
1261
1262                         vopl_out_edp: endpoint@1 {
1263                                 reg = <1>;
1264                                 remote-endpoint = <&edp_in_vopl>;
1265                         };
1266                 };
1267         };
1268
1269         vopl_mmu: iommu@ff8f3f00 {
1270                 compatible = "rockchip,iommu";
1271                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1272                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1273                 interrupt-names = "vopl_mmu";
1274                 #iommu-cells = <0>;
1275                 status = "disabled";
1276         };
1277
1278         vopb: vop@ff900000 {
1279                 compatible = "rockchip,rk3399-vop-big";
1280                 reg = <0x0 0xff900000 0x0 0x3efc>;
1281                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1282                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1283                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1284                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1285                 reset-names = "axi", "ahb", "dclk";
1286                 iommus = <&vopb_mmu>;
1287                 status = "disabled";
1288
1289                 vopb_out: port {
1290                         #address-cells = <1>;
1291                         #size-cells = <0>;
1292
1293                         vopb_out_edp: endpoint@0 {
1294                                 reg = <0>;
1295                                 remote-endpoint = <&edp_in_vopb>;
1296                         };
1297
1298                         vopb_out_mipi: endpoint@1 {
1299                                 reg = <1>;
1300                                 remote-endpoint = <&mipi_in_vopb>;
1301                         };
1302                 };
1303         };
1304
1305         vopb_mmu: iommu@ff903f00 {
1306                 compatible = "rockchip,iommu";
1307                 reg = <0x0 0xff903f00 0x0 0x100>;
1308                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1309                 interrupt-names = "vopb_mmu";
1310                 #iommu-cells = <0>;
1311                 status = "disabled";
1312         };
1313
1314         mipi_dsi: mipi@ff960000 {
1315                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1316                 reg = <0x0 0xff960000 0x0 0x8000>;
1317                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1318                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1319                          <&cru SCLK_DPHY_TX0_CFG>;
1320                 clock-names = "ref", "pclk", "phy_cfg";
1321                 rockchip,grf = <&grf>;
1322                 #address-cells = <1>;
1323                 #size-cells = <0>;
1324                 status = "disabled";
1325
1326                 ports {
1327                         #address-cells = <1>;
1328                         #size-cells = <0>;
1329                         reg = <1>;
1330
1331                         mipi_in: port {
1332                                 #address-cells = <1>;
1333                                 #size-cells = <0>;
1334
1335                                 mipi_in_vopb: endpoint@0 {
1336                                         reg = <0>;
1337                                         remote-endpoint = <&vopb_out_mipi>;
1338                                 };
1339                                 mipi_in_vopl: endpoint@1 {
1340                                         reg = <1>;
1341                                         remote-endpoint = <&vopl_out_mipi>;
1342                                 };
1343                         };
1344                 };
1345         };
1346
1347         edp: edp@ff970000 {
1348                 compatible = "rockchip,rk3399-edp";
1349                 reg = <0x0 0xff970000 0x0 0x8000>;
1350                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1351                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1352                 clock-names = "dp", "pclk";
1353                 resets = <&cru SRST_P_EDP_CTRL>;
1354                 reset-names = "dp";
1355                 rockchip,grf = <&grf>;
1356                 status = "disabled";
1357                 pinctrl-names = "default";
1358                 pinctrl-0 = <&edp_hpd>;
1359
1360                 ports {
1361                         #address-cells = <1>;
1362                         #size-cells = <0>;
1363
1364                         edp_in: port@0 {
1365                                 reg = <0>;
1366                                 #address-cells = <1>;
1367                                 #size-cells = <0>;
1368
1369                                 edp_in_vopb: endpoint@0 {
1370                                         reg = <0>;
1371                                         remote-endpoint = <&vopb_out_edp>;
1372                                 };
1373
1374                                 edp_in_vopl: endpoint@1 {
1375                                         reg = <1>;
1376                                         remote-endpoint = <&vopl_out_edp>;
1377                                 };
1378                         };
1379                 };
1380         };
1381
1382         display_subsystem: display-subsystem {
1383                 compatible = "rockchip,display-subsystem";
1384                 ports = <&vopl_out>, <&vopb_out>;
1385                 status = "disabled";
1386         };
1387
1388         pinctrl: pinctrl {
1389                 compatible = "rockchip,rk3399-pinctrl";
1390                 rockchip,grf = <&grf>;
1391                 rockchip,pmu = <&pmugrf>;
1392                 #address-cells = <0x2>;
1393                 #size-cells = <0x2>;
1394                 ranges;
1395
1396                 gpio0: gpio0@ff720000 {
1397                         compatible = "rockchip,gpio-bank";
1398                         reg = <0x0 0xff720000 0x0 0x100>;
1399                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1400                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1401
1402                         gpio-controller;
1403                         #gpio-cells = <0x2>;
1404
1405                         interrupt-controller;
1406                         #interrupt-cells = <0x2>;
1407                 };
1408
1409                 gpio1: gpio1@ff730000 {
1410                         compatible = "rockchip,gpio-bank";
1411                         reg = <0x0 0xff730000 0x0 0x100>;
1412                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1413                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1414
1415                         gpio-controller;
1416                         #gpio-cells = <0x2>;
1417
1418                         interrupt-controller;
1419                         #interrupt-cells = <0x2>;
1420                 };
1421
1422                 gpio2: gpio2@ff780000 {
1423                         compatible = "rockchip,gpio-bank";
1424                         reg = <0x0 0xff780000 0x0 0x100>;
1425                         clocks = <&cru PCLK_GPIO2>;
1426                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1427
1428                         gpio-controller;
1429                         #gpio-cells = <0x2>;
1430
1431                         interrupt-controller;
1432                         #interrupt-cells = <0x2>;
1433                 };
1434
1435                 gpio3: gpio3@ff788000 {
1436                         compatible = "rockchip,gpio-bank";
1437                         reg = <0x0 0xff788000 0x0 0x100>;
1438                         clocks = <&cru PCLK_GPIO3>;
1439                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1440
1441                         gpio-controller;
1442                         #gpio-cells = <0x2>;
1443
1444                         interrupt-controller;
1445                         #interrupt-cells = <0x2>;
1446                 };
1447
1448                 gpio4: gpio4@ff790000 {
1449                         compatible = "rockchip,gpio-bank";
1450                         reg = <0x0 0xff790000 0x0 0x100>;
1451                         clocks = <&cru PCLK_GPIO4>;
1452                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1453
1454                         gpio-controller;
1455                         #gpio-cells = <0x2>;
1456
1457                         interrupt-controller;
1458                         #interrupt-cells = <0x2>;
1459                 };
1460
1461                 pcfg_pull_up: pcfg-pull-up {
1462                         bias-pull-up;
1463                 };
1464
1465                 pcfg_pull_down: pcfg-pull-down {
1466                         bias-pull-down;
1467                 };
1468
1469                 pcfg_pull_none: pcfg-pull-none {
1470                         bias-disable;
1471                 };
1472
1473                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1474                         bias-disable;
1475                         drive-strength = <12>;
1476                 };
1477
1478                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1479                         bias-pull-up;
1480                         drive-strength = <8>;
1481                 };
1482
1483                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1484                         bias-pull-down;
1485                         drive-strength = <4>;
1486                 };
1487
1488                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1489                         bias-pull-up;
1490                         drive-strength = <2>;
1491                 };
1492
1493                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1494                         bias-pull-down;
1495                         drive-strength = <12>;
1496                 };
1497
1498                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1499                         bias-disable;
1500                         drive-strength = <13>;
1501                 };
1502
1503                 emmc {
1504                         emmc_pwr: emmc-pwr {
1505                                 rockchip,pins =
1506                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1507                         };
1508                 };
1509
1510                 gmac {
1511                         rgmii_pins: rgmii-pins {
1512                                 rockchip,pins =
1513                                         /* mac_txclk */
1514                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1515                                         /* mac_rxclk */
1516                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1517                                         /* mac_mdio */
1518                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1519                                         /* mac_txen */
1520                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1521                                         /* mac_clk */
1522                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1523                                         /* mac_rxdv */
1524                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1525                                         /* mac_mdc */
1526                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1527                                         /* mac_rxd1 */
1528                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1529                                         /* mac_rxd0 */
1530                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1531                                         /* mac_txd1 */
1532                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1533                                         /* mac_txd0 */
1534                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1535                                         /* mac_rxd3 */
1536                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1537                                         /* mac_rxd2 */
1538                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1539                                         /* mac_txd3 */
1540                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1541                                         /* mac_txd2 */
1542                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1543                         };
1544
1545                         rmii_pins: rmii-pins {
1546                                 rockchip,pins =
1547                                         /* mac_mdio */
1548                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1549                                         /* mac_txen */
1550                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1551                                         /* mac_clk */
1552                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1553                                         /* mac_rxer */
1554                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1555                                         /* mac_rxdv */
1556                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1557                                         /* mac_mdc */
1558                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1559                                         /* mac_rxd1 */
1560                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1561                                         /* mac_rxd0 */
1562                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1563                                         /* mac_txd1 */
1564                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1565                                         /* mac_txd0 */
1566                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1567                         };
1568                 };
1569
1570                 i2c0 {
1571                         i2c0_xfer: i2c0-xfer {
1572                                 rockchip,pins =
1573                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1574                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1575                         };
1576                 };
1577
1578                 i2c1 {
1579                         i2c1_xfer: i2c1-xfer {
1580                                 rockchip,pins =
1581                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1582                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1583                         };
1584                 };
1585
1586                 i2c2 {
1587                         i2c2_xfer: i2c2-xfer {
1588                                 rockchip,pins =
1589                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1590                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1591                         };
1592                 };
1593
1594                 i2c3 {
1595                         i2c3_xfer: i2c3-xfer {
1596                                 rockchip,pins =
1597                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1598                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1599                         };
1600
1601                         i2c3_gpio: i2c3_gpio {
1602                                 rockchip,pins =
1603                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1604                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1605                         };
1606
1607                 };
1608
1609                 i2c4 {
1610                         i2c4_xfer: i2c4-xfer {
1611                                 rockchip,pins =
1612                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1613                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1614                         };
1615                 };
1616
1617                 i2c5 {
1618                         i2c5_xfer: i2c5-xfer {
1619                                 rockchip,pins =
1620                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1621                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1622                         };
1623                 };
1624
1625                 i2c6 {
1626                         i2c6_xfer: i2c6-xfer {
1627                                 rockchip,pins =
1628                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1629                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1630                         };
1631                 };
1632
1633                 i2c7 {
1634                         i2c7_xfer: i2c7-xfer {
1635                                 rockchip,pins =
1636                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1637                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1638                         };
1639                 };
1640
1641                 i2c8 {
1642                         i2c8_xfer: i2c8-xfer {
1643                                 rockchip,pins =
1644                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1645                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1646                         };
1647                 };
1648
1649                 i2s0 {
1650                         i2s0_8ch_bus: i2s0-8ch-bus {
1651                                 rockchip,pins =
1652                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1653                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1654                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1655                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1656                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1657                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1658                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1659                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1660                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1661                         };
1662                 };
1663
1664                 i2s1 {
1665                         i2s1_2ch_bus: i2s1-2ch-bus {
1666                                 rockchip,pins =
1667                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1668                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1669                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1670                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1671                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1672                         };
1673                 };
1674
1675                 sdio0 {
1676                         sdio0_bus1: sdio0-bus1 {
1677                                 rockchip,pins =
1678                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1679                         };
1680
1681                         sdio0_bus4: sdio0-bus4 {
1682                                 rockchip,pins =
1683                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1684                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1685                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1686                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1687                         };
1688
1689                         sdio0_cmd: sdio0-cmd {
1690                                 rockchip,pins =
1691                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1692                         };
1693
1694                         sdio0_clk: sdio0-clk {
1695                                 rockchip,pins =
1696                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1697                         };
1698
1699                         sdio0_cd: sdio0-cd {
1700                                 rockchip,pins =
1701                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1702                         };
1703
1704                         sdio0_pwr: sdio0-pwr {
1705                                 rockchip,pins =
1706                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1707                         };
1708
1709                         sdio0_bkpwr: sdio0-bkpwr {
1710                                 rockchip,pins =
1711                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1712                         };
1713
1714                         sdio0_wp: sdio0-wp {
1715                                 rockchip,pins =
1716                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1717                         };
1718
1719                         sdio0_int: sdio0-int {
1720                                 rockchip,pins =
1721                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1722                         };
1723                 };
1724
1725                 sdmmc {
1726                         sdmmc_bus1: sdmmc-bus1 {
1727                                 rockchip,pins =
1728                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1729                         };
1730
1731                         sdmmc_bus4: sdmmc-bus4 {
1732                                 rockchip,pins =
1733                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1734                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1735                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1736                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1737                         };
1738
1739                         sdmmc_clk: sdmmc-clk {
1740                                 rockchip,pins =
1741                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1742                         };
1743
1744                         sdmmc_cmd: sdmmc-cmd {
1745                                 rockchip,pins =
1746                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1747                         };
1748
1749                         sdmmc_cd: sdmcc-cd {
1750                                 rockchip,pins =
1751                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1752                         };
1753
1754                         sdmmc_wp: sdmmc-wp {
1755                                 rockchip,pins =
1756                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1757                         };
1758                 };
1759
1760                 spdif {
1761                         spdif_bus: spdif-bus {
1762                                 rockchip,pins =
1763                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1764                         };
1765                 };
1766
1767                 spi0 {
1768                         spi0_clk: spi0-clk {
1769                                 rockchip,pins =
1770                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1771                         };
1772                         spi0_cs0: spi0-cs0 {
1773                                 rockchip,pins =
1774                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1775                         };
1776                         spi0_cs1: spi0-cs1 {
1777                                 rockchip,pins =
1778                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1779                         };
1780                         spi0_tx: spi0-tx {
1781                                 rockchip,pins =
1782                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1783                         };
1784                         spi0_rx: spi0-rx {
1785                                 rockchip,pins =
1786                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1787                         };
1788                 };
1789
1790                 spi1 {
1791                         spi1_clk: spi1-clk {
1792                                 rockchip,pins =
1793                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1794                         };
1795                         spi1_cs0: spi1-cs0 {
1796                                 rockchip,pins =
1797                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1798                         };
1799                         spi1_rx: spi1-rx {
1800                                 rockchip,pins =
1801                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1802                         };
1803                         spi1_tx: spi1-tx {
1804                                 rockchip,pins =
1805                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1806                         };
1807                 };
1808
1809                 spi2 {
1810                         spi2_clk: spi2-clk {
1811                                 rockchip,pins =
1812                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1813                         };
1814                         spi2_cs0: spi2-cs0 {
1815                                 rockchip,pins =
1816                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1817                         };
1818                         spi2_rx: spi2-rx {
1819                                 rockchip,pins =
1820                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1821                         };
1822                         spi2_tx: spi2-tx {
1823                                 rockchip,pins =
1824                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1825                         };
1826                 };
1827
1828                 spi3 {
1829                         spi3_clk: spi3-clk {
1830                                 rockchip,pins =
1831                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1832                         };
1833                         spi3_cs0: spi3-cs0 {
1834                                 rockchip,pins =
1835                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1836                         };
1837                         spi3_rx: spi3-rx {
1838                                 rockchip,pins =
1839                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1840                         };
1841                         spi3_tx: spi3-tx {
1842                                 rockchip,pins =
1843                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1844                         };
1845                 };
1846
1847                 spi4 {
1848                         spi4_clk: spi4-clk {
1849                                 rockchip,pins =
1850                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1851                         };
1852                         spi4_cs0: spi4-cs0 {
1853                                 rockchip,pins =
1854                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1855                         };
1856                         spi4_rx: spi4-rx {
1857                                 rockchip,pins =
1858                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1859                         };
1860                         spi4_tx: spi4-tx {
1861                                 rockchip,pins =
1862                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1863                         };
1864                 };
1865
1866                 spi5 {
1867                         spi5_clk: spi5-clk {
1868                                 rockchip,pins =
1869                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1870                         };
1871                         spi5_cs0: spi5-cs0 {
1872                                 rockchip,pins =
1873                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1874                         };
1875                         spi5_rx: spi5-rx {
1876                                 rockchip,pins =
1877                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1878                         };
1879                         spi5_tx: spi5-tx {
1880                                 rockchip,pins =
1881                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1882                         };
1883                 };
1884
1885                 tsadc {
1886                         otp_gpio: otp-gpio {
1887                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1888                         };
1889
1890                         otp_out: otp-out {
1891                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1892                         };
1893                 };
1894
1895                 uart0 {
1896                         uart0_xfer: uart0-xfer {
1897                                 rockchip,pins =
1898                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1899                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1900                         };
1901
1902                         uart0_cts: uart0-cts {
1903                                 rockchip,pins =
1904                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1905                         };
1906
1907                         uart0_rts: uart0-rts {
1908                                 rockchip,pins =
1909                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1910                         };
1911                 };
1912
1913                 uart1 {
1914                         uart1_xfer: uart1-xfer {
1915                                 rockchip,pins =
1916                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1917                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1918                         };
1919                 };
1920
1921                 uart2a {
1922                         uart2a_xfer: uart2a-xfer {
1923                                 rockchip,pins =
1924                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1925                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1926                         };
1927                 };
1928
1929                 uart2b {
1930                         uart2b_xfer: uart2b-xfer {
1931                                 rockchip,pins =
1932                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1933                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1934                         };
1935                 };
1936
1937                 uart2c {
1938                         uart2c_xfer: uart2c-xfer {
1939                                 rockchip,pins =
1940                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1941                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1942                         };
1943                 };
1944
1945                 uart3 {
1946                         uart3_xfer: uart3-xfer {
1947                                 rockchip,pins =
1948                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1949                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1950                         };
1951
1952                         uart3_cts: uart3-cts {
1953                                 rockchip,pins =
1954                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1955                         };
1956
1957                         uart3_rts: uart3-rts {
1958                                 rockchip,pins =
1959                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1960                         };
1961                 };
1962
1963                 uart4 {
1964                         uart4_xfer: uart4-xfer {
1965                                 rockchip,pins =
1966                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1967                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1968                         };
1969                 };
1970
1971                 uarthdcp {
1972                         uarthdcp_xfer: uarthdcp-xfer {
1973                                 rockchip,pins =
1974                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1975                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1976                         };
1977                 };
1978
1979                 pwm0 {
1980                         pwm0_pin: pwm0-pin {
1981                                 rockchip,pins =
1982                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1983                         };
1984
1985                         vop0_pwm_pin: vop0-pwm-pin {
1986                                 rockchip,pins =
1987                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1988                         };
1989                 };
1990
1991                 pwm1 {
1992                         pwm1_pin: pwm1-pin {
1993                                 rockchip,pins =
1994                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1995                         };
1996
1997                         vop1_pwm_pin: vop1-pwm-pin {
1998                                 rockchip,pins =
1999                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2000                         };
2001                 };
2002
2003                 pwm2 {
2004                         pwm2_pin: pwm2-pin {
2005                                 rockchip,pins =
2006                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2007                         };
2008                 };
2009
2010                 pwm3a {
2011                         pwm3a_pin: pwm3a-pin {
2012                                 rockchip,pins =
2013                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2014                         };
2015                 };
2016
2017                 pwm3b {
2018                         pwm3b_pin: pwm3b-pin {
2019                                 rockchip,pins =
2020                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2021                         };
2022                 };
2023
2024                 edp {
2025                         edp_hpd: edp-hpd {
2026                                 rockchip,pins =
2027                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2028                         };
2029                 };
2030
2031                 hdmi {
2032                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2033                                 rockchip,pins =
2034                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2035                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2036                         };
2037
2038                         hdmi_cec: hdmi-cec {
2039                                 rockchip,pins =
2040                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2041                         };
2042                 };
2043
2044                 pcie {
2045                         pcie_clkreqn: pci-clkreqn {
2046                                 rockchip,pins =
2047                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2048                         };
2049
2050                         pcie_clkreqnb: pci-clkreqnb {
2051                                 rockchip,pins =
2052                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2053                         };
2054                 };
2055         };
2056 };