2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/clock/rk3399-cru.h>
43 #include <dt-bindings/gpio/gpio.h>
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/pinctrl/rockchip.h>
49 compatible = "rockchip,rk3399";
50 interrupt-parent = <&gic>;
93 compatible = "arm,cortex-a53", "arm,armv8";
99 compatible = "arm,cortex-a53", "arm,armv8";
105 compatible = "arm,cortex-a53", "arm,armv8";
111 compatible = "arm,cortex-a53", "arm,armv8";
117 compatible = "arm,cortex-a72", "arm,armv8";
123 compatible = "arm,cortex-a72", "arm,armv8";
129 compatible = "arm,armv8-timer";
130 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
137 compatible = "fixed-clock";
139 clock-frequency = <24000000>;
140 clock-output-names = "xin24m";
143 gic: interrupt-controller@fee00000 {
144 compatible = "arm,gic-v3";
145 #interrupt-cells = <3>;
146 #address-cells = <2>;
149 interrupt-controller;
151 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
152 <0x0 0xfef00000 0 0xc0000>, /* GICR */
153 <0x0 0xfff00000 0 0x10000>, /* GICC */
154 <0x0 0xfff10000 0 0x10000>, /* GICH */
155 <0x0 0xfff20000 0 0x10000>; /* GICV */
156 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
157 its: interrupt-controller@fee20000 {
158 compatible = "arm,gic-v3-its";
160 reg = <0x0 0xfee20000 0x0 0x20000>;
165 compatible = "arm,amba-bus";
166 #address-cells = <2>;
170 dmac_bus: dma-controller@ff6d0000 {
171 compatible = "arm,pl330", "arm,primecell";
172 reg = <0x0 0xff6d0000 0x0 0x4000>;
173 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&cru ACLK_DMAC0_PERILP>;
177 clock-names = "apb_pclk";
180 dmac_peri: dma-controller@ff6e0000 {
181 compatible = "arm,pl330", "arm,primecell";
182 reg = <0x0 0xff6e0000 0x0 0x4000>;
183 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&cru ACLK_DMAC1_PERILP>;
187 clock-names = "apb_pclk";
191 uart0: serial@ff180000 {
192 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
193 reg = <0x0 0xff180000 0x0 0x100>;
194 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
195 clock-names = "baudclk", "apb_pclk";
196 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
202 uart1: serial@ff190000 {
203 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
204 reg = <0x0 0xff190000 0x0 0x100>;
205 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
206 clock-names = "baudclk", "apb_pclk";
207 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
213 uart2: serial@ff1a0000 {
214 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
215 reg = <0x0 0xff1a0000 0x0 0x100>;
216 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
217 clock-names = "baudclk", "apb_pclk";
218 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
224 uart3: serial@ff1b0000 {
225 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
226 reg = <0x0 0xff1b0000 0x0 0x100>;
227 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
228 clock-names = "baudclk", "apb_pclk";
229 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
236 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
237 reg = <0x0 0xff110000 0x0 0x1000>;
238 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
239 clock-names = "spiclk", "apb_pclk";
240 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
243 #address-cells = <1>;
249 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
250 reg = <0x0 0xff120000 0x0 0x1000>;
251 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
252 clock-names = "spiclk", "apb_pclk";
253 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
256 #address-cells = <1>;
262 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
263 reg = <0x0 0xff130000 0x0 0x1000>;
264 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
265 clock-names = "spiclk", "apb_pclk";
266 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
269 #address-cells = <1>;
275 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
276 reg = <0x0 0xff120000 0x0 0x1000>;
277 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
278 clock-names = "spiclk", "apb_pclk";
279 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
282 #address-cells = <1>;
288 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
289 reg = <0x0 0xff130000 0x0 0x1000>;
290 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
291 clock-names = "spiclk", "apb_pclk";
292 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
295 #address-cells = <1>;
300 pmugrf: syscon@ff320000 {
301 compatible = "rockchip,rk3399-pmugrf", "syscon";
302 reg = <0x0 0xff320000 0x0 0x1000>;
306 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
307 reg = <0x0 0xff110000 0x0 0x1000>;
308 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
309 clock-names = "spiclk", "apb_pclk";
310 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
313 #address-cells = <1>;
318 uart4: serial@ff370000 {
319 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
320 reg = <0x0 0xff370000 0x0 0x100>;
321 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
322 clock-names = "baudclk", "apb_pclk";
323 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
329 pmucru: pmu-clock-controller@ff750000 {
330 compatible = "rockchip,rk3399-pmucru";
331 reg = <0x0 0xff750000 0x0 0x1000>;
332 rockchip,grf = <&pmugrf>;
337 cru: clock-controller@ff760000 {
338 compatible = "rockchip,rk3399-cru";
339 reg = <0x0 0xff760000 0x0 0x1000>;
340 rockchip,grf = <&grf>;
345 grf: syscon@ff770000 {
346 compatible = "rockchip,rk3399-grf", "syscon";
347 reg = <0x0 0xff770000 0x0 0x10000>;
351 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
352 reg = <0x0 0xff880000 0x0 0x1000>;
353 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
356 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
357 dma-names = "tx", "rx";
358 clock-names = "i2s_hclk", "i2s_clk";
359 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
364 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
365 reg = <0x0 0xff890000 0x0 0x1000>;
366 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
369 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
370 dma-names = "tx", "rx";
371 clock-names = "i2s_hclk", "i2s_clk";
372 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
377 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
378 reg = <0x0 0xff8a0000 0x0 0x1000>;
379 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
380 #address-cells = <1>;
382 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
383 dma-names = "tx", "rx";
384 clock-names = "i2s_hclk", "i2s_clk";
385 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
390 compatible = "rockchip,rk3399-pinctrl";
391 rockchip,grf = <&grf>;
392 rockchip,pmu = <&pmugrf>;
393 #address-cells = <0x2>;
397 gpio0: gpio0@ff720000 {
398 compatible = "rockchip,gpio-bank";
399 reg = <0x0 0xff720000 0x0 0x100>;
401 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
406 interrupt-controller;
407 #interrupt-cells = <0x2>;
410 gpio1: gpio1@ff730000 {
411 compatible = "rockchip,gpio-bank";
412 reg = <0x0 0xff730000 0x0 0x100>;
414 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
419 interrupt-controller;
420 #interrupt-cells = <0x2>;
423 gpio2: gpio2@ff780000 {
424 compatible = "rockchip,gpio-bank";
425 reg = <0x0 0xff780000 0x0 0x100>;
427 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
432 interrupt-controller;
433 #interrupt-cells = <0x2>;
436 gpio3: gpio3@ff788000 {
437 compatible = "rockchip,gpio-bank";
438 reg = <0x0 0xff788000 0x0 0x100>;
440 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-controller;
446 #interrupt-cells = <0x2>;
449 gpio4: gpio4@ff790000 {
450 compatible = "rockchip,gpio-bank";
451 reg = <0x0 0xff790000 0x0 0x100>;
453 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-controller;
459 #interrupt-cells = <0x2>;
462 pcfg_pull_up: pcfg-pull-up {
466 pcfg_pull_down: pcfg-pull-down {
470 pcfg_pull_none: pcfg-pull-none {
474 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
476 drive-strength = <12>;
479 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
481 drive-strength = <8>;
484 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
486 drive-strength = <4>;
489 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
491 drive-strength = <2>;
494 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
496 drive-strength = <12>;
502 <0 5 RK_FUNC_1 &pcfg_pull_up>;
507 rgmii_pins: rgmii-pins {
509 <3 11 RK_FUNC_1 &pcfg_pull_none>,
510 <3 13 RK_FUNC_1 &pcfg_pull_none>,
511 <3 8 RK_FUNC_1 &pcfg_pull_none>,
512 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
513 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
514 <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
515 <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
516 <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
517 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
518 <3 6 RK_FUNC_1 &pcfg_pull_none>,
519 <3 7 RK_FUNC_1 &pcfg_pull_none>,
520 <3 2 RK_FUNC_1 &pcfg_pull_none>,
521 <3 3 RK_FUNC_1 &pcfg_pull_none>,
522 <3 14 RK_FUNC_1 &pcfg_pull_none>,
523 <3 9 RK_FUNC_1 &pcfg_pull_none>;
526 rmii_pins: rmii-pins {
528 <3 11 RK_FUNC_1 &pcfg_pull_none>,
529 <3 13 RK_FUNC_1 &pcfg_pull_none>,
530 <3 8 RK_FUNC_1 &pcfg_pull_none>,
531 <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
532 <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
533 <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
534 <3 6 RK_FUNC_1 &pcfg_pull_none>,
535 <3 7 RK_FUNC_1 &pcfg_pull_none>,
536 <3 9 RK_FUNC_1 &pcfg_pull_none>,
537 <3 10 RK_FUNC_1 &pcfg_pull_none>;
542 i2c0_xfer: i2c0-xfer {
544 <1 15 RK_FUNC_2 &pcfg_pull_none>,
545 <1 16 RK_FUNC_2 &pcfg_pull_none>;
550 i2c1_xfer: i2c1-xfer {
552 <4 2 RK_FUNC_1 &pcfg_pull_none>,
553 <4 1 RK_FUNC_1 &pcfg_pull_none>;
558 i2c2_xfer: i2c2-xfer {
560 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
561 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
566 i2c3_xfer: i2c3-xfer {
568 <4 17 RK_FUNC_1 &pcfg_pull_none>,
569 <4 16 RK_FUNC_1 &pcfg_pull_none>;
574 i2c4_xfer: i2c4-xfer {
576 <1 12 RK_FUNC_1 &pcfg_pull_none>,
577 <1 11 RK_FUNC_1 &pcfg_pull_none>;
582 i2c5_xfer: i2c5-xfer {
584 <3 11 RK_FUNC_2 &pcfg_pull_none>,
585 <3 10 RK_FUNC_2 &pcfg_pull_none>;
590 i2c6_xfer: i2c6-xfer {
592 <2 10 RK_FUNC_2 &pcfg_pull_none>,
593 <2 9 RK_FUNC_2 &pcfg_pull_none>;
598 i2c7_xfer: i2c7-xfer {
600 <2 8 RK_FUNC_2 &pcfg_pull_none>,
601 <2 7 RK_FUNC_2 &pcfg_pull_none>;
606 i2c8_xfer: i2c8-xfer {
608 <1 21 RK_FUNC_1 &pcfg_pull_none>,
609 <1 20 RK_FUNC_1 &pcfg_pull_none>;
614 i2s0_8ch_bus: i2s0-8ch-bus {
616 <3 24 RK_FUNC_1 &pcfg_pull_none>,
617 <3 25 RK_FUNC_1 &pcfg_pull_none>,
618 <3 26 RK_FUNC_1 &pcfg_pull_none>,
619 <3 27 RK_FUNC_1 &pcfg_pull_none>,
620 <3 28 RK_FUNC_1 &pcfg_pull_none>,
621 <3 29 RK_FUNC_1 &pcfg_pull_none>,
622 <3 30 RK_FUNC_1 &pcfg_pull_none>,
623 <3 31 RK_FUNC_1 &pcfg_pull_none>,
624 <4 0 RK_FUNC_1 &pcfg_pull_none>;
629 i2s1_2ch_bus: i2s1-2ch-bus {
631 <4 3 RK_FUNC_1 &pcfg_pull_none>,
632 <4 4 RK_FUNC_1 &pcfg_pull_none>,
633 <4 5 RK_FUNC_1 &pcfg_pull_none>,
634 <4 6 RK_FUNC_1 &pcfg_pull_none>,
635 <4 7 RK_FUNC_1 &pcfg_pull_none>;
640 sdio0_bus1: sdio0-bus1 {
642 <2 20 RK_FUNC_1 &pcfg_pull_up>;
645 sdio0_bus4: sdio0-bus4 {
647 <2 20 RK_FUNC_1 &pcfg_pull_up>,
648 <2 21 RK_FUNC_1 &pcfg_pull_up>,
649 <2 22 RK_FUNC_1 &pcfg_pull_up>,
650 <2 23 RK_FUNC_1 &pcfg_pull_up>;
653 sdio0_cmd: sdio0-cmd {
655 <2 24 RK_FUNC_1 &pcfg_pull_up>;
658 sdio0_clk: sdio0-clk {
660 <2 25 RK_FUNC_1 &pcfg_pull_none>;
665 <2 26 RK_FUNC_1 &pcfg_pull_up>;
668 sdio0_pwr: sdio0-pwr {
670 <2 27 RK_FUNC_1 &pcfg_pull_up>;
673 sdio0_bkpwr: sdio0-bkpwr {
675 <2 28 RK_FUNC_1 &pcfg_pull_up>;
680 <0 3 RK_FUNC_1 &pcfg_pull_up>;
683 sdio0_int: sdio0-int {
685 <0 4 RK_FUNC_1 &pcfg_pull_up>;
690 sdmmc_bus1: sdmmc-bus1 {
692 <4 8 RK_FUNC_1 &pcfg_pull_up>;
695 sdmmc_bus4: sdmmc-bus4 {
697 <4 8 RK_FUNC_1 &pcfg_pull_up>,
698 <4 9 RK_FUNC_1 &pcfg_pull_up>,
699 <4 10 RK_FUNC_1 &pcfg_pull_up>,
700 <4 11 RK_FUNC_1 &pcfg_pull_up>;
703 sdmmc_clk: sdmmc-clk {
705 <4 12 RK_FUNC_1 &pcfg_pull_none>;
708 sdmmc_cmd: sdmmc-cmd {
710 <4 13 RK_FUNC_1 &pcfg_pull_up>;
715 <0 7 RK_FUNC_1 &pcfg_pull_up>;
720 <0 8 RK_FUNC_1 &pcfg_pull_up>;
727 <3 6 RK_FUNC_2 &pcfg_pull_up>;
731 <3 7 RK_FUNC_2 &pcfg_pull_up>;
735 <3 8 RK_FUNC_2 &pcfg_pull_up>;
739 <3 5 RK_FUNC_2 &pcfg_pull_up>;
743 <3 4 RK_FUNC_2 &pcfg_pull_up>;
750 <1 9 RK_FUNC_2 &pcfg_pull_up>;
754 <1 10 RK_FUNC_2 &pcfg_pull_up>;
758 <1 7 RK_FUNC_2 &pcfg_pull_up>;
762 <1 8 RK_FUNC_2 &pcfg_pull_up>;
769 <2 11 RK_FUNC_1 &pcfg_pull_up>;
773 <2 12 RK_FUNC_1 &pcfg_pull_up>;
777 <2 9 RK_FUNC_1 &pcfg_pull_up>;
781 <2 10 RK_FUNC_1 &pcfg_pull_up>;
788 <1 17 RK_FUNC_1 &pcfg_pull_up>;
792 <1 18 RK_FUNC_1 &pcfg_pull_up>;
796 <1 15 RK_FUNC_1 &pcfg_pull_up>;
800 <1 16 RK_FUNC_1 &pcfg_pull_up>;
807 <3 2 RK_FUNC_2 &pcfg_pull_up>;
811 <3 3 RK_FUNC_2 &pcfg_pull_up>;
815 <3 0 RK_FUNC_2 &pcfg_pull_up>;
819 <3 1 RK_FUNC_2 &pcfg_pull_up>;
826 <2 22 RK_FUNC_2 &pcfg_pull_up>;
830 <2 23 RK_FUNC_2 &pcfg_pull_up>;
834 <2 20 RK_FUNC_2 &pcfg_pull_up>;
838 <2 21 RK_FUNC_2 &pcfg_pull_up>;
843 uart0_xfer: uart0-xfer {
845 <2 16 RK_FUNC_1 &pcfg_pull_up>,
846 <2 17 RK_FUNC_1 &pcfg_pull_none>;
849 uart0_cts: uart0-cts {
851 <2 18 RK_FUNC_1 &pcfg_pull_none>;
854 uart0_rts: uart0-rts {
856 <2 19 RK_FUNC_1 &pcfg_pull_none>;
861 uart1_xfer: uart1-xfer {
863 <3 12 RK_FUNC_2 &pcfg_pull_up>,
864 <3 13 RK_FUNC_2 &pcfg_pull_none>;
869 uart2a_xfer: uart2a-xfer {
871 <4 8 RK_FUNC_2 &pcfg_pull_up>,
872 <4 9 RK_FUNC_2 &pcfg_pull_none>;
877 uart2b_xfer: uart2b-xfer {
879 <4 16 RK_FUNC_2 &pcfg_pull_up>,
880 <4 17 RK_FUNC_2 &pcfg_pull_none>;
885 uart2c_xfer: uart2c-xfer {
887 <4 19 RK_FUNC_1 &pcfg_pull_up>,
888 <4 20 RK_FUNC_1 &pcfg_pull_none>;
893 uart3_xfer: uart3-xfer {
895 <3 14 RK_FUNC_2 &pcfg_pull_up>,
896 <3 15 RK_FUNC_2 &pcfg_pull_none>;
899 uart3_cts: uart3-cts {
901 <3 18 RK_FUNC_2 &pcfg_pull_none>;
904 uart3_rts: uart3-rts {
906 <3 19 RK_FUNC_2 &pcfg_pull_none>;
911 uart4_xfer: uart4-xfer {
913 <1 7 RK_FUNC_1 &pcfg_pull_up>,
914 <1 8 RK_FUNC_1 &pcfg_pull_none>;
919 uarthdcp_xfer: uarthdcp-xfer {
921 <4 21 RK_FUNC_2 &pcfg_pull_up>,
922 <4 22 RK_FUNC_2 &pcfg_pull_none>;
929 <4 18 RK_FUNC_1 &pcfg_pull_none>;
932 vop0_pwm_pin: vop0-pwm-pin {
934 <4 18 RK_FUNC_2 &pcfg_pull_none>;
941 <4 22 RK_FUNC_1 &pcfg_pull_none>;
944 vop1_pwm_pin: vop1-pwm-pin {
946 <4 18 RK_FUNC_3 &pcfg_pull_none>;