arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71         };
  72
  73         cpus {
  74                 #address-cells = <2>;
  75                 #size-cells = <0>;
  76
  77                 cpu-map {
  78                         cluster0 {
  79                                 core0 {
  80                                         cpu = <&cpu_l0>;
  81                                 };
  82                                 core1 {
  83                                         cpu = <&cpu_l1>;
  84                                 };
  85                                 core2 {
  86                                         cpu = <&cpu_l2>;
  87                                 };
  88                                 core3 {
  89                                         cpu = <&cpu_l3>;
  90                                 };
  91                         };
  92
  93                         cluster1 {
  94                                 core0 {
  95                                         cpu = <&cpu_b0>;
  96                                 };
  97                                 core1 {
  98                                         cpu = <&cpu_b1>;
  99                                 };
 100                         };
 101                 };
 102
 103                 cpu_l0: cpu@0 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a53", "arm,armv8";
 106                         reg = <0x0 0x0>;
 107
 108                         #cooling-cells = <2>; /* min followed by max */
 109                         clocks = <&cru ARMCLKL>;
 110                         operating-points-v2 = <&cluster0_opp>;
 111                 };
 112
 113                 cpu_l1: cpu@1 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x1>;
 117                         clocks = <&cru ARMCLKL>;
 118                         operating-points-v2 = <&cluster0_opp>;
 119                 };
 120
 121                 cpu_l2: cpu@2 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a53", "arm,armv8";
 124                         reg = <0x0 0x2>;
 125                         clocks = <&cru ARMCLKL>;
 126                         operating-points-v2 = <&cluster0_opp>;
 127                 };
 128
 129                 cpu_l3: cpu@3 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a53", "arm,armv8";
 132                         reg = <0x0 0x3>;
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_b0: cpu@100 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a72", "arm,armv8";
 140                         reg = <0x0 0x100>;
 141
 142                         #cooling-cells = <2>; /* min followed by max */
 143                         clocks = <&cru ARMCLKB>;
 144                         operating-points-v2 = <&cluster1_opp>;
 145                 };
 146
 147                 cpu_b1: cpu@101 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x101>;
 151                         clocks = <&cru ARMCLKB>;
 152                         operating-points-v2 = <&cluster1_opp>;
 153                 };
 154         };
 155
 156         cluster0_opp: opp_table0 {
 157                 compatible = "operating-points-v2";
 158                 opp-shared;
 159
 160                 opp00 {
 161                         opp-hz = /bits/ 64 <408000000>;
 162                         opp-microvolt = <1000000>;
 163                         clock-latency-ns = <40000>;
 164                 };
 165                 opp01 {
 166                         opp-hz = /bits/ 64 <600000000>;
 167                         opp-microvolt = <1000000>;
 168                 };
 169                 opp02 {
 170                         opp-hz = /bits/ 64 <816000000>;
 171                         opp-microvolt = <1000000>;
 172                 };
 173                 opp03 {
 174                         opp-hz = /bits/ 64 <1008000000>;
 175                         opp-microvolt = <1000000>;
 176                 };
 177         };
 178
 179         cluster1_opp: opp_table1 {
 180                 compatible = "operating-points-v2";
 181                 opp-shared;
 182
 183                 opp00 {
 184                         opp-hz = /bits/ 64 <408000000>;
 185                         opp-microvolt = <1000000>;
 186                         clock-latency-ns = <40000>;
 187                 };
 188                 opp01 {
 189                         opp-hz = /bits/ 64 <600000000>;
 190                         opp-microvolt = <1000000>;
 191                 };
 192                 opp02 {
 193                         opp-hz = /bits/ 64 <816000000>;
 194                         opp-microvolt = <1000000>;
 195                 };
 196                 opp03 {
 197                         opp-hz = /bits/ 64 <1008000000>;
 198                         opp-microvolt = <1000000>;
 199                 };
 200                 opp04 {
 201                         opp-hz = /bits/ 64 <1200000000>;
 202                         opp-microvolt = <1000000>;
 203                 };
 204         };
 205
 206         timer {
 207                 compatible = "arm,armv8-timer";
 208                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 212         };
 213
 214         xin24m: xin24m {
 215                 compatible = "fixed-clock";
 216                 #clock-cells = <0>;
 217                 clock-frequency = <24000000>;
 218                 clock-output-names = "xin24m";
 219         };
 220
 221         amba {
 222                 compatible = "arm,amba-bus";
 223                 #address-cells = <2>;
 224                 #size-cells = <2>;
 225                 ranges;
 226
 227                 dmac_bus: dma-controller@ff6d0000 {
 228                         compatible = "arm,pl330", "arm,primecell";
 229                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 230                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 232                         #dma-cells = <1>;
 233                         clocks = <&cru ACLK_DMAC0_PERILP>;
 234                         clock-names = "apb_pclk";
 235                 };
 236
 237                 dmac_peri: dma-controller@ff6e0000 {
 238                         compatible = "arm,pl330", "arm,primecell";
 239                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 240                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 242                         #dma-cells = <1>;
 243                         clocks = <&cru ACLK_DMAC1_PERILP>;
 244                         clock-names = "apb_pclk";
 245                 };
 246         };
 247
 248         emmc_phy: phy {
 249                 compatible = "rockchip,rk3399-emmc-phy";
 250                 reg-offset = <0xf780>;
 251                 #phy-cells = <0>;
 252                 rockchip,grf = <&grf>;
 253                 status = "disabled";
 254         };
 255
 256         sdio0: dwmmc@fe310000 {
 257                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 258                 reg = <0x0 0xfe310000 0x0 0x4000>;
 259                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 260                 clock-freq-min-max = <400000 150000000>;
 261                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 262                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 263                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 264                 fifo-depth = <0x100>;
 265                 status = "disabled";
 266         };
 267
 268         sdmmc: dwmmc@fe320000 {
 269                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 270                 reg = <0x0 0xfe320000 0x0 0x4000>;
 271                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 272                 clock-freq-min-max = <400000 150000000>;
 273                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 274                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 275                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 276                 fifo-depth = <0x100>;
 277                 status = "disabled";
 278         };
 279
 280         sdhci: sdhci@fe330000 {
 281                 compatible = "arasan,sdhci-5.1";
 282                 reg = <0x0 0xfe330000 0x0 0x10000>;
 283                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 284                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 285                 clock-names = "clk_xin", "clk_ahb";
 286                 phys = <&emmc_phy>;
 287                 phy-names = "phy_arasan";
 288                 status = "disabled";
 289         };
 290
 291         usb_host0_echi: usb@fe380000 {
 292                 compatible = "generic-ehci";
 293                 reg = <0x0 0xfe380000 0x0 0x20000>;
 294                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&cru HCLK_HOST0>;
 296                 clock-names = "hclk_host0";
 297                 status = "disabled";
 298         };
 299
 300         usb_host0_ohci: usb@fe3a0000 {
 301                 compatible = "generic-ohci";
 302                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 303                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&cru HCLK_HOST0>;
 305                 clock-names = "hclk_host0";
 306                 status = "disabled";
 307         };
 308
 309         usb_host1_echi: usb@fe3c0000 {
 310                 compatible = "generic-ehci";
 311                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 312                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&cru HCLK_HOST1>;
 314                 clock-names = "hclk_host1";
 315                 status = "disabled";
 316         };
 317
 318         usb_host1_ohci: usb@fe3e0000 {
 319                 compatible = "generic-ohci";
 320                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 321                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 322                 clocks = <&cru HCLK_HOST1>;
 323                 clock-names = "hclk_host1";
 324                 status = "disabled";
 325         };
 326
 327         gic: interrupt-controller@fee00000 {
 328                 compatible = "arm,gic-v3";
 329                 #interrupt-cells = <3>;
 330                 #address-cells = <2>;
 331                 #size-cells = <2>;
 332                 ranges;
 333                 interrupt-controller;
 334
 335                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 336                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 337                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 338                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 339                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 340                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 341                 its: interrupt-controller@fee20000 {
 342                         compatible = "arm,gic-v3-its";
 343                         msi-controller;
 344                         reg = <0x0 0xfee20000 0x0 0x20000>;
 345                 };
 346         };
 347
 348         saradc: saradc@ff100000 {
 349                 compatible = "rockchip,rk3399-saradc";
 350                 reg = <0x0 0xff100000 0x0 0x100>;
 351                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 352                 #io-channel-cells = <1>;
 353                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 354                 clock-names = "saradc", "apb_pclk";
 355                 status = "disabled";
 356         };
 357
 358         i2c0: i2c@ff3c0000 {
 359                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 360                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 361                 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
 362                 clock-names = "i2c", "i2c_sclk";
 363                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&i2c0_xfer>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 status = "disabled";
 369         };
 370
 371         i2c1: i2c@ff110000 {
 372                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 373                 reg = <0x0 0xff110000 0x0 0x1000>;
 374                 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
 375                 clock-names = "i2c", "i2c_sclk";
 376                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&i2c1_xfer>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 status = "disabled";
 382         };
 383
 384         i2c2: i2c@ff120000 {
 385                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 386                 reg = <0x0 0xff120000 0x0 0x1000>;
 387                 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
 388                 clock-names = "i2c", "i2c_sclk";
 389                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&i2c2_xfer>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 status = "disabled";
 395         };
 396
 397         i2c3: i2c@ff130000 {
 398                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 399                 reg = <0x0 0xff130000 0x0 0x1000>;
 400                 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
 401                 clock-names = "i2c", "i2c_sclk";
 402                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&i2c3_xfer>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 status = "disabled";
 408         };
 409
 410         i2c5: i2c@ff140000 {
 411                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 412                 reg = <0x0 0xff140000 0x0 0x1000>;
 413                 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
 414                 clock-names = "i2c", "i2c_sclk";
 415                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&i2c5_xfer>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 status = "disabled";
 421         };
 422
 423         i2c6: i2c@ff150000 {
 424                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 425                 reg = <0x0 0xff150000 0x0 0x1000>;
 426                 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
 427                 clock-names = "i2c", "i2c_sclk";
 428                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&i2c6_xfer>;
 431                 #address-cells = <1>;
 432                 #size-cells = <0>;
 433                 status = "disabled";
 434         };
 435
 436         i2c7: i2c@ff160000 {
 437                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 438                 reg = <0x0 0xff160000 0x0 0x1000>;
 439                 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
 440                 clock-names = "i2c", "i2c_sclk";
 441                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&i2c7_xfer>;
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 status = "disabled";
 447         };
 448
 449         uart0: serial@ff180000 {
 450                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 451                 reg = <0x0 0xff180000 0x0 0x100>;
 452                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 453                 clock-names = "baudclk", "apb_pclk";
 454                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 455                 reg-shift = <2>;
 456                 reg-io-width = <4>;
 457                 status = "disabled";
 458         };
 459
 460         uart1: serial@ff190000 {
 461                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 462                 reg = <0x0 0xff190000 0x0 0x100>;
 463                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 464                 clock-names = "baudclk", "apb_pclk";
 465                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 466                 reg-shift = <2>;
 467                 reg-io-width = <4>;
 468                 status = "disabled";
 469         };
 470
 471         uart2: serial@ff1a0000 {
 472                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 473                 reg = <0x0 0xff1a0000 0x0 0x100>;
 474                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 475                 clock-names = "baudclk", "apb_pclk";
 476                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 477                 reg-shift = <2>;
 478                 reg-io-width = <4>;
 479                 status = "disabled";
 480         };
 481
 482         uart3: serial@ff1b0000 {
 483                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 484                 reg = <0x0 0xff1b0000 0x0 0x100>;
 485                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 486                 clock-names = "baudclk", "apb_pclk";
 487                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 488                 reg-shift = <2>;
 489                 reg-io-width = <4>;
 490                 status = "disabled";
 491         };
 492
 493         spi0: spi@ff1c0000 {
 494                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 495                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 496                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 497                 clock-names = "spiclk", "apb_pclk";
 498                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503                 status = "disabled";
 504         };
 505
 506         spi1: spi@ff1d0000 {
 507                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 508                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 509                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 510                 clock-names = "spiclk", "apb_pclk";
 511                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 status = "disabled";
 517         };
 518
 519         spi2: spi@ff1e0000 {
 520                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 521                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 522                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 523                 clock-names = "spiclk", "apb_pclk";
 524                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 525                 pinctrl-names = "default";
 526                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 status = "disabled";
 530         };
 531
 532         spi4: spi@ff1f0000 {
 533                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 534                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 535                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 536                 clock-names = "spiclk", "apb_pclk";
 537                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 status = "disabled";
 543         };
 544
 545         spi5: spi@ff200000 {
 546                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 547                 reg = <0x0 0xff200000 0x0 0x1000>;
 548                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 549                 clock-names = "spiclk", "apb_pclk";
 550                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         thermal-zones {
 559                 #include "rk3368-thermal.dtsi"
 560         };
 561
 562         tsadc: tsadc@ff260000 {
 563                 compatible = "rockchip,rk3399-tsadc";
 564                 reg = <0x0 0xff260000 0x0 0x100>;
 565                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 566                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 567                 clock-names = "tsadc", "apb_pclk";
 568                 resets = <&cru SRST_TSADC>;
 569                 reset-names = "tsadc-apb";
 570                 pinctrl-names = "init", "default", "sleep";
 571                 pinctrl-0 = <&otp_gpio>;
 572                 pinctrl-1 = <&otp_out>;
 573                 pinctrl-2 = <&otp_gpio>;
 574                 #thermal-sensor-cells = <1>;
 575                 rockchip,hw-tshut-temp = <95000>;
 576                 status = "disabled";
 577         };
 578
 579         pmu: power-management@ff31000 {
 580                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 581                 reg = <0x0 0xff310000 0x0 0x1000>;
 582
 583                 power: power-controller {
 584                         status = "disabled";
 585                         compatible = "rockchip,rk3399-power-controller";
 586                         #power-domain-cells = <1>;
 587                         #address-cells = <1>;
 588                         #size-cells = <0>;
 589
 590                         pd_center {
 591                                 reg = <RK3399_PD_CENTER>;
 592                                 #address-cells = <1>;
 593                                 #size-cells = <0>;
 594
 595                                 pd_vdu {
 596                                         reg = <RK3399_PD_VDU>;
 597                                 };
 598                                 pd_vcodec {
 599                                         reg = <RK3399_PD_VCODEC>;
 600                                 };
 601                                 pd_iep {
 602                                         reg = <RK3399_PD_IEP>;
 603                                 };
 604                                 pd_rga {
 605                                         reg = <RK3399_PD_RGA>;
 606                                 };
 607                         };
 608                         pd_vio {
 609                                 reg = <RK3399_PD_VIO>;
 610                                 #address-cells = <1>;
 611                                 #size-cells = <0>;
 612
 613                                 pd_isp0 {
 614                                         reg = <RK3399_PD_ISP0>;
 615                                 };
 616                                 pd_isp1 {
 617                                         reg = <RK3399_PD_ISP1>;
 618                                 };
 619                                 pd_hdcp {
 620                                         reg = <RK3399_PD_HDCP>;
 621                                 };
 622                                 pd_vo {
 623                                         reg = <RK3399_PD_VO>;
 624                                         #address-cells = <1>;
 625                                         #size-cells = <0>;
 626
 627                                         pd_vopb {
 628                                                 reg = <RK3399_PD_VOPB>;
 629                                         };
 630                                         pd_vopl {
 631                                                 reg = <RK3399_PD_VOPL>;
 632                                         };
 633                                 };
 634                         };
 635                         pd_gpu {
 636                                 reg = <RK3399_PD_GPU>;
 637                         };
 638                 };
 639         };
 640
 641         pmugrf: syscon@ff320000 {
 642                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 643                 reg = <0x0 0xff320000 0x0 0x1000>;
 644         };
 645
 646         spi3: spi@ff350000 {
 647                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 648                 reg = <0x0 0xff350000 0x0 0x1000>;
 649                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 650                 clock-names = "spiclk", "apb_pclk";
 651                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 654                 #address-cells = <1>;
 655                 #size-cells = <0>;
 656                 status = "disabled";
 657         };
 658
 659         uart4: serial@ff370000 {
 660                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 661                 reg = <0x0 0xff370000 0x0 0x100>;
 662                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 663                 clock-names = "baudclk", "apb_pclk";
 664                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 665                 reg-shift = <2>;
 666                 reg-io-width = <4>;
 667                 status = "disabled";
 668         };
 669
 670         i2c4: i2c@ff3d0000 {
 671                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 672                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 673                 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
 674                 clock-names = "i2c", "i2c_sclk";
 675                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&i2c4_xfer>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 status = "disabled";
 681         };
 682
 683         i2c8: i2c@ff3e0000 {
 684                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 685                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 686                 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
 687                 clock-names = "i2c", "i2c_sclk";
 688                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 689                 pinctrl-names = "default";
 690                 pinctrl-0 = <&i2c8_xfer>;
 691                 #address-cells = <1>;
 692                 #size-cells = <0>;
 693                 status = "disabled";
 694         };
 695
 696         pwm0: pwm@ff420000 {
 697                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 698                 reg = <0x0 0xff420000 0x0 0x10>;
 699                 #pwm-cells = <3>;
 700                 pinctrl-names = "default";
 701                 pinctrl-0 = <&pwm0_pin>;
 702                 clocks = <&cru PCLK_RKPWM_PMU>;
 703                 clock-names = "pwm";
 704                 status = "disabled";
 705         };
 706
 707         pwm1: pwm@ff420010 {
 708                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 709                 reg = <0x0 0xff420010 0x0 0x10>;
 710                 #pwm-cells = <3>;
 711                 pinctrl-names = "default";
 712                 pinctrl-0 = <&pwm1_pin>;
 713                 clocks = <&cru PCLK_RKPWM_PMU>;
 714                 clock-names = "pwm";
 715                 status = "disabled";
 716         };
 717
 718         pwm2: pwm@ff420020 {
 719                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 720                 reg = <0x0 0xff420020 0x0 0x10>;
 721                 #pwm-cells = <3>;
 722                 pinctrl-names = "default";
 723                 pinctrl-0 = <&pwm2_pin>;
 724                 clocks = <&cru PCLK_RKPWM_PMU>;
 725                 clock-names = "pwm";
 726                 status = "disabled";
 727         };
 728
 729         pwm3: pwm@ff420030 {
 730                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 731                 reg = <0x0 0xff420030 0x0 0x10>;
 732                 #pwm-cells = <3>;
 733                 pinctrl-names = "default";
 734                 pinctrl-0 = <&pwm3a_pin>;
 735                 clocks = <&cru PCLK_RKPWM_PMU>;
 736                 clock-names = "pwm";
 737                 status = "disabled";
 738         };
 739
 740         pmucru: pmu-clock-controller@ff750000 {
 741                 compatible = "rockchip,rk3399-pmucru";
 742                 reg = <0x0 0xff750000 0x0 0x1000>;
 743                 rockchip,grf = <&pmugrf>;
 744                 #clock-cells = <1>;
 745                 #reset-cells = <1>;
 746         };
 747
 748         cru: clock-controller@ff760000 {
 749                 compatible = "rockchip,rk3399-cru";
 750                 reg = <0x0 0xff760000 0x0 0x1000>;
 751                 rockchip,grf = <&grf>;
 752                 #clock-cells = <1>;
 753                 #reset-cells = <1>;
 754         };
 755
 756         grf: syscon@ff770000 {
 757                 compatible = "rockchip,rk3399-grf", "syscon";
 758                 reg = <0x0 0xff770000 0x0 0x10000>;
 759         };
 760
 761         wdt0: watchdog@ff840000 {
 762                 compatible = "snps,dw-wdt";
 763                 reg = <0x0 0xff840000 0x0 0x100>;
 764                 clocks = <&cru PCLK_WDT>;
 765                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 766                 status = "disabled";
 767         };
 768
 769         spdif: spdif@ff870000 {
 770                 compatible = "rockchip,rk3399-spdif";
 771                 reg = <0x0 0xff870000 0x0 0x1000>;
 772                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 773                 dmas = <&dmac_bus 7>;
 774                 dma-names = "tx";
 775                 clock-names = "hclk", "mclk";
 776                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 777                 pinctrl-names = "default";
 778                 pinctrl-0 = <&spdif_bus>;
 779                 status = "disabled";
 780         };
 781
 782         i2s0: i2s@ff880000 {
 783                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 784                 reg = <0x0 0xff880000 0x0 0x1000>;
 785                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 786                 #address-cells = <1>;
 787                 #size-cells = <0>;
 788                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 789                 dma-names = "tx", "rx";
 790                 clock-names = "i2s_hclk", "i2s_clk";
 791                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 792                 pinctrl-names = "default";
 793                 pinctrl-0 = <&i2s0_8ch_bus>;
 794                 status = "disabled";
 795         };
 796
 797         i2s1: i2s@ff890000 {
 798                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 799                 reg = <0x0 0xff890000 0x0 0x1000>;
 800                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 801                 #address-cells = <1>;
 802                 #size-cells = <0>;
 803                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 804                 dma-names = "tx", "rx";
 805                 clock-names = "i2s_hclk", "i2s_clk";
 806                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 807                 pinctrl-names = "default";
 808                 pinctrl-0 = <&i2s1_2ch_bus>;
 809                 status = "disabled";
 810         };
 811
 812         i2s2: i2s@ff8a0000 {
 813                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 814                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 815                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 816                 #address-cells = <1>;
 817                 #size-cells = <0>;
 818                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 819                 dma-names = "tx", "rx";
 820                 clock-names = "i2s_hclk", "i2s_clk";
 821                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 822                 status = "disabled";
 823         };
 824
 825         pinctrl: pinctrl {
 826                 compatible = "rockchip,rk3399-pinctrl";
 827                 rockchip,grf = <&grf>;
 828                 rockchip,pmu = <&pmugrf>;
 829                 #address-cells = <0x2>;
 830                 #size-cells = <0x2>;
 831                 ranges;
 832
 833                 gpio0: gpio0@ff720000 {
 834                         compatible = "rockchip,gpio-bank";
 835                         reg = <0x0 0xff720000 0x0 0x100>;
 836                         clocks = <&xin24m>;
 837                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 838
 839                         gpio-controller;
 840                         #gpio-cells = <0x2>;
 841
 842                         interrupt-controller;
 843                         #interrupt-cells = <0x2>;
 844                 };
 845
 846                 gpio1: gpio1@ff730000 {
 847                         compatible = "rockchip,gpio-bank";
 848                         reg = <0x0 0xff730000 0x0 0x100>;
 849                         clocks = <&xin24m>;
 850                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 851
 852                         gpio-controller;
 853                         #gpio-cells = <0x2>;
 854
 855                         interrupt-controller;
 856                         #interrupt-cells = <0x2>;
 857                 };
 858
 859                 gpio2: gpio2@ff780000 {
 860                         compatible = "rockchip,gpio-bank";
 861                         reg = <0x0 0xff780000 0x0 0x100>;
 862                         clocks = <&xin24m>;
 863                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 864
 865                         gpio-controller;
 866                         #gpio-cells = <0x2>;
 867
 868                         interrupt-controller;
 869                         #interrupt-cells = <0x2>;
 870                 };
 871
 872                 gpio3: gpio3@ff788000 {
 873                         compatible = "rockchip,gpio-bank";
 874                         reg = <0x0 0xff788000 0x0 0x100>;
 875                         clocks = <&xin24m>;
 876                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 877
 878                         gpio-controller;
 879                         #gpio-cells = <0x2>;
 880
 881                         interrupt-controller;
 882                         #interrupt-cells = <0x2>;
 883                 };
 884
 885                 gpio4: gpio4@ff790000 {
 886                         compatible = "rockchip,gpio-bank";
 887                         reg = <0x0 0xff790000 0x0 0x100>;
 888                         clocks = <&xin24m>;
 889                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 890
 891                         gpio-controller;
 892                         #gpio-cells = <0x2>;
 893
 894                         interrupt-controller;
 895                         #interrupt-cells = <0x2>;
 896                 };
 897
 898                 pcfg_pull_up: pcfg-pull-up {
 899                         bias-pull-up;
 900                 };
 901
 902                 pcfg_pull_down: pcfg-pull-down {
 903                         bias-pull-down;
 904                 };
 905
 906                 pcfg_pull_none: pcfg-pull-none {
 907                         bias-disable;
 908                 };
 909
 910                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 911                         bias-disable;
 912                         drive-strength = <12>;
 913                 };
 914
 915                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 916                         bias-pull-up;
 917                         drive-strength = <8>;
 918                 };
 919
 920                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 921                         bias-pull-down;
 922                         drive-strength = <4>;
 923                 };
 924
 925                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 926                         bias-pull-up;
 927                         drive-strength = <2>;
 928                 };
 929
 930                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 931                         bias-pull-down;
 932                         drive-strength = <12>;
 933                 };
 934
 935                 emmc {
 936                         emmc_pwr: emmc-pwr {
 937                                 rockchip,pins =
 938                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 939                         };
 940                 };
 941
 942                 gmac {
 943                         rgmii_pins: rgmii-pins {
 944                                 rockchip,pins =
 945                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 946                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 947                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 948                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 949                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 950                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 951                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 952                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 953                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 954                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 955                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 956                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 957                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 958                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 959                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 960                         };
 961
 962                         rmii_pins: rmii-pins {
 963                                 rockchip,pins =
 964                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 965                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 966                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 967                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 968                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 969                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 970                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 971                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 972                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 973                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 974                         };
 975                 };
 976
 977                 i2c0 {
 978                         i2c0_xfer: i2c0-xfer {
 979                                 rockchip,pins =
 980                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 981                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 982                         };
 983                 };
 984
 985                 i2c1 {
 986                         i2c1_xfer: i2c1-xfer {
 987                                 rockchip,pins =
 988                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 989                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 990                         };
 991                 };
 992
 993                 i2c2 {
 994                         i2c2_xfer: i2c2-xfer {
 995                                 rockchip,pins =
 996                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 997                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 998                         };
 999                 };
1000
1001                 i2c3 {
1002                         i2c3_xfer: i2c3-xfer {
1003                                 rockchip,pins =
1004                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1005                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1006                         };
1007                 };
1008
1009                 i2c4 {
1010                         i2c4_xfer: i2c4-xfer {
1011                                 rockchip,pins =
1012                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1013                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1014                         };
1015                 };
1016
1017                 i2c5 {
1018                         i2c5_xfer: i2c5-xfer {
1019                                 rockchip,pins =
1020                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1021                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1022                         };
1023                 };
1024
1025                 i2c6 {
1026                         i2c6_xfer: i2c6-xfer {
1027                                 rockchip,pins =
1028                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1029                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1030                         };
1031                 };
1032
1033                 i2c7 {
1034                         i2c7_xfer: i2c7-xfer {
1035                                 rockchip,pins =
1036                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1037                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1038                         };
1039                 };
1040
1041                 i2c8 {
1042                         i2c8_xfer: i2c8-xfer {
1043                                 rockchip,pins =
1044                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1045                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1046                         };
1047                 };
1048
1049                 i2s0 {
1050                         i2s0_8ch_bus: i2s0-8ch-bus {
1051                                 rockchip,pins =
1052                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1053                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1054                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1055                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1056                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1057                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1058                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1059                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1060                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1061                         };
1062                 };
1063
1064                 i2s1 {
1065                         i2s1_2ch_bus: i2s1-2ch-bus {
1066                                 rockchip,pins =
1067                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1068                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1069                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1070                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1071                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1072                         };
1073                 };
1074
1075                 sdio0 {
1076                         sdio0_bus1: sdio0-bus1 {
1077                                 rockchip,pins =
1078                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1079                         };
1080
1081                         sdio0_bus4: sdio0-bus4 {
1082                                 rockchip,pins =
1083                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1084                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1085                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1086                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1087                         };
1088
1089                         sdio0_cmd: sdio0-cmd {
1090                                 rockchip,pins =
1091                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1092                         };
1093
1094                         sdio0_clk: sdio0-clk {
1095                                 rockchip,pins =
1096                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1097                         };
1098
1099                         sdio0_cd: sdio0-cd {
1100                                 rockchip,pins =
1101                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1102                         };
1103
1104                         sdio0_pwr: sdio0-pwr {
1105                                 rockchip,pins =
1106                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1107                         };
1108
1109                         sdio0_bkpwr: sdio0-bkpwr {
1110                                 rockchip,pins =
1111                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1112                         };
1113
1114                         sdio0_wp: sdio0-wp {
1115                                 rockchip,pins =
1116                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1117                         };
1118
1119                         sdio0_int: sdio0-int {
1120                                 rockchip,pins =
1121                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1122                         };
1123                 };
1124
1125                 sdmmc {
1126                         sdmmc_bus1: sdmmc-bus1 {
1127                                 rockchip,pins =
1128                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1129                         };
1130
1131                         sdmmc_bus4: sdmmc-bus4 {
1132                                 rockchip,pins =
1133                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1134                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1135                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1136                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1137                         };
1138
1139                         sdmmc_clk: sdmmc-clk {
1140                                 rockchip,pins =
1141                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1142                         };
1143
1144                         sdmmc_cmd: sdmmc-cmd {
1145                                 rockchip,pins =
1146                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1147                         };
1148
1149                         sdmmc_cd: sdmcc-cd {
1150                                 rockchip,pins =
1151                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1152                         };
1153
1154                         sdmmc_wp: sdmmc-wp {
1155                                 rockchip,pins =
1156                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1157                         };
1158                 };
1159
1160                 spdif {
1161                         spdif_bus: spdif-bus {
1162                                 rockchip,pins =
1163                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1164                         };
1165                 };
1166
1167                 spi0 {
1168                         spi0_clk: spi0-clk {
1169                                 rockchip,pins =
1170                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1171                         };
1172                         spi0_cs0: spi0-cs0 {
1173                                 rockchip,pins =
1174                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1175                         };
1176                         spi0_cs1: spi0-cs1 {
1177                                 rockchip,pins =
1178                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1179                         };
1180                         spi0_tx: spi0-tx {
1181                                 rockchip,pins =
1182                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1183                         };
1184                         spi0_rx: spi0-rx {
1185                                 rockchip,pins =
1186                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1187                         };
1188                 };
1189
1190                 spi1 {
1191                         spi1_clk: spi1-clk {
1192                                 rockchip,pins =
1193                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1194                         };
1195                         spi1_cs0: spi1-cs0 {
1196                                 rockchip,pins =
1197                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1198                         };
1199                         spi1_rx: spi1-rx {
1200                                 rockchip,pins =
1201                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1202                         };
1203                         spi1_tx: spi1-tx {
1204                                 rockchip,pins =
1205                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1206                         };
1207                 };
1208
1209                 spi2 {
1210                         spi2_clk: spi2-clk {
1211                                 rockchip,pins =
1212                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1213                         };
1214                         spi2_cs0: spi2-cs0 {
1215                                 rockchip,pins =
1216                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1217                         };
1218                         spi2_rx: spi2-rx {
1219                                 rockchip,pins =
1220                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1221                         };
1222                         spi2_tx: spi2-tx {
1223                                 rockchip,pins =
1224                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1225                         };
1226                 };
1227
1228                 spi3 {
1229                         spi3_clk: spi3-clk {
1230                                 rockchip,pins =
1231                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1232                         };
1233                         spi3_cs0: spi3-cs0 {
1234                                 rockchip,pins =
1235                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1236                         };
1237                         spi3_rx: spi3-rx {
1238                                 rockchip,pins =
1239                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1240                         };
1241                         spi3_tx: spi3-tx {
1242                                 rockchip,pins =
1243                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1244                         };
1245                 };
1246
1247                 spi4 {
1248                         spi4_clk: spi4-clk {
1249                                 rockchip,pins =
1250                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1251                         };
1252                         spi4_cs0: spi4-cs0 {
1253                                 rockchip,pins =
1254                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1255                         };
1256                         spi4_rx: spi4-rx {
1257                                 rockchip,pins =
1258                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1259                         };
1260                         spi4_tx: spi4-tx {
1261                                 rockchip,pins =
1262                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1263                         };
1264                 };
1265
1266                 spi5 {
1267                         spi5_clk: spi5-clk {
1268                                 rockchip,pins =
1269                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1270                         };
1271                         spi5_cs0: spi5-cs0 {
1272                                 rockchip,pins =
1273                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1274                         };
1275                         spi5_rx: spi5-rx {
1276                                 rockchip,pins =
1277                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1278                         };
1279                         spi5_tx: spi5-tx {
1280                                 rockchip,pins =
1281                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1282                         };
1283                 };
1284
1285                 tsadc {
1286                         otp_gpio: otp-gpio {
1287                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1288                         };
1289
1290                         otp_out: otp-out {
1291                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1292                         };
1293                 };
1294
1295                 uart0 {
1296                         uart0_xfer: uart0-xfer {
1297                                 rockchip,pins =
1298                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1299                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1300                         };
1301
1302                         uart0_cts: uart0-cts {
1303                                 rockchip,pins =
1304                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1305                         };
1306
1307                         uart0_rts: uart0-rts {
1308                                 rockchip,pins =
1309                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1310                         };
1311                 };
1312
1313                 uart1 {
1314                         uart1_xfer: uart1-xfer {
1315                                 rockchip,pins =
1316                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1317                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1318                         };
1319                 };
1320
1321                 uart2a {
1322                         uart2a_xfer: uart2a-xfer {
1323                                 rockchip,pins =
1324                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1325                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1326                         };
1327                 };
1328
1329                 uart2b {
1330                         uart2b_xfer: uart2b-xfer {
1331                                 rockchip,pins =
1332                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1333                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1334                         };
1335                 };
1336
1337                 uart2c {
1338                         uart2c_xfer: uart2c-xfer {
1339                                 rockchip,pins =
1340                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1341                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1342                         };
1343                 };
1344
1345                 uart3 {
1346                         uart3_xfer: uart3-xfer {
1347                                 rockchip,pins =
1348                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1349                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1350                         };
1351
1352                         uart3_cts: uart3-cts {
1353                                 rockchip,pins =
1354                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1355                         };
1356
1357                         uart3_rts: uart3-rts {
1358                                 rockchip,pins =
1359                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1360                         };
1361                 };
1362
1363                 uart4 {
1364                         uart4_xfer: uart4-xfer {
1365                                 rockchip,pins =
1366                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1367                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1368                         };
1369                 };
1370
1371                 uarthdcp {
1372                         uarthdcp_xfer: uarthdcp-xfer {
1373                                 rockchip,pins =
1374                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1375                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1376                         };
1377                 };
1378
1379                 pwm0 {
1380                         pwm0_pin: pwm0-pin {
1381                                 rockchip,pins =
1382                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1383                         };
1384
1385                         vop0_pwm_pin: vop0-pwm-pin {
1386                                 rockchip,pins =
1387                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1388                         };
1389                 };
1390
1391                 pwm1 {
1392                         pwm1_pin: pwm1-pin {
1393                                 rockchip,pins =
1394                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1395                         };
1396
1397                         vop1_pwm_pin: vop1-pwm-pin {
1398                                 rockchip,pins =
1399                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1400                         };
1401                 };
1402
1403                 pwm2 {
1404                         pwm2_pin: pwm2-pin {
1405                                 rockchip,pins =
1406                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1407                         };
1408                 };
1409
1410                 pwm3a {
1411                         pwm3a_pin: pwm3a-pin {
1412                                 rockchip,pins =
1413                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1414                         };
1415                 };
1416
1417                 pwm3b {
1418                         pwm3b_pin: pwm3b-pin {
1419                                 rockchip,pins =
1420                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1421                         };
1422                 };
1423
1424                 pmic {
1425                         pmic_int_l: pmic-int-l {
1426                                 rockchip,pins =
1427                                         <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
1428                         };
1429                 };
1430         };
1431 };