arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 #include "rk3399-dram-default-timing.dtsi"
  53
  54 / {
  55         compatible = "rockchip,rk3399";
  56
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 i2c6 = &i2c6;
  69                 i2c7 = &i2c7;
  70                 i2c8 = &i2c8;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu_l0: cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <100>;
 120                         clocks = <&cru ARMCLKL>;
 121                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 122                         operating-points-v2 = <&cluster0_opp>;
 123                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 124                 };
 125
 126                 cpu_l1: cpu@1 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         reg = <0x0 0x1>;
 130                         enable-method = "psci";
 131                         clocks = <&cru ARMCLKL>;
 132                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 133                         operating-points-v2 = <&cluster0_opp>;
 134                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 135                 };
 136
 137                 cpu_l2: cpu@2 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x2>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 144                         operating-points-v2 = <&cluster0_opp>;
 145                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 146                 };
 147
 148                 cpu_l3: cpu@3 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a53", "arm,armv8";
 151                         reg = <0x0 0x3>;
 152                         enable-method = "psci";
 153                         clocks = <&cru ARMCLKL>;
 154                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 155                         operating-points-v2 = <&cluster0_opp>;
 156                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 157                 };
 158
 159                 cpu_b0: cpu@100 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a72", "arm,armv8";
 162                         reg = <0x0 0x100>;
 163                         enable-method = "psci";
 164                         #cooling-cells = <2>; /* min followed by max */
 165                         dynamic-power-coefficient = <436>;
 166                         clocks = <&cru ARMCLKB>;
 167                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 168                         operating-points-v2 = <&cluster1_opp>;
 169                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 170                 };
 171
 172                 cpu_b1: cpu@101 {
 173                         device_type = "cpu";
 174                         compatible = "arm,cortex-a72", "arm,armv8";
 175                         reg = <0x0 0x101>;
 176                         enable-method = "psci";
 177                         clocks = <&cru ARMCLKB>;
 178                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 179                         operating-points-v2 = <&cluster1_opp>;
 180                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 181                 };
 182
 183                 idle-states {
 184                         entry-method = "psci";
 185
 186                         CPU_SLEEP: cpu-sleep {
 187                                 compatible = "arm,idle-state";
 188                                 local-timer-stop;
 189                                 arm,psci-suspend-param = <0x0010000>;
 190                                 entry-latency-us = <120>;
 191                                 exit-latency-us = <250>;
 192                                 min-residency-us = <900>;
 193                         };
 194
 195                         CLUSTER_SLEEP: cluster-sleep {
 196                                 compatible = "arm,idle-state";
 197                                 local-timer-stop;
 198                                 arm,psci-suspend-param = <0x1010000>;
 199                                 entry-latency-us = <400>;
 200                                 exit-latency-us = <500>;
 201                                 min-residency-us = <2000>;
 202                         };
 203                 };
 204
 205                 /include/ "rk3399-sched-energy.dtsi"
 206
 207         };
 208
 209         cluster0_opp: opp_table0 {
 210                 compatible = "operating-points-v2";
 211                 opp-shared;
 212
 213                 opp@408000000 {
 214                         opp-hz = /bits/ 64 <408000000>;
 215                         opp-microvolt = <800000>;
 216                         clock-latency-ns = <40000>;
 217                 };
 218                 opp@600000000 {
 219                         opp-hz = /bits/ 64 <600000000>;
 220                         opp-microvolt = <800000>;
 221                 };
 222                 opp@816000000 {
 223                         opp-hz = /bits/ 64 <816000000>;
 224                         opp-microvolt = <800000>;
 225                 };
 226                 opp@1008000000 {
 227                         opp-hz = /bits/ 64 <1008000000>;
 228                         opp-microvolt = <875000>;
 229                 };
 230                 opp@1200000000 {
 231                         opp-hz = /bits/ 64 <1200000000>;
 232                         opp-microvolt = <925000>;
 233                 };
 234                 opp@1416000000 {
 235                         opp-hz = /bits/ 64 <1416000000>;
 236                         opp-microvolt = <1025000>;
 237                 };
 238         };
 239
 240         cluster1_opp: opp_table1 {
 241                 compatible = "operating-points-v2";
 242                 opp-shared;
 243
 244                 opp@408000000 {
 245                         opp-hz = /bits/ 64 <408000000>;
 246                         opp-microvolt = <800000>;
 247                         clock-latency-ns = <40000>;
 248                 };
 249                 opp@600000000 {
 250                         opp-hz = /bits/ 64 <600000000>;
 251                         opp-microvolt = <800000>;
 252                 };
 253                 opp@816000000 {
 254                         opp-hz = /bits/ 64 <816000000>;
 255                         opp-microvolt = <800000>;
 256                 };
 257                 opp@1008000000 {
 258                         opp-hz = /bits/ 64 <1008000000>;
 259                         opp-microvolt = <850000>;
 260                 };
 261                 opp@1200000000 {
 262                         opp-hz = /bits/ 64 <1200000000>;
 263                         opp-microvolt = <925000>;
 264                 };
 265         };
 266
 267         cpu_avs: cpu-avs {
 268                 cluster0-avs {
 269                         cluster-id = <0>;
 270                         min-volt = <800000>; /* uV */
 271                         min-freq = <408000>; /* KHz */
 272                         leakage-adjust-volt = <
 273                         /*  mA        mA         uV */
 274                             0         254        0
 275                         >;
 276                         nvmem-cells = <&cpul_leakage>;
 277                         nvmem-cell-names = "cpu_leakage";
 278                 };
 279                 cluster1-avs {
 280                         cluster-id = <1>;
 281                         min-volt = <800000>; /* uV */
 282                         min-freq = <408000>; /* KHz */
 283                         leakage-adjust-volt = <
 284                         /*  mA        mA         uV */
 285                             0         254        0
 286                         >;
 287                         nvmem-cells = <&cpub_leakage>;
 288                         nvmem-cell-names = "cpu_leakage";
 289                 };
 290         };
 291
 292         timer {
 293                 compatible = "arm,armv8-timer";
 294                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 295                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 296                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 297                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 298         };
 299
 300         pmu_a53 {
 301                 compatible = "arm,cortex-a53-pmu";
 302                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 303         };
 304
 305         pmu_a72 {
 306                 compatible = "arm,cortex-a72-pmu";
 307                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 308         };
 309
 310         xin24m: xin24m {
 311                 compatible = "fixed-clock";
 312                 #clock-cells = <0>;
 313                 clock-frequency = <24000000>;
 314                 clock-output-names = "xin24m";
 315         };
 316
 317         amba {
 318                 compatible = "arm,amba-bus";
 319                 #address-cells = <2>;
 320                 #size-cells = <2>;
 321                 ranges;
 322
 323                 dmac_bus: dma-controller@ff6d0000 {
 324                         compatible = "arm,pl330", "arm,primecell";
 325                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 326                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 327                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 328                         #dma-cells = <1>;
 329                         clocks = <&cru ACLK_DMAC0_PERILP>;
 330                         clock-names = "apb_pclk";
 331                         peripherals-req-type-burst;
 332                 };
 333
 334                 dmac_peri: dma-controller@ff6e0000 {
 335                         compatible = "arm,pl330", "arm,primecell";
 336                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 337                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 338                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 339                         #dma-cells = <1>;
 340                         clocks = <&cru ACLK_DMAC1_PERILP>;
 341                         clock-names = "apb_pclk";
 342                         peripherals-req-type-burst;
 343                 };
 344         };
 345
 346         gmac: eth@fe300000 {
 347                 compatible = "rockchip,rk3399-gmac";
 348                 reg = <0x0 0xfe300000 0x0 0x10000>;
 349                 rockchip,grf = <&grf>;
 350                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 351                 interrupt-names = "macirq";
 352                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 353                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 354                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 355                          <&cru PCLK_GMAC>;
 356                 clock-names = "stmmaceth", "mac_clk_rx",
 357                               "mac_clk_tx", "clk_mac_ref",
 358                               "clk_mac_refout", "aclk_mac",
 359                               "pclk_mac";
 360                 resets = <&cru SRST_A_GMAC>;
 361                 reset-names = "stmmaceth";
 362                 power-domains = <&power RK3399_PD_GMAC>;
 363                 status = "disabled";
 364         };
 365
 366         sdio0: dwmmc@fe310000 {
 367                 compatible = "rockchip,rk3399-dw-mshc",
 368                              "rockchip,rk3288-dw-mshc";
 369                 reg = <0x0 0xfe310000 0x0 0x4000>;
 370                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 371                 clock-freq-min-max = <400000 150000000>;
 372                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 373                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 374                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 375                 fifo-depth = <0x100>;
 376                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 377                 status = "disabled";
 378         };
 379
 380         sdmmc: dwmmc@fe320000 {
 381                 compatible = "rockchip,rk3399-dw-mshc",
 382                              "rockchip,rk3288-dw-mshc";
 383                 reg = <0x0 0xfe320000 0x0 0x4000>;
 384                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 385                 clock-freq-min-max = <400000 150000000>;
 386                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 387                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 388                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 389                 fifo-depth = <0x100>;
 390                 power-domains = <&power RK3399_PD_SD>;
 391                 status = "disabled";
 392         };
 393
 394         sdhci: sdhci@fe330000 {
 395                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 396                 reg = <0x0 0xfe330000 0x0 0x10000>;
 397                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 398                 arasan,soc-ctl-syscon = <&grf>;
 399                 assigned-clocks = <&cru SCLK_EMMC>;
 400                 assigned-clock-rates = <200000000>;
 401                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 402                 clock-names = "clk_xin", "clk_ahb";
 403                 clock-output-names = "emmc_cardclock";
 404                 #clock-cells = <0>;
 405                 phys = <&emmc_phy>;
 406                 phy-names = "phy_arasan";
 407                 power-domains = <&power RK3399_PD_EMMC>;
 408                 status = "disabled";
 409         };
 410
 411         usb_host0_ehci: usb@fe380000 {
 412                 compatible = "generic-ehci";
 413                 reg = <0x0 0xfe380000 0x0 0x20000>;
 414                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 415                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 416                          <&cru SCLK_USBPHY0_480M_SRC>;
 417                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 418                 phys = <&u2phy0_host>;
 419                 phy-names = "usb";
 420                 power-domains = <&power RK3399_PD_PERIHP>;
 421                 status = "disabled";
 422         };
 423
 424         usb_host0_ohci: usb@fe3a0000 {
 425                 compatible = "generic-ohci";
 426                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 427                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 428                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 429                          <&cru SCLK_USBPHY0_480M_SRC>;
 430                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 431                 phys = <&u2phy0_host>;
 432                 phy-names = "usb";
 433                 power-domains = <&power RK3399_PD_PERIHP>;
 434                 status = "disabled";
 435         };
 436
 437         usb_host1_ehci: usb@fe3c0000 {
 438                 compatible = "generic-ehci";
 439                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 440                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 441                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 442                          <&cru SCLK_USBPHY1_480M_SRC>;
 443                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 444                 phys = <&u2phy1_host>;
 445                 phy-names = "usb";
 446                 power-domains = <&power RK3399_PD_PERIHP>;
 447                 status = "disabled";
 448         };
 449
 450         usb_host1_ohci: usb@fe3e0000 {
 451                 compatible = "generic-ohci";
 452                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 453                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 454                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 455                          <&cru SCLK_USBPHY1_480M_SRC>;
 456                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 457                 phys = <&u2phy1_host>;
 458                 phy-names = "usb";
 459                 power-domains = <&power RK3399_PD_PERIHP>;
 460                 status = "disabled";
 461         };
 462
 463         usbdrd3_0: usb@fe800000 {
 464                 compatible = "rockchip,rk3399-dwc3";
 465                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 466                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 467                 clock-names = "ref_clk", "suspend_clk",
 468                               "bus_clk", "grf_clk";
 469                 power-domains = <&power RK3399_PD_USB3>;
 470                 resets = <&cru SRST_A_USB3_OTG0>;
 471                 reset-names = "usb3-otg";
 472                 #address-cells = <2>;
 473                 #size-cells = <2>;
 474                 ranges;
 475                 status = "disabled";
 476                 usbdrd_dwc3_0: dwc3@fe800000 {
 477                         compatible = "snps,dwc3";
 478                         reg = <0x0 0xfe800000 0x0 0x100000>;
 479                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 480                         dr_mode = "otg";
 481                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 482                         phy-names = "usb2-phy", "usb3-phy";
 483                         phy_type = "utmi_wide";
 484                         snps,dis_enblslpm_quirk;
 485                         snps,dis-u2-freeclk-exists-quirk;
 486                         snps,dis_u2_susphy_quirk;
 487                         snps,dis-del-phy-power-chg-quirk;
 488                         snps,xhci-slow-suspend-quirk;
 489                         status = "disabled";
 490                 };
 491         };
 492
 493         usbdrd3_1: usb@fe900000 {
 494                 compatible = "rockchip,rk3399-dwc3";
 495                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 496                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 497                 clock-names = "ref_clk", "suspend_clk",
 498                               "bus_clk", "grf_clk";
 499                 power-domains = <&power RK3399_PD_USB3>;
 500                 resets = <&cru SRST_A_USB3_OTG1>;
 501                 reset-names = "usb3-otg";
 502                 #address-cells = <2>;
 503                 #size-cells = <2>;
 504                 ranges;
 505                 status = "disabled";
 506                 usbdrd_dwc3_1: dwc3@fe900000 {
 507                         compatible = "snps,dwc3";
 508                         reg = <0x0 0xfe900000 0x0 0x100000>;
 509                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 510                         dr_mode = "host";
 511                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 512                         phy-names = "usb2-phy", "usb3-phy";
 513                         phy_type = "utmi_wide";
 514                         snps,dis_enblslpm_quirk;
 515                         snps,dis-u2-freeclk-exists-quirk;
 516                         snps,dis_u2_susphy_quirk;
 517                         snps,dis-del-phy-power-chg-quirk;
 518                         snps,xhci-slow-suspend-quirk;
 519                         status = "disabled";
 520                 };
 521         };
 522
 523         gic: interrupt-controller@fee00000 {
 524                 compatible = "arm,gic-v3";
 525                 #interrupt-cells = <4>;
 526                 #address-cells = <2>;
 527                 #size-cells = <2>;
 528                 ranges;
 529                 interrupt-controller;
 530
 531                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 532                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 533                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 534                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 535                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 536                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 537                 its: interrupt-controller@fee20000 {
 538                         compatible = "arm,gic-v3-its";
 539                         msi-controller;
 540                         reg = <0x0 0xfee20000 0x0 0x20000>;
 541                 };
 542
 543                 ppi-partitions {
 544                         part0: interrupt-partition-0 {
 545                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 546                         };
 547
 548                         part1: interrupt-partition-1 {
 549                                 affinity = <&cpu_b0 &cpu_b1>;
 550                         };
 551                 };
 552         };
 553
 554         saradc: saradc@ff100000 {
 555                 compatible = "rockchip,rk3399-saradc";
 556                 reg = <0x0 0xff100000 0x0 0x100>;
 557                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 558                 #io-channel-cells = <1>;
 559                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 560                 clock-names = "saradc", "apb_pclk";
 561                 resets = <&cru SRST_P_SARADC>;
 562                 reset-names = "saradc-apb";
 563                 status = "disabled";
 564         };
 565
 566         i2c0: i2c@ff3c0000 {
 567                 compatible = "rockchip,rk3399-i2c";
 568                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 569                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 570                 clock-names = "i2c", "pclk";
 571                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c0_xfer>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         i2c1: i2c@ff110000 {
 580                 compatible = "rockchip,rk3399-i2c";
 581                 reg = <0x0 0xff110000 0x0 0x1000>;
 582                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 583                 clock-names = "i2c", "pclk";
 584                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&i2c1_xfer>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         i2c2: i2c@ff120000 {
 593                 compatible = "rockchip,rk3399-i2c";
 594                 reg = <0x0 0xff120000 0x0 0x1000>;
 595                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 596                 clock-names = "i2c", "pclk";
 597                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&i2c2_xfer>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 status = "disabled";
 603         };
 604
 605         i2c3: i2c@ff130000 {
 606                 compatible = "rockchip,rk3399-i2c";
 607                 reg = <0x0 0xff130000 0x0 0x1000>;
 608                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 609                 clock-names = "i2c", "pclk";
 610                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&i2c3_xfer>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 status = "disabled";
 616         };
 617
 618         i2c5: i2c@ff140000 {
 619                 compatible = "rockchip,rk3399-i2c";
 620                 reg = <0x0 0xff140000 0x0 0x1000>;
 621                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 622                 clock-names = "i2c", "pclk";
 623                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&i2c5_xfer>;
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 status = "disabled";
 629         };
 630
 631         i2c6: i2c@ff150000 {
 632                 compatible = "rockchip,rk3399-i2c";
 633                 reg = <0x0 0xff150000 0x0 0x1000>;
 634                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 635                 clock-names = "i2c", "pclk";
 636                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&i2c6_xfer>;
 639                 #address-cells = <1>;
 640                 #size-cells = <0>;
 641                 status = "disabled";
 642         };
 643
 644         i2c7: i2c@ff160000 {
 645                 compatible = "rockchip,rk3399-i2c";
 646                 reg = <0x0 0xff160000 0x0 0x1000>;
 647                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 648                 clock-names = "i2c", "pclk";
 649                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&i2c7_xfer>;
 652                 #address-cells = <1>;
 653                 #size-cells = <0>;
 654                 status = "disabled";
 655         };
 656
 657         uart0: serial@ff180000 {
 658                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 659                 reg = <0x0 0xff180000 0x0 0x100>;
 660                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 661                 clock-names = "baudclk", "apb_pclk";
 662                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 663                 reg-shift = <2>;
 664                 reg-io-width = <4>;
 665                 pinctrl-names = "default";
 666                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 667                 status = "disabled";
 668         };
 669
 670         uart1: serial@ff190000 {
 671                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 672                 reg = <0x0 0xff190000 0x0 0x100>;
 673                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 674                 clock-names = "baudclk", "apb_pclk";
 675                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 676                 reg-shift = <2>;
 677                 reg-io-width = <4>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&uart1_xfer>;
 680                 status = "disabled";
 681         };
 682
 683         uart2: serial@ff1a0000 {
 684                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 685                 reg = <0x0 0xff1a0000 0x0 0x100>;
 686                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 687                 clock-names = "baudclk", "apb_pclk";
 688                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 689                 reg-shift = <2>;
 690                 reg-io-width = <4>;
 691                 pinctrl-names = "default";
 692                 pinctrl-0 = <&uart2c_xfer>;
 693                 status = "disabled";
 694         };
 695
 696         uart3: serial@ff1b0000 {
 697                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 698                 reg = <0x0 0xff1b0000 0x0 0x100>;
 699                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 700                 clock-names = "baudclk", "apb_pclk";
 701                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 702                 reg-shift = <2>;
 703                 reg-io-width = <4>;
 704                 pinctrl-names = "default";
 705                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 706                 status = "disabled";
 707         };
 708
 709         spi0: spi@ff1c0000 {
 710                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 711                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 712                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 713                 clock-names = "spiclk", "apb_pclk";
 714                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 715                 pinctrl-names = "default";
 716                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 status = "disabled";
 720         };
 721
 722         spi1: spi@ff1d0000 {
 723                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 724                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 725                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 726                 clock-names = "spiclk", "apb_pclk";
 727                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 728                 pinctrl-names = "default";
 729                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 730                 #address-cells = <1>;
 731                 #size-cells = <0>;
 732                 status = "disabled";
 733         };
 734
 735         spi2: spi@ff1e0000 {
 736                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 737                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 738                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 739                 clock-names = "spiclk", "apb_pclk";
 740                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 741                 pinctrl-names = "default";
 742                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 743                 #address-cells = <1>;
 744                 #size-cells = <0>;
 745                 status = "disabled";
 746         };
 747
 748         spi4: spi@ff1f0000 {
 749                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 750                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 751                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 752                 clock-names = "spiclk", "apb_pclk";
 753                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 754                 pinctrl-names = "default";
 755                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 756                 #address-cells = <1>;
 757                 #size-cells = <0>;
 758                 status = "disabled";
 759         };
 760
 761         spi5: spi@ff200000 {
 762                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 763                 reg = <0x0 0xff200000 0x0 0x1000>;
 764                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 765                 clock-names = "spiclk", "apb_pclk";
 766                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 767                 pinctrl-names = "default";
 768                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 769                 #address-cells = <1>;
 770                 #size-cells = <0>;
 771                 status = "disabled";
 772         };
 773
 774         thermal-zones {
 775                 soc_thermal: soc-thermal {
 776                         polling-delay-passive = <20>; /* milliseconds */
 777                         polling-delay = <1000>; /* milliseconds */
 778                         sustainable-power = <1000>; /* milliwatts */
 779
 780                         thermal-sensors = <&tsadc 0>;
 781
 782                         trips {
 783                                 threshold: trip-point@0 {
 784                                         temperature = <70000>; /* millicelsius */
 785                                         hysteresis = <2000>; /* millicelsius */
 786                                         type = "passive";
 787                                 };
 788                                 target: trip-point@1 {
 789                                         temperature = <85000>; /* millicelsius */
 790                                         hysteresis = <2000>; /* millicelsius */
 791                                         type = "passive";
 792                                 };
 793                                 soc_crit: soc-crit {
 794                                         temperature = <95000>; /* millicelsius */
 795                                         hysteresis = <2000>; /* millicelsius */
 796                                         type = "critical";
 797                                 };
 798                         };
 799
 800                         cooling-maps {
 801                                 map0 {
 802                                         trip = <&target>;
 803                                         cooling-device =
 804                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 805                                         contribution = <4096>;
 806                                 };
 807                                 map1 {
 808                                         trip = <&target>;
 809                                         cooling-device =
 810                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 811                                         contribution = <1024>;
 812                                 };
 813                                 map2 {
 814                                         trip = <&target>;
 815                                         cooling-device =
 816                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 817                                         contribution = <4096>;
 818                                 };
 819                         };
 820                 };
 821
 822                 gpu_thermal: gpu-thermal {
 823                         polling-delay-passive = <100>; /* milliseconds */
 824                         polling-delay = <1000>; /* milliseconds */
 825
 826                         thermal-sensors = <&tsadc 1>;
 827                 };
 828         };
 829
 830         tsadc: tsadc@ff260000 {
 831                 compatible = "rockchip,rk3399-tsadc";
 832                 reg = <0x0 0xff260000 0x0 0x100>;
 833                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 834                 rockchip,grf = <&grf>;
 835                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 836                 clock-names = "tsadc", "apb_pclk";
 837                 assigned-clocks = <&cru SCLK_TSADC>;
 838                 assigned-clock-rates = <750000>;
 839                 resets = <&cru SRST_TSADC>;
 840                 reset-names = "tsadc-apb";
 841                 pinctrl-names = "init", "default", "sleep";
 842                 pinctrl-0 = <&otp_gpio>;
 843                 pinctrl-1 = <&otp_out>;
 844                 pinctrl-2 = <&otp_gpio>;
 845                 #thermal-sensor-cells = <1>;
 846                 rockchip,hw-tshut-temp = <95000>;
 847                 status = "disabled";
 848         };
 849
 850         qos_emmc: qos@ffa58000 {
 851                 compatible = "syscon";
 852                 reg = <0x0 0xffa58000 0x0 0x20>;
 853         };
 854
 855         qos_gmac: qos@ffa5c000 {
 856                 compatible = "syscon";
 857                 reg = <0x0 0xffa5c000 0x0 0x20>;
 858         };
 859
 860         qos_pcie: qos@ffa60080 {
 861                 compatible = "syscon";
 862                 reg = <0x0 0xffa60080 0x0 0x20>;
 863         };
 864
 865         qos_usb_host0: qos@ffa60100 {
 866                 compatible = "syscon";
 867                 reg = <0x0 0xffa60100 0x0 0x20>;
 868         };
 869
 870         qos_usb_host1: qos@ffa60180 {
 871                 compatible = "syscon";
 872                 reg = <0x0 0xffa60180 0x0 0x20>;
 873         };
 874
 875         qos_usb_otg0: qos@ffa70000 {
 876                 compatible = "syscon";
 877                 reg = <0x0 0xffa70000 0x0 0x20>;
 878         };
 879
 880         qos_usb_otg1: qos@ffa70080 {
 881                 compatible = "syscon";
 882                 reg = <0x0 0xffa70080 0x0 0x20>;
 883         };
 884
 885         qos_sd: qos@ffa74000 {
 886                 compatible = "syscon";
 887                 reg = <0x0 0xffa74000 0x0 0x20>;
 888         };
 889
 890         qos_sdioaudio: qos@ffa76000 {
 891                 compatible = "syscon";
 892                 reg = <0x0 0xffa76000 0x0 0x20>;
 893         };
 894
 895         qos_hdcp: qos@ffa90000 {
 896                 compatible = "syscon";
 897                 reg = <0x0 0xffa90000 0x0 0x20>;
 898         };
 899
 900         qos_iep: qos@ffa98000 {
 901                 compatible = "syscon";
 902                 reg = <0x0 0xffa98000 0x0 0x20>;
 903         };
 904
 905         qos_isp0_m0: qos@ffaa0000 {
 906                 compatible = "syscon";
 907                 reg = <0x0 0xffaa0000 0x0 0x20>;
 908         };
 909
 910         qos_isp0_m1: qos@ffaa0080 {
 911                 compatible = "syscon";
 912                 reg = <0x0 0xffaa0080 0x0 0x20>;
 913         };
 914
 915         qos_isp1_m0: qos@ffaa8000 {
 916                 compatible = "syscon";
 917                 reg = <0x0 0xffaa8000 0x0 0x20>;
 918         };
 919
 920         qos_isp1_m1: qos@ffaa8080 {
 921                 compatible = "syscon";
 922                 reg = <0x0 0xffaa8080 0x0 0x20>;
 923         };
 924
 925         qos_rga_r: qos@ffab0000 {
 926                 compatible = "syscon";
 927                 reg = <0x0 0xffab0000 0x0 0x20>;
 928         };
 929
 930         qos_rga_w: qos@ffab0080 {
 931                 compatible = "syscon";
 932                 reg = <0x0 0xffab0080 0x0 0x20>;
 933         };
 934
 935         qos_video_m0: qos@ffab8000 {
 936                 compatible = "syscon";
 937                 reg = <0x0 0xffab8000 0x0 0x20>;
 938         };
 939
 940         qos_video_m1_r: qos@ffac0000 {
 941                 compatible = "syscon";
 942                 reg = <0x0 0xffac0000 0x0 0x20>;
 943         };
 944
 945         qos_video_m1_w: qos@ffac0080 {
 946                 compatible = "syscon";
 947                 reg = <0x0 0xffac0080 0x0 0x20>;
 948         };
 949
 950         qos_vop_big_r: qos@ffac8000 {
 951                 compatible = "syscon";
 952                 reg = <0x0 0xffac8000 0x0 0x20>;
 953         };
 954
 955         qos_vop_big_w: qos@ffac8080 {
 956                 compatible = "syscon";
 957                 reg = <0x0 0xffac8080 0x0 0x20>;
 958         };
 959
 960         qos_vop_little: qos@ffad0000 {
 961                 compatible = "syscon";
 962                 reg = <0x0 0xffad0000 0x0 0x20>;
 963         };
 964
 965         qos_perihp: qos@ffad8080 {
 966                 compatible = "syscon";
 967                 reg = <0x0 0xffad8080 0x0 0x20>;
 968         };
 969
 970         qos_gpu: qos@ffae0000 {
 971                 compatible = "syscon";
 972                 reg = <0x0 0xffae0000 0x0 0x20>;
 973         };
 974
 975         pmu: power-management@ff310000 {
 976                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 977                 reg = <0x0 0xff310000 0x0 0x1000>;
 978
 979                 /*
 980                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 981                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 982                  * Some of the power domains are grouped together for every
 983                  * voltage domain.
 984                  * The detail contents as below.
 985                  */
 986                 power: power-controller {
 987                         compatible = "rockchip,rk3399-power-controller";
 988                         #power-domain-cells = <1>;
 989                         #address-cells = <1>;
 990                         #size-cells = <0>;
 991
 992                         /* These power domains are grouped by VD_CENTER */
 993                         pd_iep@RK3399_PD_IEP {
 994                                 reg = <RK3399_PD_IEP>;
 995                                 clocks = <&cru ACLK_IEP>,
 996                                          <&cru HCLK_IEP>;
 997                                 pm_qos = <&qos_iep>;
 998                         };
 999                         pd_rga@RK3399_PD_RGA {
1000                                 reg = <RK3399_PD_RGA>;
1001                                 clocks = <&cru ACLK_RGA>,
1002                                          <&cru HCLK_RGA>;
1003                                 pm_qos = <&qos_rga_r>,
1004                                          <&qos_rga_w>;
1005                         };
1006                         pd_vcodec@RK3399_PD_VCODEC {
1007                                 reg = <RK3399_PD_VCODEC>;
1008                                 clocks = <&cru ACLK_VCODEC>,
1009                                          <&cru HCLK_VCODEC>;
1010                                 pm_qos = <&qos_video_m0>;
1011                         };
1012                         pd_vdu@RK3399_PD_VDU {
1013                                 reg = <RK3399_PD_VDU>;
1014                                 clocks = <&cru ACLK_VDU>,
1015                                          <&cru HCLK_VDU>;
1016                                 pm_qos = <&qos_video_m1_r>,
1017                                          <&qos_video_m1_w>;
1018                         };
1019
1020                         /* These power domains are grouped by VD_GPU */
1021                         pd_gpu@RK3399_PD_GPU {
1022                                 reg = <RK3399_PD_GPU>;
1023                                 clocks = <&cru ACLK_GPU>;
1024                                 pm_qos = <&qos_gpu>;
1025                         };
1026
1027                         /* These power domains are grouped by VD_LOGIC */
1028                         pd_edp@RK3399_PD_EDP {
1029                                 reg = <RK3399_PD_EDP>;
1030                                 clocks = <&cru PCLK_EDP_CTRL>;
1031                         };
1032                         pd_emmc@RK3399_PD_EMMC {
1033                                 reg = <RK3399_PD_EMMC>;
1034                                 clocks = <&cru ACLK_EMMC>;
1035                                 pm_qos = <&qos_emmc>;
1036                         };
1037                         pd_gmac@RK3399_PD_GMAC {
1038                                 reg = <RK3399_PD_GMAC>;
1039                                 clocks = <&cru ACLK_GMAC>;
1040                                 pm_qos = <&qos_gmac>;
1041                         };
1042                         pd_perihp@RK3399_PD_PERIHP {
1043                                 reg = <RK3399_PD_PERIHP>;
1044                                 #address-cells = <1>;
1045                                 #size-cells = <0>;
1046                                 clocks = <&cru ACLK_PERIHP>;
1047                                 pm_qos = <&qos_perihp>,
1048                                          <&qos_pcie>,
1049                                          <&qos_usb_host0>,
1050                                          <&qos_usb_host1>;
1051
1052                                 pd_sd@RK3399_PD_SD {
1053                                         reg = <RK3399_PD_SD>;
1054                                         clocks = <&cru HCLK_SDMMC>,
1055                                                  <&cru SCLK_SDMMC>;
1056                                         pm_qos = <&qos_sd>;
1057                                 };
1058                         };
1059                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1060                                 reg = <RK3399_PD_SDIOAUDIO>;
1061                                 clocks = <&cru HCLK_SDIO>;
1062                                 pm_qos = <&qos_sdioaudio>;
1063                         };
1064                         pd_usb3@RK3399_PD_USB3 {
1065                                 reg = <RK3399_PD_USB3>;
1066                                 clocks = <&cru ACLK_USB3>;
1067                                 pm_qos = <&qos_usb_otg0>,
1068                                          <&qos_usb_otg1>;
1069                         };
1070                         pd_vio@RK3399_PD_VIO {
1071                                 reg = <RK3399_PD_VIO>;
1072                                 #address-cells = <1>;
1073                                 #size-cells = <0>;
1074
1075                                 pd_hdcp@RK3399_PD_HDCP {
1076                                         reg = <RK3399_PD_HDCP>;
1077                                         clocks = <&cru ACLK_HDCP>,
1078                                                  <&cru HCLK_HDCP>,
1079                                                  <&cru PCLK_HDCP>;
1080                                         pm_qos = <&qos_hdcp>;
1081                                 };
1082                                 pd_isp0@RK3399_PD_ISP0 {
1083                                         reg = <RK3399_PD_ISP0>;
1084                                         clocks = <&cru ACLK_ISP0>,
1085                                                  <&cru HCLK_ISP0>;
1086                                         pm_qos = <&qos_isp0_m0>,
1087                                                  <&qos_isp0_m1>;
1088                                 };
1089                                 pd_isp1@RK3399_PD_ISP1 {
1090                                         reg = <RK3399_PD_ISP1>;
1091                                         clocks = <&cru ACLK_ISP1>,
1092                                                  <&cru HCLK_ISP1>;
1093                                         pm_qos = <&qos_isp1_m0>,
1094                                                  <&qos_isp1_m1>;
1095                                 };
1096                                 pd_tcpc0@RK3399_PD_TCPC0 {
1097                                         reg = <RK3399_PD_TCPD0>;
1098                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1099                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1100                                 };
1101                                 pd_tcpc1@RK3399_PD_TCPC1 {
1102                                         reg = <RK3399_PD_TCPD1>;
1103                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1104                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1105                                 };
1106                                 pd_vo@RK3399_PD_VO {
1107                                         reg = <RK3399_PD_VO>;
1108                                         #address-cells = <1>;
1109                                         #size-cells = <0>;
1110
1111                                         pd_vopb@RK3399_PD_VOPB {
1112                                                 reg = <RK3399_PD_VOPB>;
1113                                                 clocks = <&cru ACLK_VOP0>,
1114                                                          <&cru HCLK_VOP0>;
1115                                                 pm_qos = <&qos_vop_big_r>,
1116                                                          <&qos_vop_big_w>;
1117                                         };
1118                                         pd_vopl@RK3399_PD_VOPL {
1119                                                 reg = <RK3399_PD_VOPL>;
1120                                                 clocks = <&cru ACLK_VOP1>,
1121                                                          <&cru HCLK_VOP1>;
1122                                                 pm_qos = <&qos_vop_little>;
1123                                         };
1124                                 };
1125                         };
1126                 };
1127         };
1128
1129         pmugrf: syscon@ff320000 {
1130                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1131                 reg = <0x0 0xff320000 0x0 0x1000>;
1132
1133                 reboot-mode {
1134                         compatible = "syscon-reboot-mode";
1135                         offset = <0x300>;
1136                         mode-bootloader = <BOOT_LOADER>;
1137                         mode-charge = <BOOT_CHARGING>;
1138                         mode-fastboot = <BOOT_FASTBOOT>;
1139                         mode-loader = <BOOT_LOADER>;
1140                         mode-normal = <BOOT_NORMAL>;
1141                         mode-recovery = <BOOT_RECOVERY>;
1142                         mode-ums = <BOOT_UMS>;
1143                 };
1144
1145                 pmu_pvtm: pmu-pvtm {
1146                         compatible = "rockchip,rk3399-pmu-pvtm";
1147                         clocks = <&pmucru SCLK_PVTM_PMU>;
1148                         clock-names = "pmu";
1149                         status = "disabled";
1150                 };
1151         };
1152
1153         spi3: spi@ff350000 {
1154                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1155                 reg = <0x0 0xff350000 0x0 0x1000>;
1156                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1157                 clock-names = "spiclk", "apb_pclk";
1158                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1159                 pinctrl-names = "default";
1160                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1161                 #address-cells = <1>;
1162                 #size-cells = <0>;
1163                 status = "disabled";
1164         };
1165
1166         uart4: serial@ff370000 {
1167                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1168                 reg = <0x0 0xff370000 0x0 0x100>;
1169                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1170                 clock-names = "baudclk", "apb_pclk";
1171                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1172                 reg-shift = <2>;
1173                 reg-io-width = <4>;
1174                 pinctrl-names = "default";
1175                 pinctrl-0 = <&uart4_xfer>;
1176                 status = "disabled";
1177         };
1178
1179         i2c4: i2c@ff3d0000 {
1180                 compatible = "rockchip,rk3399-i2c";
1181                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1182                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1183                 clock-names = "i2c", "pclk";
1184                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1185                 pinctrl-names = "default";
1186                 pinctrl-0 = <&i2c4_xfer>;
1187                 #address-cells = <1>;
1188                 #size-cells = <0>;
1189                 status = "disabled";
1190         };
1191
1192         i2c8: i2c@ff3e0000 {
1193                 compatible = "rockchip,rk3399-i2c";
1194                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1195                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1196                 clock-names = "i2c", "pclk";
1197                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1198                 pinctrl-names = "default";
1199                 pinctrl-0 = <&i2c8_xfer>;
1200                 #address-cells = <1>;
1201                 #size-cells = <0>;
1202                 status = "disabled";
1203         };
1204
1205         pcie_phy: phy@e220 {
1206                 compatible = "rockchip,rk3399-pcie-phy";
1207                 #phy-cells = <0>;
1208                 rockchip,grf = <&grf>;
1209                 clocks = <&cru SCLK_PCIEPHY_REF>;
1210                 clock-names = "refclk";
1211                 resets = <&cru SRST_PCIEPHY>;
1212                 reset-names = "phy";
1213                 status = "disabled";
1214         };
1215
1216         pcie0: pcie@f8000000 {
1217                 compatible = "rockchip,rk3399-pcie";
1218                 #address-cells = <3>;
1219                 #size-cells = <2>;
1220                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1221                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1222                 clock-names = "aclk", "aclk-perf",
1223                               "hclk", "pm";
1224                 bus-range = <0x0 0x1>;
1225                 msi-map = <0x0 &its 0x0 0x1000>;
1226                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1227                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1228                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1229                 interrupt-names = "sys", "legacy", "client";
1230                 #interrupt-cells = <1>;
1231                 interrupt-map-mask = <0 0 0 7>;
1232                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1233                                 <0 0 0 2 &pcie0_intc 1>,
1234                                 <0 0 0 3 &pcie0_intc 2>,
1235                                 <0 0 0 4 &pcie0_intc 3>;
1236                 phys = <&pcie_phy>;
1237                 phy-names = "pcie-phy";
1238                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1239                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1240                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1241                       <0x0 0xfd000000 0x0 0x1000000>;
1242                 reg-names = "axi-base", "apb-base";
1243                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1244                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1245                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1246                 status = "disabled";
1247                 pcie0_intc: interrupt-controller {
1248                         interrupt-controller;
1249                         #address-cells = <0>;
1250                         #interrupt-cells = <1>;
1251                 };
1252         };
1253
1254         pwm0: pwm@ff420000 {
1255                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1256                 reg = <0x0 0xff420000 0x0 0x10>;
1257                 #pwm-cells = <3>;
1258                 pinctrl-names = "default";
1259                 pinctrl-0 = <&pwm0_pin>;
1260                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1261                 clock-names = "pwm";
1262                 status = "disabled";
1263         };
1264
1265         pwm1: pwm@ff420010 {
1266                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1267                 reg = <0x0 0xff420010 0x0 0x10>;
1268                 #pwm-cells = <3>;
1269                 pinctrl-names = "default";
1270                 pinctrl-0 = <&pwm1_pin>;
1271                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1272                 clock-names = "pwm";
1273                 status = "disabled";
1274         };
1275
1276         pwm2: pwm@ff420020 {
1277                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1278                 reg = <0x0 0xff420020 0x0 0x10>;
1279                 #pwm-cells = <3>;
1280                 pinctrl-names = "default";
1281                 pinctrl-0 = <&pwm2_pin>;
1282                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1283                 clock-names = "pwm";
1284                 status = "disabled";
1285         };
1286
1287         pwm3: pwm@ff420030 {
1288                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1289                 reg = <0x0 0xff420030 0x0 0x10>;
1290                 #pwm-cells = <3>;
1291                 pinctrl-names = "default";
1292                 pinctrl-0 = <&pwm3a_pin>;
1293                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1294                 clock-names = "pwm";
1295                 status = "disabled";
1296         };
1297
1298         dfi: dfi@ff630000 {
1299                 reg = <0x00 0xff630000 0x00 0x4000>;
1300                 compatible = "rockchip,rk3399-dfi";
1301                 rockchip,pmu = <&pmugrf>;
1302                 clocks = <&cru PCLK_DDR_MON>;
1303                 clock-names = "pclk_ddr_mon";
1304                 status = "disabled";
1305         };
1306
1307         dmc: dmc {
1308                 compatible = "rockchip,rk3399-dmc";
1309                 devfreq-events = <&dfi>;
1310                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1311                 clocks = <&cru SCLK_DDRCLK>;
1312                 clock-names = "dmc_clk";
1313                 ddr_timing = <&ddr_timing>;
1314                 operating-points-v2 = <&dmc_opp_table>;
1315                 status = "disabled";
1316         };
1317
1318         dmc_opp_table: dmc_opp_table {
1319                 compatible = "operating-points-v2";
1320
1321                 opp00 {
1322                         opp-hz = /bits/ 64 <666000000>;
1323                         opp-microvolt = <900000>;
1324                 };
1325         };
1326
1327         rga: rga@ff680000 {
1328                 compatible = "rockchip,rk3399-rga";
1329                 reg = <0x0 0xff680000 0x0 0x10000>;
1330                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1331                 interrupt-names = "rga";
1332                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1333                 clock-names = "aclk", "hclk", "sclk";
1334                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1335                 reset-names = "core", "axi", "ahb";
1336                 power-domains = <&power RK3399_PD_RGA>;
1337                 status = "disabled";
1338         };
1339
1340         efuse0: efuse@ff690000 {
1341                 compatible = "rockchip,rk3399-efuse";
1342                 reg = <0x0 0xff690000 0x0 0x80>;
1343                 #address-cells = <1>;
1344                 #size-cells = <1>;
1345                 clocks = <&cru PCLK_EFUSE1024NS>;
1346                 clock-names = "pclk_efuse";
1347
1348                 /* Data cells */
1349                 cpul_leakage: cpul-leakage {
1350                         reg = <0x1a 0x1>;
1351                 };
1352                 cpub_leakage: cpub-leakage {
1353                         reg = <0x17 0x1>;
1354                 };
1355                 gpu_leakage: gpu-leakage {
1356                         reg = <0x18 0x1>;
1357                 };
1358                 center_leakage: center-leakage {
1359                         reg = <0x19 0x1>;
1360                 };
1361                 logic_leakage: logic-leakage {
1362                         reg = <0x1b 0x1>;
1363                 };
1364                 wafer_info: wafer-info {
1365                         reg = <0x1c 0x1>;
1366                 };
1367         };
1368
1369         pmucru: pmu-clock-controller@ff750000 {
1370                 compatible = "rockchip,rk3399-pmucru";
1371                 reg = <0x0 0xff750000 0x0 0x1000>;
1372                 #clock-cells = <1>;
1373                 #reset-cells = <1>;
1374                 assigned-clocks = <&pmucru PLL_PPLL>;
1375                 assigned-clock-rates = <676000000>;
1376         };
1377
1378         cru: clock-controller@ff760000 {
1379                 compatible = "rockchip,rk3399-cru";
1380                 reg = <0x0 0xff760000 0x0 0x1000>;
1381                 #clock-cells = <1>;
1382                 #reset-cells = <1>;
1383                 assigned-clocks =
1384                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1385                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1386                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1387                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1388                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1389                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1390                         <&cru PCLK_PERIHP>,
1391                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1392                         <&cru PCLK_PERILP0>,
1393                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1394                 assigned-clock-rates =
1395                          <400000000>,  <200000000>,
1396                          <400000000>,  <200000000>,
1397                          <816000000>, <816000000>,
1398                          <594000000>,  <800000000>,
1399                          <200000000>, <1000000000>,
1400                          <150000000>,   <75000000>,
1401                           <37500000>,
1402                          <100000000>,  <100000000>,
1403                           <50000000>,
1404                          <100000000>,   <50000000>;
1405         };
1406
1407         grf: syscon@ff770000 {
1408                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1409                 reg = <0x0 0xff770000 0x0 0x10000>;
1410                 #address-cells = <1>;
1411                 #size-cells = <1>;
1412
1413                 emmc_phy: phy@f780 {
1414                         compatible = "rockchip,rk3399-emmc-phy";
1415                         reg = <0xf780 0x24>;
1416                         clocks = <&sdhci>;
1417                         clock-names = "emmcclk";
1418                         #phy-cells = <0>;
1419                         status = "disabled";
1420                 };
1421
1422                 u2phy0: usb2-phy@e450 {
1423                         compatible = "rockchip,rk3399-usb2phy";
1424                         reg = <0xe450 0x10>;
1425                         clocks = <&cru SCLK_USB2PHY0_REF>;
1426                         clock-names = "phyclk";
1427                         #clock-cells = <0>;
1428                         clock-output-names = "clk_usbphy0_480m";
1429                         status = "disabled";
1430
1431                         u2phy0_otg: otg-port {
1432                                 #phy-cells = <0>;
1433                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1434                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1435                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1436                                 interrupt-names = "otg-bvalid", "otg-id",
1437                                                   "linestate";
1438                                 status = "disabled";
1439                         };
1440
1441                         u2phy0_host: host-port {
1442                                 #phy-cells = <0>;
1443                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1444                                 interrupt-names = "linestate";
1445                                 status = "disabled";
1446                         };
1447                 };
1448
1449                 u2phy1: usb2-phy@e460 {
1450                         compatible = "rockchip,rk3399-usb2phy";
1451                         reg = <0xe460 0x10>;
1452                         clocks = <&cru SCLK_USB2PHY1_REF>;
1453                         clock-names = "phyclk";
1454                         #clock-cells = <0>;
1455                         clock-output-names = "clk_usbphy1_480m";
1456                         status = "disabled";
1457
1458                         u2phy1_otg: otg-port {
1459                                 #phy-cells = <0>;
1460                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1461                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1462                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1463                                 interrupt-names = "otg-bvalid", "otg-id",
1464                                                   "linestate";
1465                                 status = "disabled";
1466                         };
1467
1468                         u2phy1_host: host-port {
1469                                 #phy-cells = <0>;
1470                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1471                                 interrupt-names = "linestate";
1472                                 status = "disabled";
1473                         };
1474                 };
1475
1476                 pvtm: pvtm {
1477                         compatible = "rockchip,rk3399-pvtm";
1478                         clocks = <&cru SCLK_PVTM_CORE_L>,
1479                                  <&cru SCLK_PVTM_CORE_B>,
1480                                  <&cru SCLK_PVTM_GPU>,
1481                                  <&cru SCLK_PVTM_DDR>;
1482                         clock-names = "core_l", "core_b", "gpu", "ddr";
1483                         status = "disabled";
1484                 };
1485         };
1486
1487         tcphy0: phy@ff7c0000 {
1488                 compatible = "rockchip,rk3399-typec-phy";
1489                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1490                 rockchip,grf = <&grf>;
1491                 #phy-cells = <1>;
1492                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1493                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1494                 clock-names = "tcpdcore", "tcpdphy-ref";
1495                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1496                 assigned-clock-rates = <50000000>;
1497                 power-domains = <&power RK3399_PD_TCPD0>;
1498                 resets = <&cru SRST_UPHY0>,
1499                          <&cru SRST_UPHY0_PIPE_L00>,
1500                          <&cru SRST_P_UPHY0_TCPHY>;
1501                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1502                 rockchip,typec-conn-dir = <0xe580 0 16>;
1503                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1504                 rockchip,usb3-host-disable = <0x2434 0 16>;
1505                 rockchip,usb3-host-port = <0x2434 12 28>;
1506                 rockchip,external-psm = <0xe588 14 30>;
1507                 rockchip,pipe-status = <0xe5c0 0 0>;
1508                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1509                 status = "disabled";
1510
1511                 tcphy0_dp: dp-port {
1512                         #phy-cells = <0>;
1513                 };
1514
1515                 tcphy0_usb3: usb3-port {
1516                         #phy-cells = <0>;
1517                 };
1518         };
1519
1520         tcphy1: phy@ff800000 {
1521                 compatible = "rockchip,rk3399-typec-phy";
1522                 reg = <0x0 0xff800000 0x0 0x40000>;
1523                 rockchip,grf = <&grf>;
1524                 #phy-cells = <1>;
1525                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1526                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1527                 clock-names = "tcpdcore", "tcpdphy-ref";
1528                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1529                 assigned-clock-rates = <50000000>;
1530                 power-domains = <&power RK3399_PD_TCPD1>;
1531                 resets = <&cru SRST_UPHY1>,
1532                          <&cru SRST_UPHY1_PIPE_L00>,
1533                          <&cru SRST_P_UPHY1_TCPHY>;
1534                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1535                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1536                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1537                 rockchip,usb3-host-disable = <0x2444 0 16>;
1538                 rockchip,usb3-host-port = <0x2444 12 28>;
1539                 rockchip,external-psm = <0xe594 14 30>;
1540                 rockchip,pipe-status = <0xe5c0 16 16>;
1541                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1542                 status = "disabled";
1543
1544                 tcphy1_dp: dp-port {
1545                         #phy-cells = <0>;
1546                 };
1547
1548                 tcphy1_usb3: usb3-port {
1549                         #phy-cells = <0>;
1550                 };
1551         };
1552
1553         watchdog@ff848000 {
1554                 compatible = "snps,dw-wdt";
1555                 reg = <0x0 0xff848000 0x0 0x100>;
1556                 clocks = <&cru PCLK_WDT>;
1557                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1558         };
1559
1560         rktimer: rktimer@ff850000 {
1561                 compatible = "rockchip,rk3399-timer";
1562                 reg = <0x0 0xff850000 0x0 0x1000>;
1563                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1564                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1565                 clock-names = "pclk", "timer";
1566         };
1567
1568         spdif: spdif@ff870000 {
1569                 compatible = "rockchip,rk3399-spdif";
1570                 reg = <0x0 0xff870000 0x0 0x1000>;
1571                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1572                 dmas = <&dmac_bus 7>;
1573                 dma-names = "tx";
1574                 clock-names = "mclk", "hclk";
1575                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1576                 pinctrl-names = "default";
1577                 pinctrl-0 = <&spdif_bus>;
1578                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1579                 status = "disabled";
1580         };
1581
1582         i2s0: i2s@ff880000 {
1583                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1584                 reg = <0x0 0xff880000 0x0 0x1000>;
1585                 rockchip,grf = <&grf>;
1586                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1587                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1588                 dma-names = "tx", "rx";
1589                 clock-names = "i2s_clk", "i2s_hclk";
1590                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1591                 pinctrl-names = "default";
1592                 pinctrl-0 = <&i2s0_8ch_bus>;
1593                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1594                 status = "disabled";
1595         };
1596
1597         i2s1: i2s@ff890000 {
1598                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1599                 reg = <0x0 0xff890000 0x0 0x1000>;
1600                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1601                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1602                 dma-names = "tx", "rx";
1603                 clock-names = "i2s_clk", "i2s_hclk";
1604                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1605                 pinctrl-names = "default";
1606                 pinctrl-0 = <&i2s1_2ch_bus>;
1607                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1608                 status = "disabled";
1609         };
1610
1611         i2s2: i2s@ff8a0000 {
1612                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1613                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1614                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1615                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1616                 dma-names = "tx", "rx";
1617                 clock-names = "i2s_clk", "i2s_hclk";
1618                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1619                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1620                 status = "disabled";
1621         };
1622
1623         gpu: gpu@ff9a0000 {
1624                 compatible = "arm,malit860",
1625                              "arm,malit86x",
1626                              "arm,malit8xx",
1627                              "arm,mali-midgard";
1628
1629                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1630
1631                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1632                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1633                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1634                 interrupt-names = "GPU", "JOB", "MMU";
1635
1636                 clocks = <&cru ACLK_GPU>;
1637                 clock-names = "clk_mali";
1638                 #cooling-cells = <2>; /* min followed by max */
1639                 operating-points-v2 = <&gpu_opp_table>;
1640                 power-domains = <&power RK3399_PD_GPU>;
1641                 power-off-delay-ms = <200>;
1642                 status = "disabled";
1643
1644                 gpu_power_model: power_model {
1645                         compatible = "arm,mali-simple-power-model";
1646                         voltage = <900>;
1647                         frequency = <500>;
1648                         static-power = <300>;
1649                         dynamic-power = <396>;
1650                         ts = <32000 4700 (-80) 2>;
1651                         thermal-zone = "gpu-thermal";
1652                 };
1653         };
1654
1655         gpu_opp_table: gpu_opp_table {
1656                 compatible = "operating-points-v2";
1657                 opp-shared;
1658
1659                 opp@200000000 {
1660                         opp-hz = /bits/ 64 <200000000>;
1661                         opp-microvolt = <900000>;
1662                 };
1663                 opp@300000000 {
1664                         opp-hz = /bits/ 64 <300000000>;
1665                         opp-microvolt = <900000>;
1666                 };
1667                 opp@400000000 {
1668                         opp-hz = /bits/ 64 <400000000>;
1669                         opp-microvolt = <900000>;
1670                 };
1671
1672         };
1673
1674         vopl: vop@ff8f0000 {
1675                 compatible = "rockchip,rk3399-vop-lit";
1676                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1677                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1678                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1679                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1680                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1681                 reset-names = "axi", "ahb", "dclk";
1682                 power-domains = <&power RK3399_PD_VOPL>;
1683                 iommus = <&vopl_mmu>;
1684                 status = "disabled";
1685
1686                 vopl_out: port {
1687                         #address-cells = <1>;
1688                         #size-cells = <0>;
1689
1690                         vopl_out_mipi: endpoint@0 {
1691                                 reg = <0>;
1692                                 remote-endpoint = <&mipi_in_vopl>;
1693                         };
1694
1695                         vopl_out_edp: endpoint@1 {
1696                                 reg = <1>;
1697                                 remote-endpoint = <&edp_in_vopl>;
1698                         };
1699
1700                         vopl_out_hdmi: endpoint@2 {
1701                                 reg = <2>;
1702                                 remote-endpoint = <&hdmi_in_vopl>;
1703                         };
1704                 };
1705         };
1706
1707         vop1_pwm: voppwm@ff8f01a0 {
1708                 compatible = "rockchip,vop-pwm";
1709                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1710                 #pwm-cells = <3>;
1711                 pinctrl-names = "default";
1712                 pinctrl-0 = <&vop1_pwm_pin>;
1713                 clocks = <&cru SCLK_VOP1_PWM>;
1714                 clock-names = "pwm";
1715                 status = "disabled";
1716         };
1717
1718         vopl_mmu: iommu@ff8f3f00 {
1719                 compatible = "rockchip,iommu";
1720                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1721                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1722                 interrupt-names = "vopl_mmu";
1723                 #iommu-cells = <0>;
1724                 status = "disabled";
1725         };
1726
1727         vopb: vop@ff900000 {
1728                 compatible = "rockchip,rk3399-vop-big";
1729                 reg = <0x0 0xff900000 0x0 0x3efc>;
1730                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1731                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1732                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1733                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1734                 reset-names = "axi", "ahb", "dclk";
1735                 power-domains = <&power RK3399_PD_VOPB>;
1736                 iommus = <&vopb_mmu>;
1737                 status = "disabled";
1738
1739                 vopb_out: port {
1740                         #address-cells = <1>;
1741                         #size-cells = <0>;
1742
1743                         vopb_out_edp: endpoint@0 {
1744                                 reg = <0>;
1745                                 remote-endpoint = <&edp_in_vopb>;
1746                         };
1747
1748                         vopb_out_mipi: endpoint@1 {
1749                                 reg = <1>;
1750                                 remote-endpoint = <&mipi_in_vopb>;
1751                         };
1752
1753                         vopb_out_hdmi: endpoint@2 {
1754                                 reg = <2>;
1755                                 remote-endpoint = <&hdmi_in_vopb>;
1756                         };
1757                 };
1758         };
1759
1760         vop0_pwm: voppwm@ff9001a0 {
1761                 compatible = "rockchip,vop-pwm";
1762                 reg = <0x0 0xff9001a0 0x0 0x10>;
1763                 #pwm-cells = <3>;
1764                 pinctrl-names = "default";
1765                 pinctrl-0 = <&vop0_pwm_pin>;
1766                 clocks = <&cru SCLK_VOP0_PWM>;
1767                 clock-names = "pwm";
1768                 status = "disabled";
1769         };
1770
1771         vopb_mmu: iommu@ff903f00 {
1772                 compatible = "rockchip,iommu";
1773                 reg = <0x0 0xff903f00 0x0 0x100>;
1774                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1775                 interrupt-names = "vopb_mmu";
1776                 #iommu-cells = <0>;
1777                 status = "disabled";
1778         };
1779
1780         hdmi: hdmi@ff940000 {
1781                 compatible = "rockchip,rk3399-dw-hdmi";
1782                 reg = <0x0 0xff940000 0x0 0x20000>;
1783                 reg-io-width = <4>;
1784                 rockchip,grf = <&grf>;
1785                 power-domains = <&power RK3399_PD_HDCP>;
1786                 pinctrl-names = "default";
1787                 pinctrl-0 = <&hdmi_i2c_xfer>;
1788                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1789                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1790                 clock-names = "iahb", "isfr", "vpll", "grf";
1791                 status = "disabled";
1792
1793                 ports {
1794                         hdmi_in: port {
1795                                 #address-cells = <1>;
1796                                 #size-cells = <0>;
1797                                 hdmi_in_vopb: endpoint@0 {
1798                                         reg = <0>;
1799                                         remote-endpoint = <&vopb_out_hdmi>;
1800                                 };
1801                                 hdmi_in_vopl: endpoint@1 {
1802                                         reg = <1>;
1803                                         remote-endpoint = <&vopl_out_hdmi>;
1804                                 };
1805                         };
1806                 };
1807         };
1808
1809         mipi_dsi: mipi@ff960000 {
1810                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1811                 reg = <0x0 0xff960000 0x0 0x8000>;
1812                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1813                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1814                          <&cru SCLK_DPHY_TX0_CFG>;
1815                 clock-names = "ref", "pclk", "phy_cfg";
1816                 power-domains = <&power RK3399_PD_VIO>;
1817                 rockchip,grf = <&grf>;
1818                 #address-cells = <1>;
1819                 #size-cells = <0>;
1820                 status = "disabled";
1821
1822                 ports {
1823                         #address-cells = <1>;
1824                         #size-cells = <0>;
1825                         reg = <1>;
1826
1827                         mipi_in: port {
1828                                 #address-cells = <1>;
1829                                 #size-cells = <0>;
1830
1831                                 mipi_in_vopb: endpoint@0 {
1832                                         reg = <0>;
1833                                         remote-endpoint = <&vopb_out_mipi>;
1834                                 };
1835                                 mipi_in_vopl: endpoint@1 {
1836                                         reg = <1>;
1837                                         remote-endpoint = <&vopl_out_mipi>;
1838                                 };
1839                         };
1840                 };
1841         };
1842
1843         edp: edp@ff970000 {
1844                 compatible = "rockchip,rk3399-edp";
1845                 reg = <0x0 0xff970000 0x0 0x8000>;
1846                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1847                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1848                 clock-names = "dp", "pclk";
1849                 power-domains = <&power RK3399_PD_EDP>;
1850                 resets = <&cru SRST_P_EDP_CTRL>;
1851                 reset-names = "dp";
1852                 rockchip,grf = <&grf>;
1853                 status = "disabled";
1854                 pinctrl-names = "default";
1855                 pinctrl-0 = <&edp_hpd>;
1856
1857                 ports {
1858                         #address-cells = <1>;
1859                         #size-cells = <0>;
1860
1861                         edp_in: port@0 {
1862                                 reg = <0>;
1863                                 #address-cells = <1>;
1864                                 #size-cells = <0>;
1865
1866                                 edp_in_vopb: endpoint@0 {
1867                                         reg = <0>;
1868                                         remote-endpoint = <&vopb_out_edp>;
1869                                 };
1870
1871                                 edp_in_vopl: endpoint@1 {
1872                                         reg = <1>;
1873                                         remote-endpoint = <&vopl_out_edp>;
1874                                 };
1875                         };
1876                 };
1877         };
1878
1879         display_subsystem: display-subsystem {
1880                 compatible = "rockchip,display-subsystem";
1881                 ports = <&vopl_out>, <&vopb_out>;
1882                 status = "disabled";
1883         };
1884
1885         pinctrl: pinctrl {
1886                 compatible = "rockchip,rk3399-pinctrl";
1887                 rockchip,grf = <&grf>;
1888                 rockchip,pmu = <&pmugrf>;
1889                 #address-cells = <0x2>;
1890                 #size-cells = <0x2>;
1891                 ranges;
1892
1893                 gpio0: gpio0@ff720000 {
1894                         compatible = "rockchip,gpio-bank";
1895                         reg = <0x0 0xff720000 0x0 0x100>;
1896                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1897                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1898
1899                         gpio-controller;
1900                         #gpio-cells = <0x2>;
1901
1902                         interrupt-controller;
1903                         #interrupt-cells = <0x2>;
1904                 };
1905
1906                 gpio1: gpio1@ff730000 {
1907                         compatible = "rockchip,gpio-bank";
1908                         reg = <0x0 0xff730000 0x0 0x100>;
1909                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1910                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1911
1912                         gpio-controller;
1913                         #gpio-cells = <0x2>;
1914
1915                         interrupt-controller;
1916                         #interrupt-cells = <0x2>;
1917                 };
1918
1919                 gpio2: gpio2@ff780000 {
1920                         compatible = "rockchip,gpio-bank";
1921                         reg = <0x0 0xff780000 0x0 0x100>;
1922                         clocks = <&cru PCLK_GPIO2>;
1923                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1924
1925                         gpio-controller;
1926                         #gpio-cells = <0x2>;
1927
1928                         interrupt-controller;
1929                         #interrupt-cells = <0x2>;
1930                 };
1931
1932                 gpio3: gpio3@ff788000 {
1933                         compatible = "rockchip,gpio-bank";
1934                         reg = <0x0 0xff788000 0x0 0x100>;
1935                         clocks = <&cru PCLK_GPIO3>;
1936                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1937
1938                         gpio-controller;
1939                         #gpio-cells = <0x2>;
1940
1941                         interrupt-controller;
1942                         #interrupt-cells = <0x2>;
1943                 };
1944
1945                 gpio4: gpio4@ff790000 {
1946                         compatible = "rockchip,gpio-bank";
1947                         reg = <0x0 0xff790000 0x0 0x100>;
1948                         clocks = <&cru PCLK_GPIO4>;
1949                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1950
1951                         gpio-controller;
1952                         #gpio-cells = <0x2>;
1953
1954                         interrupt-controller;
1955                         #interrupt-cells = <0x2>;
1956                 };
1957
1958                 pcfg_pull_up: pcfg-pull-up {
1959                         bias-pull-up;
1960                 };
1961
1962                 pcfg_pull_down: pcfg-pull-down {
1963                         bias-pull-down;
1964                 };
1965
1966                 pcfg_pull_none: pcfg-pull-none {
1967                         bias-disable;
1968                 };
1969
1970                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1971                         bias-pull-up;
1972                         drive-strength = <20>;
1973                 };
1974
1975                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1976                         bias-disable;
1977                         drive-strength = <20>;
1978                 };
1979
1980                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1981                         bias-disable;
1982                         drive-strength = <18>;
1983                 };
1984
1985                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1986                         bias-disable;
1987                         drive-strength = <12>;
1988                 };
1989
1990                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1991                         bias-pull-up;
1992                         drive-strength = <8>;
1993                 };
1994
1995                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1996                         bias-pull-down;
1997                         drive-strength = <4>;
1998                 };
1999
2000                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2001                         bias-pull-up;
2002                         drive-strength = <2>;
2003                 };
2004
2005                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2006                         bias-pull-down;
2007                         drive-strength = <12>;
2008                 };
2009
2010                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2011                         bias-disable;
2012                         drive-strength = <13>;
2013                 };
2014
2015                 pcfg_output_high: pcfg-output-high {
2016                         output-high;
2017                 };
2018
2019                 pcfg_output_low: pcfg-output-low {
2020                         output-low;
2021                 };
2022
2023                 pcfg_input: pcfg-input {
2024                         input-enable;
2025                 };
2026
2027                 emmc {
2028                         emmc_pwr: emmc-pwr {
2029                                 rockchip,pins =
2030                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
2031                         };
2032                 };
2033
2034                 gmac {
2035                         rgmii_pins: rgmii-pins {
2036                                 rockchip,pins =
2037                                         /* mac_txclk */
2038                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2039                                         /* mac_rxclk */
2040                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2041                                         /* mac_mdio */
2042                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2043                                         /* mac_txen */
2044                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2045                                         /* mac_clk */
2046                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2047                                         /* mac_rxdv */
2048                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2049                                         /* mac_mdc */
2050                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2051                                         /* mac_rxd1 */
2052                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2053                                         /* mac_rxd0 */
2054                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2055                                         /* mac_txd1 */
2056                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2057                                         /* mac_txd0 */
2058                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2059                                         /* mac_rxd3 */
2060                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2061                                         /* mac_rxd2 */
2062                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2063                                         /* mac_txd3 */
2064                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2065                                         /* mac_txd2 */
2066                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2067                         };
2068
2069                         rmii_pins: rmii-pins {
2070                                 rockchip,pins =
2071                                         /* mac_mdio */
2072                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2073                                         /* mac_txen */
2074                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2075                                         /* mac_clk */
2076                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2077                                         /* mac_rxer */
2078                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2079                                         /* mac_rxdv */
2080                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2081                                         /* mac_mdc */
2082                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2083                                         /* mac_rxd1 */
2084                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2085                                         /* mac_rxd0 */
2086                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2087                                         /* mac_txd1 */
2088                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2089                                         /* mac_txd0 */
2090                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2091                         };
2092                 };
2093
2094                 i2c0 {
2095                         i2c0_xfer: i2c0-xfer {
2096                                 rockchip,pins =
2097                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2098                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2099                         };
2100                 };
2101
2102                 i2c1 {
2103                         i2c1_xfer: i2c1-xfer {
2104                                 rockchip,pins =
2105                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2106                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2107                         };
2108                 };
2109
2110                 i2c2 {
2111                         i2c2_xfer: i2c2-xfer {
2112                                 rockchip,pins =
2113                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2114                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2115                         };
2116                 };
2117
2118                 i2c3 {
2119                         i2c3_xfer: i2c3-xfer {
2120                                 rockchip,pins =
2121                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2122                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2123                         };
2124
2125                         i2c3_gpio: i2c3_gpio {
2126                                 rockchip,pins =
2127                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2128                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2129                         };
2130
2131                 };
2132
2133                 i2c4 {
2134                         i2c4_xfer: i2c4-xfer {
2135                                 rockchip,pins =
2136                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2137                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2138                         };
2139                 };
2140
2141                 i2c5 {
2142                         i2c5_xfer: i2c5-xfer {
2143                                 rockchip,pins =
2144                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2145                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2146                         };
2147                 };
2148
2149                 i2c6 {
2150                         i2c6_xfer: i2c6-xfer {
2151                                 rockchip,pins =
2152                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2153                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2154                         };
2155                 };
2156
2157                 i2c7 {
2158                         i2c7_xfer: i2c7-xfer {
2159                                 rockchip,pins =
2160                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2161                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2162                         };
2163                 };
2164
2165                 i2c8 {
2166                         i2c8_xfer: i2c8-xfer {
2167                                 rockchip,pins =
2168                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2169                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2170                         };
2171                 };
2172
2173                 i2s0 {
2174                         i2s0_8ch_bus: i2s0-8ch-bus {
2175                                 rockchip,pins =
2176                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2177                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2178                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2179                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2180                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2181                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2182                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2183                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2184                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2185                         };
2186                 };
2187
2188                 i2s1 {
2189                         i2s1_2ch_bus: i2s1-2ch-bus {
2190                                 rockchip,pins =
2191                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2192                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2193                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2194                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2195                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2196                         };
2197                 };
2198
2199                 sdio0 {
2200                         sdio0_bus1: sdio0-bus1 {
2201                                 rockchip,pins =
2202                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2203                         };
2204
2205                         sdio0_bus4: sdio0-bus4 {
2206                                 rockchip,pins =
2207                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2208                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2209                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2210                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2211                         };
2212
2213                         sdio0_cmd: sdio0-cmd {
2214                                 rockchip,pins =
2215                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2216                         };
2217
2218                         sdio0_clk: sdio0-clk {
2219                                 rockchip,pins =
2220                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2221                         };
2222
2223                         sdio0_cd: sdio0-cd {
2224                                 rockchip,pins =
2225                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2226                         };
2227
2228                         sdio0_pwr: sdio0-pwr {
2229                                 rockchip,pins =
2230                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2231                         };
2232
2233                         sdio0_bkpwr: sdio0-bkpwr {
2234                                 rockchip,pins =
2235                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2236                         };
2237
2238                         sdio0_wp: sdio0-wp {
2239                                 rockchip,pins =
2240                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2241                         };
2242
2243                         sdio0_int: sdio0-int {
2244                                 rockchip,pins =
2245                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2246                         };
2247                 };
2248
2249                 sdmmc {
2250                         sdmmc_bus1: sdmmc-bus1 {
2251                                 rockchip,pins =
2252                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2253                         };
2254
2255                         sdmmc_bus4: sdmmc-bus4 {
2256                                 rockchip,pins =
2257                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2258                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2259                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2260                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2261                         };
2262
2263                         sdmmc_clk: sdmmc-clk {
2264                                 rockchip,pins =
2265                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2266                         };
2267
2268                         sdmmc_cmd: sdmmc-cmd {
2269                                 rockchip,pins =
2270                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2271                         };
2272
2273                         sdmmc_cd: sdmcc-cd {
2274                                 rockchip,pins =
2275                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2276                         };
2277
2278                         sdmmc_wp: sdmmc-wp {
2279                                 rockchip,pins =
2280                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2281                         };
2282                 };
2283
2284                 spdif {
2285                         spdif_bus: spdif-bus {
2286                                 rockchip,pins =
2287                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2288                         };
2289
2290                         spdif_bus_1: spdif-bus-1 {
2291                                 rockchip,pins =
2292                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2293                         };
2294                 };
2295
2296                 spi0 {
2297                         spi0_clk: spi0-clk {
2298                                 rockchip,pins =
2299                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2300                         };
2301                         spi0_cs0: spi0-cs0 {
2302                                 rockchip,pins =
2303                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2304                         };
2305                         spi0_cs1: spi0-cs1 {
2306                                 rockchip,pins =
2307                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2308                         };
2309                         spi0_tx: spi0-tx {
2310                                 rockchip,pins =
2311                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2312                         };
2313                         spi0_rx: spi0-rx {
2314                                 rockchip,pins =
2315                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2316                         };
2317                 };
2318
2319                 spi1 {
2320                         spi1_clk: spi1-clk {
2321                                 rockchip,pins =
2322                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2323                         };
2324                         spi1_cs0: spi1-cs0 {
2325                                 rockchip,pins =
2326                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2327                         };
2328                         spi1_rx: spi1-rx {
2329                                 rockchip,pins =
2330                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2331                         };
2332                         spi1_tx: spi1-tx {
2333                                 rockchip,pins =
2334                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2335                         };
2336                 };
2337
2338                 spi2 {
2339                         spi2_clk: spi2-clk {
2340                                 rockchip,pins =
2341                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2342                         };
2343                         spi2_cs0: spi2-cs0 {
2344                                 rockchip,pins =
2345                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2346                         };
2347                         spi2_rx: spi2-rx {
2348                                 rockchip,pins =
2349                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2350                         };
2351                         spi2_tx: spi2-tx {
2352                                 rockchip,pins =
2353                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2354                         };
2355                 };
2356
2357                 spi3 {
2358                         spi3_clk: spi3-clk {
2359                                 rockchip,pins =
2360                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2361                         };
2362                         spi3_cs0: spi3-cs0 {
2363                                 rockchip,pins =
2364                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2365                         };
2366                         spi3_rx: spi3-rx {
2367                                 rockchip,pins =
2368                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2369                         };
2370                         spi3_tx: spi3-tx {
2371                                 rockchip,pins =
2372                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2373                         };
2374                 };
2375
2376                 spi4 {
2377                         spi4_clk: spi4-clk {
2378                                 rockchip,pins =
2379                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2380                         };
2381                         spi4_cs0: spi4-cs0 {
2382                                 rockchip,pins =
2383                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2384                         };
2385                         spi4_rx: spi4-rx {
2386                                 rockchip,pins =
2387                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2388                         };
2389                         spi4_tx: spi4-tx {
2390                                 rockchip,pins =
2391                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2392                         };
2393                 };
2394
2395                 spi5 {
2396                         spi5_clk: spi5-clk {
2397                                 rockchip,pins =
2398                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2399                         };
2400                         spi5_cs0: spi5-cs0 {
2401                                 rockchip,pins =
2402                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2403                         };
2404                         spi5_rx: spi5-rx {
2405                                 rockchip,pins =
2406                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2407                         };
2408                         spi5_tx: spi5-tx {
2409                                 rockchip,pins =
2410                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2411                         };
2412                 };
2413
2414                 tsadc {
2415                         otp_gpio: otp-gpio {
2416                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2417                         };
2418
2419                         otp_out: otp-out {
2420                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2421                         };
2422                 };
2423
2424                 uart0 {
2425                         uart0_xfer: uart0-xfer {
2426                                 rockchip,pins =
2427                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2428                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2429                         };
2430
2431                         uart0_cts: uart0-cts {
2432                                 rockchip,pins =
2433                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2434                         };
2435
2436                         uart0_rts: uart0-rts {
2437                                 rockchip,pins =
2438                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2439                         };
2440                 };
2441
2442                 uart1 {
2443                         uart1_xfer: uart1-xfer {
2444                                 rockchip,pins =
2445                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2446                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2447                         };
2448                 };
2449
2450                 uart2a {
2451                         uart2a_xfer: uart2a-xfer {
2452                                 rockchip,pins =
2453                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2454                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2455                         };
2456                 };
2457
2458                 uart2b {
2459                         uart2b_xfer: uart2b-xfer {
2460                                 rockchip,pins =
2461                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2462                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2463                         };
2464                 };
2465
2466                 uart2c {
2467                         uart2c_xfer: uart2c-xfer {
2468                                 rockchip,pins =
2469                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2470                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2471                         };
2472                 };
2473
2474                 uart3 {
2475                         uart3_xfer: uart3-xfer {
2476                                 rockchip,pins =
2477                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2478                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2479                         };
2480
2481                         uart3_cts: uart3-cts {
2482                                 rockchip,pins =
2483                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2484                         };
2485
2486                         uart3_rts: uart3-rts {
2487                                 rockchip,pins =
2488                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2489                         };
2490                 };
2491
2492                 uart4 {
2493                         uart4_xfer: uart4-xfer {
2494                                 rockchip,pins =
2495                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2496                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2497                         };
2498                 };
2499
2500                 uarthdcp {
2501                         uarthdcp_xfer: uarthdcp-xfer {
2502                                 rockchip,pins =
2503                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2504                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2505                         };
2506                 };
2507
2508                 pwm0 {
2509                         pwm0_pin: pwm0-pin {
2510                                 rockchip,pins =
2511                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2512                         };
2513
2514                         vop0_pwm_pin: vop0-pwm-pin {
2515                                 rockchip,pins =
2516                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2517                         };
2518                 };
2519
2520                 pwm1 {
2521                         pwm1_pin: pwm1-pin {
2522                                 rockchip,pins =
2523                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2524                         };
2525
2526                         vop1_pwm_pin: vop1-pwm-pin {
2527                                 rockchip,pins =
2528                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2529                         };
2530                 };
2531
2532                 pwm2 {
2533                         pwm2_pin: pwm2-pin {
2534                                 rockchip,pins =
2535                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2536                         };
2537                 };
2538
2539                 pwm3a {
2540                         pwm3a_pin: pwm3a-pin {
2541                                 rockchip,pins =
2542                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2543                         };
2544                 };
2545
2546                 pwm3b {
2547                         pwm3b_pin: pwm3b-pin {
2548                                 rockchip,pins =
2549                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2550                         };
2551                 };
2552
2553                 edp {
2554                         edp_hpd: edp-hpd {
2555                                 rockchip,pins =
2556                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2557                         };
2558                 };
2559
2560                 hdmi {
2561                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2562                                 rockchip,pins =
2563                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2564                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2565                         };
2566
2567                         hdmi_cec: hdmi-cec {
2568                                 rockchip,pins =
2569                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2570                         };
2571                 };
2572
2573                 pcie {
2574                         pcie_clkreqn: pci-clkreqn {
2575                                 rockchip,pins =
2576                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2577                         };
2578
2579                         pcie_clkreqnb: pci-clkreqnb {
2580                                 rockchip,pins =
2581                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2582                         };
2583                 };
2584         };
2585 };