2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3399";
55 interrupt-parent = <&gic>;
77 compatible = "arm,psci-1.0";
113 compatible = "arm,cortex-a53", "arm,armv8";
115 enable-method = "psci";
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <100>;
118 clocks = <&cru ARMCLKL>;
119 cpu-idle-states = <&cpu_sleep>;
120 operating-points-v2 = <&cluster0_opp>;
121 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 cpu-idle-states = <&cpu_sleep>;
131 operating-points-v2 = <&cluster0_opp>;
132 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 enable-method = "psci";
140 clocks = <&cru ARMCLKL>;
141 cpu-idle-states = <&cpu_sleep>;
142 operating-points-v2 = <&cluster0_opp>;
143 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 cpu-idle-states = <&cpu_sleep>;
153 operating-points-v2 = <&cluster0_opp>;
154 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
159 compatible = "arm,cortex-a72", "arm,armv8";
161 enable-method = "psci";
162 #cooling-cells = <2>; /* min followed by max */
163 dynamic-power-coefficient = <436>;
164 clocks = <&cru ARMCLKB>;
165 cpu-idle-states = <&cpu_sleep>;
166 operating-points-v2 = <&cluster1_opp>;
167 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
172 compatible = "arm,cortex-a72", "arm,armv8";
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 cpu-idle-states = <&cpu_sleep>;
177 operating-points-v2 = <&cluster1_opp>;
178 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
182 entry-method = "psci";
183 cpu_sleep: cpu-sleep-0 {
184 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x0010000>;
187 entry-latency-us = <350>;
188 exit-latency-us = <600>;
189 min-residency-us = <1150>;
193 /include/ "rk3399-sched-energy.dtsi"
197 cluster0_opp: opp_table0 {
198 compatible = "operating-points-v2";
202 opp-hz = /bits/ 64 <408000000>;
203 opp-microvolt = <800000>;
204 clock-latency-ns = <40000>;
207 opp-hz = /bits/ 64 <600000000>;
208 opp-microvolt = <800000>;
211 opp-hz = /bits/ 64 <816000000>;
212 opp-microvolt = <800000>;
215 opp-hz = /bits/ 64 <1008000000>;
216 opp-microvolt = <875000>;
219 opp-hz = /bits/ 64 <1200000000>;
220 opp-microvolt = <925000>;
223 opp-hz = /bits/ 64 <1416000000>;
224 opp-microvolt = <1025000>;
228 cluster1_opp: opp_table1 {
229 compatible = "operating-points-v2";
233 opp-hz = /bits/ 64 <408000000>;
234 opp-microvolt = <800000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <600000000>;
239 opp-microvolt = <800000>;
242 opp-hz = /bits/ 64 <816000000>;
243 opp-microvolt = <800000>;
246 opp-hz = /bits/ 64 <1008000000>;
247 opp-microvolt = <850000>;
250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <925000>;
256 compatible = "arm,armv8-timer";
257 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
258 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
259 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
260 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
264 compatible = "arm,cortex-a53-pmu";
265 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
269 compatible = "arm,cortex-a72-pmu";
270 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
274 compatible = "fixed-clock";
276 clock-frequency = <24000000>;
277 clock-output-names = "xin24m";
281 compatible = "arm,amba-bus";
282 #address-cells = <2>;
286 dmac_bus: dma-controller@ff6d0000 {
287 compatible = "arm,pl330", "arm,primecell";
288 reg = <0x0 0xff6d0000 0x0 0x4000>;
289 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
290 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
292 clocks = <&cru ACLK_DMAC0_PERILP>;
293 clock-names = "apb_pclk";
294 peripherals-req-type-burst;
297 dmac_peri: dma-controller@ff6e0000 {
298 compatible = "arm,pl330", "arm,primecell";
299 reg = <0x0 0xff6e0000 0x0 0x4000>;
300 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
301 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
303 clocks = <&cru ACLK_DMAC1_PERILP>;
304 clock-names = "apb_pclk";
305 peripherals-req-type-burst;
310 compatible = "rockchip,rk3399-gmac";
311 reg = <0x0 0xfe300000 0x0 0x10000>;
312 rockchip,grf = <&grf>;
313 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
314 interrupt-names = "macirq";
315 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
316 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
317 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
319 clock-names = "stmmaceth", "mac_clk_rx",
320 "mac_clk_tx", "clk_mac_ref",
321 "clk_mac_refout", "aclk_mac",
323 resets = <&cru SRST_A_GMAC>;
324 reset-names = "stmmaceth";
329 compatible = "rockchip,rk3399-emmc-phy";
330 reg-offset = <0xf780>;
332 rockchip,grf = <&grf>;
333 ctrl-base = <0xfe330000>;
337 sdio0: dwmmc@fe310000 {
338 compatible = "rockchip,rk3399-dw-mshc",
339 "rockchip,rk3288-dw-mshc";
340 reg = <0x0 0xfe310000 0x0 0x4000>;
341 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
342 clock-freq-min-max = <400000 150000000>;
343 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
344 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
345 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
346 fifo-depth = <0x100>;
350 sdmmc: dwmmc@fe320000 {
351 compatible = "rockchip,rk3399-dw-mshc",
352 "rockchip,rk3288-dw-mshc";
353 reg = <0x0 0xfe320000 0x0 0x4000>;
354 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
355 clock-freq-min-max = <400000 150000000>;
356 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
357 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
358 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
359 fifo-depth = <0x100>;
363 sdhci: sdhci@fe330000 {
364 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
365 reg = <0x0 0xfe330000 0x0 0x10000>;
366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
367 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
368 clock-names = "clk_xin", "clk_ahb";
369 assigned-clocks = <&cru SCLK_EMMC>;
370 assigned-clock-parents = <&cru PLL_CPLL>;
371 assigned-clock-rates = <200000000>;
373 phy-names = "phy_arasan";
377 usb_host0_ehci: usb@fe380000 {
378 compatible = "generic-ehci";
379 reg = <0x0 0xfe380000 0x0 0x20000>;
380 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
381 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
382 <&cru SCLK_USBPHY0_480M_SRC>;
383 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
384 phys = <&u2phy0_host>;
389 usb_host0_ohci: usb@fe3a0000 {
390 compatible = "generic-ohci";
391 reg = <0x0 0xfe3a0000 0x0 0x20000>;
392 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
393 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
394 <&cru SCLK_USBPHY0_480M_SRC>;
395 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
396 phys = <&u2phy0_host>;
401 usb_host1_ehci: usb@fe3c0000 {
402 compatible = "generic-ehci";
403 reg = <0x0 0xfe3c0000 0x0 0x20000>;
404 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
405 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
406 <&cru SCLK_USBPHY1_480M_SRC>;
407 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
408 phys = <&u2phy1_host>;
413 usb_host1_ohci: usb@fe3e0000 {
414 compatible = "generic-ohci";
415 reg = <0x0 0xfe3e0000 0x0 0x20000>;
416 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
417 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
418 <&cru SCLK_USBPHY1_480M_SRC>;
419 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
420 phys = <&u2phy1_host>;
425 usbdrd3_0: usb@fe800000 {
426 compatible = "rockchip,dwc3";
427 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
428 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
429 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
430 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
431 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
432 "aclk_usb3", "aclk_usb3_grf";
433 #address-cells = <2>;
437 usbdrd_dwc3_0: dwc3@fe800000 {
438 compatible = "snps,dwc3";
439 reg = <0x0 0xfe800000 0x0 0x100000>;
440 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
442 phys = <&u2phy0_otg>;
443 phy-names = "usb2-phy";
444 snps,dis_enblslpm_quirk;
445 snps,phyif_utmi_16_bits;
446 snps,dis_u2_freeclk_exists_quirk;
447 snps,dis_del_phy_power_chg_quirk;
448 snps,xhci_slow_suspend_quirk;
453 usbdrd3_1: usb@fe900000 {
454 compatible = "rockchip,dwc3";
455 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
456 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
457 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
458 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
459 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
460 "aclk_usb3", "aclk_usb3_grf";
461 #address-cells = <2>;
465 usbdrd_dwc3_1: dwc3@fe900000 {
466 compatible = "snps,dwc3";
467 reg = <0x0 0xfe900000 0x0 0x100000>;
468 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
470 phys = <&u2phy1_otg>;
471 phy-names = "usb2-phy";
472 snps,dis_enblslpm_quirk;
473 snps,phyif_utmi_16_bits;
474 snps,dis_u2_freeclk_exists_quirk;
475 snps,dis_del_phy_power_chg_quirk;
476 snps,xhci_slow_suspend_quirk;
481 gic: interrupt-controller@fee00000 {
482 compatible = "arm,gic-v3";
483 #interrupt-cells = <4>;
484 #address-cells = <2>;
487 interrupt-controller;
489 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
490 <0x0 0xfef00000 0 0xc0000>, /* GICR */
491 <0x0 0xfff00000 0 0x10000>, /* GICC */
492 <0x0 0xfff10000 0 0x10000>, /* GICH */
493 <0x0 0xfff20000 0 0x10000>; /* GICV */
494 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
495 its: interrupt-controller@fee20000 {
496 compatible = "arm,gic-v3-its";
498 reg = <0x0 0xfee20000 0x0 0x20000>;
502 part0: interrupt-partition-0 {
503 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
506 part1: interrupt-partition-1 {
507 affinity = <&cpu_b0 &cpu_b1>;
512 saradc: saradc@ff100000 {
513 compatible = "rockchip,rk3399-saradc";
514 reg = <0x0 0xff100000 0x0 0x100>;
515 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
516 #io-channel-cells = <1>;
517 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
518 clock-names = "saradc", "apb_pclk";
523 compatible = "rockchip,rk3399-i2c";
524 reg = <0x0 0xff3c0000 0x0 0x1000>;
525 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
526 clock-names = "i2c", "pclk";
527 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&i2c0_xfer>;
530 #address-cells = <1>;
536 compatible = "rockchip,rk3399-i2c";
537 reg = <0x0 0xff110000 0x0 0x1000>;
538 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
539 clock-names = "i2c", "pclk";
540 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c1_xfer>;
543 #address-cells = <1>;
549 compatible = "rockchip,rk3399-i2c";
550 reg = <0x0 0xff120000 0x0 0x1000>;
551 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
552 clock-names = "i2c", "pclk";
553 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c2_xfer>;
556 #address-cells = <1>;
562 compatible = "rockchip,rk3399-i2c";
563 reg = <0x0 0xff130000 0x0 0x1000>;
564 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
565 clock-names = "i2c", "pclk";
566 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&i2c3_xfer>;
569 #address-cells = <1>;
575 compatible = "rockchip,rk3399-i2c";
576 reg = <0x0 0xff140000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
578 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2c5_xfer>;
582 #address-cells = <1>;
588 compatible = "rockchip,rk3399-i2c";
589 reg = <0x0 0xff150000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
591 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&i2c6_xfer>;
595 #address-cells = <1>;
601 compatible = "rockchip,rk3399-i2c";
602 reg = <0x0 0xff160000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
604 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c7_xfer>;
608 #address-cells = <1>;
613 uart0: serial@ff180000 {
614 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
615 reg = <0x0 0xff180000 0x0 0x100>;
616 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
617 clock-names = "baudclk", "apb_pclk";
618 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
626 uart1: serial@ff190000 {
627 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
628 reg = <0x0 0xff190000 0x0 0x100>;
629 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
630 clock-names = "baudclk", "apb_pclk";
631 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&uart1_xfer>;
639 uart2: serial@ff1a0000 {
640 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
641 reg = <0x0 0xff1a0000 0x0 0x100>;
642 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
643 clock-names = "baudclk", "apb_pclk";
644 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&uart2c_xfer>;
652 uart3: serial@ff1b0000 {
653 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
654 reg = <0x0 0xff1b0000 0x0 0x100>;
655 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
656 clock-names = "baudclk", "apb_pclk";
657 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
666 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
667 reg = <0x0 0xff1c0000 0x0 0x1000>;
668 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
669 clock-names = "spiclk", "apb_pclk";
670 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
673 #address-cells = <1>;
679 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
680 reg = <0x0 0xff1d0000 0x0 0x1000>;
681 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
682 clock-names = "spiclk", "apb_pclk";
683 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
686 #address-cells = <1>;
692 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
693 reg = <0x0 0xff1e0000 0x0 0x1000>;
694 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
695 clock-names = "spiclk", "apb_pclk";
696 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
697 pinctrl-names = "default";
698 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
699 #address-cells = <1>;
705 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
706 reg = <0x0 0xff1f0000 0x0 0x1000>;
707 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
708 clock-names = "spiclk", "apb_pclk";
709 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
710 pinctrl-names = "default";
711 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
712 #address-cells = <1>;
718 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
719 reg = <0x0 0xff200000 0x0 0x1000>;
720 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
721 clock-names = "spiclk", "apb_pclk";
722 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
725 #address-cells = <1>;
731 soc_thermal: soc-thermal {
732 polling-delay-passive = <20>; /* milliseconds */
733 polling-delay = <1000>; /* milliseconds */
734 sustainable-power = <1000>; /* milliwatts */
736 thermal-sensors = <&tsadc 0>;
739 threshold: trip-point@0 {
740 temperature = <70000>; /* millicelsius */
741 hysteresis = <2000>; /* millicelsius */
744 target: trip-point@1 {
745 temperature = <85000>; /* millicelsius */
746 hysteresis = <2000>; /* millicelsius */
750 temperature = <95000>; /* millicelsius */
751 hysteresis = <2000>; /* millicelsius */
760 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
761 contribution = <4096>;
766 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
767 contribution = <1024>;
772 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
773 contribution = <4096>;
778 gpu_thermal: gpu-thermal {
779 polling-delay-passive = <100>; /* milliseconds */
780 polling-delay = <1000>; /* milliseconds */
782 thermal-sensors = <&tsadc 1>;
786 tsadc: tsadc@ff260000 {
787 compatible = "rockchip,rk3399-tsadc";
788 reg = <0x0 0xff260000 0x0 0x100>;
789 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
790 rockchip,grf = <&grf>;
791 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
792 clock-names = "tsadc", "apb_pclk";
793 assigned-clocks = <&cru SCLK_TSADC>;
794 assigned-clock-rates = <750000>;
795 resets = <&cru SRST_TSADC>;
796 reset-names = "tsadc-apb";
797 pinctrl-names = "init", "default", "sleep";
798 pinctrl-0 = <&otp_gpio>;
799 pinctrl-1 = <&otp_out>;
800 pinctrl-2 = <&otp_gpio>;
801 #thermal-sensor-cells = <1>;
802 rockchip,hw-tshut-temp = <95000>;
806 qos_emmc: qos@ffa58000 {
807 compatible = "syscon";
808 reg = <0x0 0xffa58000 0x0 0x20>;
811 qos_gmac: qos@ffa5c000 {
812 compatible = "syscon";
813 reg = <0x0 0xffa5c000 0x0 0x20>;
816 qos_pcie: qos@ffa60080 {
817 compatible = "syscon";
818 reg = <0x0 0xffa60080 0x0 0x20>;
821 qos_usb_host0: qos@ffa60100 {
822 compatible = "syscon";
823 reg = <0x0 0xffa60100 0x0 0x20>;
826 qos_usb_host1: qos@ffa60180 {
827 compatible = "syscon";
828 reg = <0x0 0xffa60180 0x0 0x20>;
831 qos_usb_otg0: qos@ffa70000 {
832 compatible = "syscon";
833 reg = <0x0 0xffa70000 0x0 0x20>;
836 qos_usb_otg1: qos@ffa70080 {
837 compatible = "syscon";
838 reg = <0x0 0xffa70080 0x0 0x20>;
841 qos_sd: qos@ffa74000 {
842 compatible = "syscon";
843 reg = <0x0 0xffa74000 0x0 0x20>;
846 qos_sdioaudio: qos@ffa76000 {
847 compatible = "syscon";
848 reg = <0x0 0xffa76000 0x0 0x20>;
851 qos_hdcp: qos@ffa90000 {
852 compatible = "syscon";
853 reg = <0x0 0xffa90000 0x0 0x20>;
856 qos_iep: qos@ffa98000 {
857 compatible = "syscon";
858 reg = <0x0 0xffa98000 0x0 0x20>;
861 qos_isp0_m0: qos@ffaa0000 {
862 compatible = "syscon";
863 reg = <0x0 0xffaa0000 0x0 0x20>;
866 qos_isp0_m1: qos@ffaa0080 {
867 compatible = "syscon";
868 reg = <0x0 0xffaa0080 0x0 0x20>;
871 qos_isp1_m0: qos@ffaa8000 {
872 compatible = "syscon";
873 reg = <0x0 0xffaa8000 0x0 0x20>;
876 qos_isp1_m1: qos@ffaa8080 {
877 compatible = "syscon";
878 reg = <0x0 0xffaa8080 0x0 0x20>;
881 qos_rga_r: qos@ffab0000 {
882 compatible = "syscon";
883 reg = <0x0 0xffab0000 0x0 0x20>;
886 qos_rga_w: qos@ffab0080 {
887 compatible = "syscon";
888 reg = <0x0 0xffab0080 0x0 0x20>;
891 qos_video_m0: qos@ffab8000 {
892 compatible = "syscon";
893 reg = <0x0 0xffab8000 0x0 0x20>;
896 qos_video_m1_r: qos@ffac0000 {
897 compatible = "syscon";
898 reg = <0x0 0xffac0000 0x0 0x20>;
901 qos_video_m1_w: qos@ffac0080 {
902 compatible = "syscon";
903 reg = <0x0 0xffac0080 0x0 0x20>;
906 qos_vop_big_r: qos@ffac8000 {
907 compatible = "syscon";
908 reg = <0x0 0xffac8000 0x0 0x20>;
911 qos_vop_big_w: qos@ffac8080 {
912 compatible = "syscon";
913 reg = <0x0 0xffac8080 0x0 0x20>;
916 qos_vop_little: qos@ffad0000 {
917 compatible = "syscon";
918 reg = <0x0 0xffad0000 0x0 0x20>;
921 qos_perihp: qos@ffad8080 {
922 compatible = "syscon";
923 reg = <0x0 0xffad8080 0x0 0x20>;
926 qos_gpu: qos@ffae0000 {
927 compatible = "syscon";
928 reg = <0x0 0xffae0000 0x0 0x20>;
931 pmu: power-management@ff310000 {
932 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
933 reg = <0x0 0xff310000 0x0 0x1000>;
936 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
937 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
938 * Some of the power domains are grouped together for every
940 * The detail contents as below.
942 power: power-controller {
943 compatible = "rockchip,rk3399-power-controller";
944 #power-domain-cells = <1>;
945 #address-cells = <1>;
948 /* These power domains are grouped by VD_CENTER */
949 pd_iep@RK3399_PD_IEP {
950 reg = <RK3399_PD_IEP>;
951 clocks = <&cru ACLK_IEP>,
955 pd_rga@RK3399_PD_RGA {
956 reg = <RK3399_PD_RGA>;
957 clocks = <&cru ACLK_RGA>,
959 pm_qos = <&qos_rga_r>,
962 pd_vcodec@RK3399_PD_VCODEC {
963 reg = <RK3399_PD_VCODEC>;
964 clocks = <&cru ACLK_VCODEC>,
966 pm_qos = <&qos_video_m0>;
968 pd_vdu@RK3399_PD_VDU {
969 reg = <RK3399_PD_VDU>;
970 clocks = <&cru ACLK_VDU>,
972 pm_qos = <&qos_video_m1_r>,
976 /* These power domains are grouped by VD_GPU */
977 pd_gpu@RK3399_PD_GPU {
978 reg = <RK3399_PD_GPU>;
979 clocks = <&cru ACLK_GPU>;
983 /* These power domains are grouped by VD_LOGIC */
984 pd_emmc@RK3399_PD_EMMC {
985 reg = <RK3399_PD_EMMC>;
986 clocks = <&cru ACLK_EMMC>;
987 pm_qos = <&qos_emmc>;
989 pd_gmac@RK3399_PD_GMAC {
990 reg = <RK3399_PD_GMAC>;
991 clocks = <&cru ACLK_GMAC>;
992 pm_qos = <&qos_gmac>;
994 pd_perihp@RK3399_PD_PERIHP {
995 reg = <RK3399_PD_PERIHP>;
996 clocks = <&cru ACLK_PERIHP>;
997 pm_qos = <&qos_perihp>,
1002 pd_sd@RK3399_PD_SD {
1003 reg = <RK3399_PD_SD>;
1004 clocks = <&cru HCLK_SDMMC>;
1007 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1008 reg = <RK3399_PD_SDIOAUDIO>;
1009 clocks = <&cru HCLK_SDIO>;
1010 pm_qos = <&qos_sdioaudio>;
1012 pd_usb3@RK3399_PD_USB3 {
1013 reg = <RK3399_PD_USB3>;
1014 clocks = <&cru ACLK_USB3>;
1015 pm_qos = <&qos_usb_otg0>,
1018 pd_vio@RK3399_PD_VIO {
1019 reg = <RK3399_PD_VIO>;
1020 #address-cells = <1>;
1023 pd_hdcp@RK3399_PD_HDCP {
1024 reg = <RK3399_PD_HDCP>;
1025 clocks = <&cru ACLK_HDCP>,
1028 pm_qos = <&qos_hdcp>;
1030 pd_isp0@RK3399_PD_ISP0 {
1031 reg = <RK3399_PD_ISP0>;
1032 clocks = <&cru ACLK_ISP0>,
1034 pm_qos = <&qos_isp0_m0>,
1037 pd_isp1@RK3399_PD_ISP1 {
1038 reg = <RK3399_PD_ISP1>;
1039 clocks = <&cru ACLK_ISP1>,
1041 pm_qos = <&qos_isp1_m0>,
1044 pd_vo@RK3399_PD_VO {
1045 reg = <RK3399_PD_VO>;
1046 #address-cells = <1>;
1049 pd_vopb@RK3399_PD_VOPB {
1050 reg = <RK3399_PD_VOPB>;
1051 clocks = <&cru ACLK_VOP0>,
1053 pm_qos = <&qos_vop_big_r>,
1056 pd_vopl@RK3399_PD_VOPL {
1057 reg = <RK3399_PD_VOPL>;
1058 clocks = <&cru ACLK_VOP1>,
1060 pm_qos = <&qos_vop_little>;
1067 pmugrf: syscon@ff320000 {
1068 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1069 reg = <0x0 0xff320000 0x0 0x1000>;
1072 compatible = "syscon-reboot-mode";
1074 mode-bootloader = <BOOT_LOADER>;
1075 mode-charge = <BOOT_CHARGING>;
1076 mode-fastboot = <BOOT_FASTBOOT>;
1077 mode-loader = <BOOT_LOADER>;
1078 mode-normal = <BOOT_NORMAL>;
1079 mode-recovery = <BOOT_RECOVERY>;
1083 spi3: spi@ff350000 {
1084 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1085 reg = <0x0 0xff350000 0x0 0x1000>;
1086 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1087 clock-names = "spiclk", "apb_pclk";
1088 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1091 #address-cells = <1>;
1093 status = "disabled";
1096 uart4: serial@ff370000 {
1097 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1098 reg = <0x0 0xff370000 0x0 0x100>;
1099 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1100 clock-names = "baudclk", "apb_pclk";
1101 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1104 pinctrl-names = "default";
1105 pinctrl-0 = <&uart4_xfer>;
1106 status = "disabled";
1109 i2c4: i2c@ff3d0000 {
1110 compatible = "rockchip,rk3399-i2c";
1111 reg = <0x0 0xff3d0000 0x0 0x1000>;
1112 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1113 clock-names = "i2c", "pclk";
1114 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1115 pinctrl-names = "default";
1116 pinctrl-0 = <&i2c4_xfer>;
1117 #address-cells = <1>;
1119 status = "disabled";
1122 i2c8: i2c@ff3e0000 {
1123 compatible = "rockchip,rk3399-i2c";
1124 reg = <0x0 0xff3e0000 0x0 0x1000>;
1125 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1126 clock-names = "i2c", "pclk";
1127 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&i2c8_xfer>;
1130 #address-cells = <1>;
1132 status = "disabled";
1135 pcie0: pcie@f8000000 {
1136 compatible = "rockchip,rk3399-pcie";
1137 #address-cells = <3>;
1139 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1140 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1141 clock-names = "aclk_pcie", "aclk_perf_pcie",
1142 "hclk_pcie", "clk_pciephy_ref";
1143 bus-range = <0x0 0x1>;
1144 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1145 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1146 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1147 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1148 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1149 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1150 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1151 < 0x0 0xfd000000 0x0 0x1000000 >;
1152 reg-name = "axi-base", "apb-base";
1153 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1154 <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1155 <&cru SRST_PCIE_PIPE>;
1156 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1157 "mgmt-sticky-rst", "pipe-rst";
1158 rockchip,grf = <&grf>;
1159 pcie-conf = <0xe220>;
1160 pcie-status = <0xe2a4>;
1161 pcie-laneoff = <0xe214>;
1162 msi-parent = <&its>;
1163 #interrupt-cells = <1>;
1164 interrupt-map-mask = <0 0 0 7>;
1165 interrupt-map = <0 0 0 1 &pcie0 1>,
1169 status = "disabled";
1170 pcie_intc: interrupt-controller {
1171 interrupt-controller;
1172 #address-cells = <0>;
1173 #interrupt-cells = <1>;
1177 pwm0: pwm@ff420000 {
1178 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1179 reg = <0x0 0xff420000 0x0 0x10>;
1181 pinctrl-names = "default";
1182 pinctrl-0 = <&pwm0_pin>;
1183 clocks = <&pmucru PCLK_RKPWM_PMU>;
1184 clock-names = "pwm";
1185 status = "disabled";
1188 pwm1: pwm@ff420010 {
1189 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1190 reg = <0x0 0xff420010 0x0 0x10>;
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&pwm1_pin>;
1194 clocks = <&pmucru PCLK_RKPWM_PMU>;
1195 clock-names = "pwm";
1196 status = "disabled";
1199 pwm2: pwm@ff420020 {
1200 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1201 reg = <0x0 0xff420020 0x0 0x10>;
1203 pinctrl-names = "default";
1204 pinctrl-0 = <&pwm2_pin>;
1205 clocks = <&pmucru PCLK_RKPWM_PMU>;
1206 clock-names = "pwm";
1207 status = "disabled";
1210 pwm3: pwm@ff420030 {
1211 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1212 reg = <0x0 0xff420030 0x0 0x10>;
1214 pinctrl-names = "default";
1215 pinctrl-0 = <&pwm3a_pin>;
1216 clocks = <&pmucru PCLK_RKPWM_PMU>;
1217 clock-names = "pwm";
1218 status = "disabled";
1222 compatible = "rockchip,rk3399-rga";
1223 reg = <0x0 0xff680000 0x0 0x10000>;
1224 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1225 interrupt-names = "rga";
1226 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1227 clock-names = "aclk", "hclk", "sclk";
1228 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1229 reset-names = "core", "axi", "ahb";
1230 power-domains = <&power RK3399_PD_RGA>;
1231 status = "disabled";
1234 pmucru: pmu-clock-controller@ff750000 {
1235 compatible = "rockchip,rk3399-pmucru";
1236 reg = <0x0 0xff750000 0x0 0x1000>;
1239 assigned-clocks = <&pmucru PLL_PPLL>;
1240 assigned-clock-rates = <676000000>;
1243 cru: clock-controller@ff760000 {
1244 compatible = "rockchip,rk3399-cru";
1245 reg = <0x0 0xff760000 0x0 0x1000>;
1249 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1250 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1251 <&cru ARMCLKL>, <&cru ARMCLKB>,
1252 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1254 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1256 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1257 <&cru PCLK_PERILP0>,
1258 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1259 assigned-clock-rates =
1260 <400000000>, <200000000>,
1261 <400000000>, <200000000>,
1262 <816000000>, <816000000>,
1263 <594000000>, <800000000>,
1265 <150000000>, <75000000>,
1267 <100000000>, <100000000>,
1269 <100000000>, <50000000>;
1272 grf: syscon@ff770000 {
1273 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1274 reg = <0x0 0xff770000 0x0 0x10000>;
1275 #address-cells = <1>;
1278 u2phy0: usb2-phy@e450 {
1279 compatible = "rockchip,rk3399-usb2phy";
1280 reg = <0xe450 0x10>;
1281 clocks = <&cru SCLK_USB2PHY0_REF>;
1282 clock-names = "phyclk";
1284 clock-output-names = "clk_usbphy0_480m";
1285 status = "disabled";
1287 u2phy0_otg: otg-port {
1289 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1290 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1291 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1292 interrupt-names = "otg-bvalid", "otg-id",
1294 status = "disabled";
1297 u2phy0_host: host-port {
1299 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1300 interrupt-names = "linestate";
1301 status = "disabled";
1305 u2phy1: usb2-phy@e460 {
1306 compatible = "rockchip,rk3399-usb2phy";
1307 reg = <0xe460 0x10>;
1308 clocks = <&cru SCLK_USB2PHY1_REF>;
1309 clock-names = "phyclk";
1311 clock-output-names = "clk_usbphy1_480m";
1312 status = "disabled";
1314 u2phy1_otg: otg-port {
1316 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1319 interrupt-names = "otg-bvalid", "otg-id",
1321 status = "disabled";
1324 u2phy1_host: host-port {
1326 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1327 interrupt-names = "linestate";
1328 status = "disabled";
1333 tcphy0: phy@ff7c0000 {
1334 compatible = "rockchip,rk3399-typec-phy";
1335 reg = <0x0 0xff7c0000 0x0 0x40000>;
1336 rockchip,grf = <&grf>;
1338 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1339 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1340 clock-names = "tcpdcore", "tcpdphy-ref";
1341 resets = <&cru SRST_UPHY0>,
1342 <&cru SRST_UPHY0_PIPE_L00>,
1343 <&cru SRST_P_UPHY0_TCPHY>;
1344 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1345 rockchip,typec-conn-dir = <0xe580 0 16>;
1346 rockchip,usb3tousb2-en = <0xe580 3 19>;
1347 rockchip,external-psm = <0xe588 14 30>;
1348 rockchip,pipe-status = <0xe5c0 0 0>;
1349 rockchip,uphy-dp-sel = <0x6268 19 19>;
1350 status = "disabled";
1353 tcphy1: phy@ff800000 {
1354 compatible = "rockchip,rk3399-typec-phy";
1355 reg = <0x0 0xff800000 0x0 0x40000>;
1356 rockchip,grf = <&grf>;
1358 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1359 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1360 clock-names = "tcpdcore", "tcpdphy-ref";
1361 resets = <&cru SRST_UPHY1>,
1362 <&cru SRST_UPHY1_PIPE_L00>,
1363 <&cru SRST_P_UPHY1_TCPHY>;
1364 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1365 rockchip,typec-conn-dir = <0xe58c 0 16>;
1366 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1367 rockchip,external-psm = <0xe594 14 30>;
1368 rockchip,pipe-status = <0xe5c0 16 16>;
1369 rockchip,uphy-dp-sel = <0x6268 3 19>;
1370 status = "disabled";
1374 compatible = "snps,dw-wdt";
1375 reg = <0x0 0xff840000 0x0 0x100>;
1376 clocks = <&cru PCLK_WDT>;
1377 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1380 rktimer: rktimer@ff850000 {
1381 compatible = "rockchip,rk3399-timer";
1382 reg = <0x0 0xff850000 0x0 0x1000>;
1383 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1384 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1385 clock-names = "pclk", "timer";
1388 spdif: spdif@ff870000 {
1389 compatible = "rockchip,rk3399-spdif";
1390 reg = <0x0 0xff870000 0x0 0x1000>;
1391 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1392 dmas = <&dmac_bus 7>;
1394 clock-names = "mclk", "hclk";
1395 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&spdif_bus>;
1398 status = "disabled";
1401 i2s0: i2s@ff880000 {
1402 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1403 reg = <0x0 0xff880000 0x0 0x1000>;
1404 rockchip,grf = <&grf>;
1405 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1406 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1407 dma-names = "tx", "rx";
1408 clock-names = "i2s_clk", "i2s_hclk";
1409 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&i2s0_8ch_bus>;
1412 status = "disabled";
1415 i2s1: i2s@ff890000 {
1416 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1417 reg = <0x0 0xff890000 0x0 0x1000>;
1418 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1419 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1420 dma-names = "tx", "rx";
1421 clock-names = "i2s_clk", "i2s_hclk";
1422 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1423 pinctrl-names = "default";
1424 pinctrl-0 = <&i2s1_2ch_bus>;
1425 status = "disabled";
1428 i2s2: i2s@ff8a0000 {
1429 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1430 reg = <0x0 0xff8a0000 0x0 0x1000>;
1431 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1432 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1433 dma-names = "tx", "rx";
1434 clock-names = "i2s_clk", "i2s_hclk";
1435 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1436 status = "disabled";
1440 compatible = "arm,malit860",
1445 reg = <0x0 0xff9a0000 0x0 0x10000>;
1447 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1448 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1449 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1450 interrupt-names = "GPU", "JOB", "MMU";
1452 clocks = <&cru ACLK_GPU>;
1453 clock-names = "clk_mali";
1454 #cooling-cells = <2>; /* min followed by max */
1455 operating-points-v2 = <&gpu_opp_table>;
1456 power-domains = <&power RK3399_PD_GPU>;
1457 power-off-delay-ms = <200>;
1458 status = "disabled";
1460 gpu_power_model: power_model {
1461 compatible = "arm,mali-simple-power-model";
1464 static-power = <300>;
1465 dynamic-power = <396>;
1466 ts = <32000 4700 (-80) 2>;
1467 thermal-zone = "gpu-thermal";
1471 gpu_opp_table: gpu_opp_table {
1472 compatible = "operating-points-v2";
1476 opp-hz = /bits/ 64 <200000000>;
1477 opp-microvolt = <900000>;
1480 opp-hz = /bits/ 64 <300000000>;
1481 opp-microvolt = <900000>;
1484 opp-hz = /bits/ 64 <400000000>;
1485 opp-microvolt = <900000>;
1490 vopl: vop@ff8f0000 {
1491 compatible = "rockchip,rk3399-vop-lit";
1492 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1493 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1494 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1495 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1496 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1497 reset-names = "axi", "ahb", "dclk";
1498 power-domains = <&power RK3399_PD_VOPL>;
1499 iommus = <&vopl_mmu>;
1500 status = "disabled";
1503 #address-cells = <1>;
1506 vopl_out_mipi: endpoint@0 {
1508 remote-endpoint = <&mipi_in_vopl>;
1511 vopl_out_edp: endpoint@1 {
1513 remote-endpoint = <&edp_in_vopl>;
1516 vopl_out_hdmi: endpoint@2 {
1518 remote-endpoint = <&hdmi_in_vopl>;
1523 vopl_mmu: iommu@ff8f3f00 {
1524 compatible = "rockchip,iommu";
1525 reg = <0x0 0xff8f3f00 0x0 0x100>;
1526 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1527 interrupt-names = "vopl_mmu";
1529 status = "disabled";
1532 vopb: vop@ff900000 {
1533 compatible = "rockchip,rk3399-vop-big";
1534 reg = <0x0 0xff900000 0x0 0x3efc>;
1535 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1536 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1537 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1538 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1539 reset-names = "axi", "ahb", "dclk";
1540 power-domains = <&power RK3399_PD_VOPB>;
1541 iommus = <&vopb_mmu>;
1542 status = "disabled";
1545 #address-cells = <1>;
1548 vopb_out_edp: endpoint@0 {
1550 remote-endpoint = <&edp_in_vopb>;
1553 vopb_out_mipi: endpoint@1 {
1555 remote-endpoint = <&mipi_in_vopb>;
1558 vopb_out_hdmi: endpoint@2 {
1560 remote-endpoint = <&hdmi_in_vopb>;
1565 vopb_mmu: iommu@ff903f00 {
1566 compatible = "rockchip,iommu";
1567 reg = <0x0 0xff903f00 0x0 0x100>;
1568 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1569 interrupt-names = "vopb_mmu";
1571 status = "disabled";
1574 hdmi: hdmi@ff940000 {
1575 compatible = "rockchip,rk3399-dw-hdmi";
1576 reg = <0x0 0xff940000 0x0 0x20000>;
1578 rockchip,grf = <&grf>;
1579 power-domains = <&power RK3399_PD_HDCP>;
1580 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1581 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1582 clock-names = "iahb", "isfr", "vpll", "grf";
1583 status = "disabled";
1587 #address-cells = <1>;
1589 hdmi_in_vopb: endpoint@0 {
1591 remote-endpoint = <&vopb_out_hdmi>;
1593 hdmi_in_vopl: endpoint@1 {
1595 remote-endpoint = <&vopl_out_hdmi>;
1601 mipi_dsi: mipi@ff960000 {
1602 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1603 reg = <0x0 0xff960000 0x0 0x8000>;
1604 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1605 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1606 <&cru SCLK_DPHY_TX0_CFG>;
1607 clock-names = "ref", "pclk", "phy_cfg";
1608 power-domains = <&power RK3399_PD_VIO>;
1609 rockchip,grf = <&grf>;
1610 #address-cells = <1>;
1612 status = "disabled";
1615 #address-cells = <1>;
1620 #address-cells = <1>;
1623 mipi_in_vopb: endpoint@0 {
1625 remote-endpoint = <&vopb_out_mipi>;
1627 mipi_in_vopl: endpoint@1 {
1629 remote-endpoint = <&vopl_out_mipi>;
1636 compatible = "rockchip,rk3399-edp";
1637 reg = <0x0 0xff970000 0x0 0x8000>;
1638 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1639 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1640 clock-names = "dp", "pclk";
1641 resets = <&cru SRST_P_EDP_CTRL>;
1643 rockchip,grf = <&grf>;
1644 status = "disabled";
1645 pinctrl-names = "default";
1646 pinctrl-0 = <&edp_hpd>;
1649 #address-cells = <1>;
1654 #address-cells = <1>;
1657 edp_in_vopb: endpoint@0 {
1659 remote-endpoint = <&vopb_out_edp>;
1662 edp_in_vopl: endpoint@1 {
1664 remote-endpoint = <&vopl_out_edp>;
1670 display_subsystem: display-subsystem {
1671 compatible = "rockchip,display-subsystem";
1672 ports = <&vopl_out>, <&vopb_out>;
1673 status = "disabled";
1677 compatible = "rockchip,rk3399-pinctrl";
1678 rockchip,grf = <&grf>;
1679 rockchip,pmu = <&pmugrf>;
1680 #address-cells = <0x2>;
1681 #size-cells = <0x2>;
1684 gpio0: gpio0@ff720000 {
1685 compatible = "rockchip,gpio-bank";
1686 reg = <0x0 0xff720000 0x0 0x100>;
1687 clocks = <&pmucru PCLK_GPIO0_PMU>;
1688 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1691 #gpio-cells = <0x2>;
1693 interrupt-controller;
1694 #interrupt-cells = <0x2>;
1697 gpio1: gpio1@ff730000 {
1698 compatible = "rockchip,gpio-bank";
1699 reg = <0x0 0xff730000 0x0 0x100>;
1700 clocks = <&pmucru PCLK_GPIO1_PMU>;
1701 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1704 #gpio-cells = <0x2>;
1706 interrupt-controller;
1707 #interrupt-cells = <0x2>;
1710 gpio2: gpio2@ff780000 {
1711 compatible = "rockchip,gpio-bank";
1712 reg = <0x0 0xff780000 0x0 0x100>;
1713 clocks = <&cru PCLK_GPIO2>;
1714 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1717 #gpio-cells = <0x2>;
1719 interrupt-controller;
1720 #interrupt-cells = <0x2>;
1723 gpio3: gpio3@ff788000 {
1724 compatible = "rockchip,gpio-bank";
1725 reg = <0x0 0xff788000 0x0 0x100>;
1726 clocks = <&cru PCLK_GPIO3>;
1727 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1730 #gpio-cells = <0x2>;
1732 interrupt-controller;
1733 #interrupt-cells = <0x2>;
1736 gpio4: gpio4@ff790000 {
1737 compatible = "rockchip,gpio-bank";
1738 reg = <0x0 0xff790000 0x0 0x100>;
1739 clocks = <&cru PCLK_GPIO4>;
1740 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1743 #gpio-cells = <0x2>;
1745 interrupt-controller;
1746 #interrupt-cells = <0x2>;
1749 pcfg_pull_up: pcfg-pull-up {
1753 pcfg_pull_down: pcfg-pull-down {
1757 pcfg_pull_none: pcfg-pull-none {
1761 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1763 drive-strength = <20>;
1766 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1768 drive-strength = <20>;
1771 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1773 drive-strength = <18>;
1776 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1778 drive-strength = <12>;
1781 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1783 drive-strength = <8>;
1786 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1788 drive-strength = <4>;
1791 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1793 drive-strength = <2>;
1796 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1798 drive-strength = <12>;
1801 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1803 drive-strength = <13>;
1807 emmc_pwr: emmc-pwr {
1809 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1814 rgmii_pins: rgmii-pins {
1817 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1819 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1821 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1823 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1825 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1827 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1829 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1831 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1833 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1835 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1837 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1839 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1841 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1843 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1845 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1848 rmii_pins: rmii-pins {
1851 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1853 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1855 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1857 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1859 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1861 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1863 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1865 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1867 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1869 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1874 i2c0_xfer: i2c0-xfer {
1876 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1877 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1882 i2c1_xfer: i2c1-xfer {
1884 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1885 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1890 i2c2_xfer: i2c2-xfer {
1892 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1893 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1898 i2c3_xfer: i2c3-xfer {
1900 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1901 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1904 i2c3_gpio: i2c3_gpio {
1906 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1907 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1913 i2c4_xfer: i2c4-xfer {
1915 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1916 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1921 i2c5_xfer: i2c5-xfer {
1923 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1924 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1929 i2c6_xfer: i2c6-xfer {
1931 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1932 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1937 i2c7_xfer: i2c7-xfer {
1939 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1940 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1945 i2c8_xfer: i2c8-xfer {
1947 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1948 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1953 i2s0_8ch_bus: i2s0-8ch-bus {
1955 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1956 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1957 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1958 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1959 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1960 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1961 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1962 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1963 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1968 i2s1_2ch_bus: i2s1-2ch-bus {
1970 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1971 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1972 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1973 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1974 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1979 sdio0_bus1: sdio0-bus1 {
1981 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1984 sdio0_bus4: sdio0-bus4 {
1986 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1987 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1988 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1989 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1992 sdio0_cmd: sdio0-cmd {
1994 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1997 sdio0_clk: sdio0-clk {
1999 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2002 sdio0_cd: sdio0-cd {
2004 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2007 sdio0_pwr: sdio0-pwr {
2009 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2012 sdio0_bkpwr: sdio0-bkpwr {
2014 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2017 sdio0_wp: sdio0-wp {
2019 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2022 sdio0_int: sdio0-int {
2024 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2029 sdmmc_bus1: sdmmc-bus1 {
2031 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2034 sdmmc_bus4: sdmmc-bus4 {
2036 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2037 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2038 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2039 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2042 sdmmc_clk: sdmmc-clk {
2044 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2047 sdmmc_cmd: sdmmc-cmd {
2049 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2052 sdmmc_cd: sdmcc-cd {
2054 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2057 sdmmc_wp: sdmmc-wp {
2059 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2064 spdif_bus: spdif-bus {
2066 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2069 spdif_bus_1: spdif-bus-1 {
2071 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2076 spi0_clk: spi0-clk {
2078 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2080 spi0_cs0: spi0-cs0 {
2082 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2084 spi0_cs1: spi0-cs1 {
2086 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2090 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2094 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2099 spi1_clk: spi1-clk {
2101 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2103 spi1_cs0: spi1-cs0 {
2105 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2109 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2113 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2118 spi2_clk: spi2-clk {
2120 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2122 spi2_cs0: spi2-cs0 {
2124 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2128 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2132 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2137 spi3_clk: spi3-clk {
2139 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2141 spi3_cs0: spi3-cs0 {
2143 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2147 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2151 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2156 spi4_clk: spi4-clk {
2158 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2160 spi4_cs0: spi4-cs0 {
2162 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2166 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2170 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2175 spi5_clk: spi5-clk {
2177 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2179 spi5_cs0: spi5-cs0 {
2181 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2185 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2189 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2194 otp_gpio: otp-gpio {
2195 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2199 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2204 uart0_xfer: uart0-xfer {
2206 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2207 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2210 uart0_cts: uart0-cts {
2212 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2215 uart0_rts: uart0-rts {
2217 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2222 uart1_xfer: uart1-xfer {
2224 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2225 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2230 uart2a_xfer: uart2a-xfer {
2232 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2233 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2238 uart2b_xfer: uart2b-xfer {
2240 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2241 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2246 uart2c_xfer: uart2c-xfer {
2248 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2249 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2254 uart3_xfer: uart3-xfer {
2256 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2257 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2260 uart3_cts: uart3-cts {
2262 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2265 uart3_rts: uart3-rts {
2267 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2272 uart4_xfer: uart4-xfer {
2274 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2275 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2280 uarthdcp_xfer: uarthdcp-xfer {
2282 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2283 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2288 pwm0_pin: pwm0-pin {
2290 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2293 vop0_pwm_pin: vop0-pwm-pin {
2295 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2300 pwm1_pin: pwm1-pin {
2302 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2305 vop1_pwm_pin: vop1-pwm-pin {
2307 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2312 pwm2_pin: pwm2-pin {
2314 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2319 pwm3a_pin: pwm3a-pin {
2321 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2326 pwm3b_pin: pwm3b-pin {
2328 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2335 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2340 hdmi_i2c_xfer: hdmi-i2c-xfer {
2342 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2343 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2346 hdmi_cec: hdmi-cec {
2348 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2353 pcie_clkreqn: pci-clkreqn {
2355 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2358 pcie_clkreqnb: pci-clkreqnb {
2360 <4 24 RK_FUNC_1 &pcfg_pull_none>;