2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
75 compatible = "arm,psci-1.0";
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 clocks = <&cru ARMCLKL>;
116 operating-points-v2 = <&cluster0_opp>;
121 compatible = "arm,cortex-a53", "arm,armv8";
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 operating-points-v2 = <&cluster0_opp>;
130 compatible = "arm,cortex-a53", "arm,armv8";
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster0_opp>;
148 compatible = "arm,cortex-a72", "arm,armv8";
150 enable-method = "psci";
151 #cooling-cells = <2>; /* min followed by max */
152 clocks = <&cru ARMCLKB>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a72", "arm,armv8";
160 enable-method = "psci";
161 clocks = <&cru ARMCLKB>;
162 operating-points-v2 = <&cluster1_opp>;
166 cluster0_opp: opp_table0 {
167 compatible = "operating-points-v2";
171 opp-hz = /bits/ 64 <408000000>;
172 opp-microvolt = <900000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <600000000>;
177 opp-microvolt = <900000>;
180 opp-hz = /bits/ 64 <816000000>;
181 opp-microvolt = <900000>;
184 opp-hz = /bits/ 64 <1008000000>;
185 opp-microvolt = <900000>;
189 cluster1_opp: opp_table1 {
190 compatible = "operating-points-v2";
194 opp-hz = /bits/ 64 <408000000>;
195 opp-microvolt = <900000>;
196 clock-latency-ns = <40000>;
199 opp-hz = /bits/ 64 <600000000>;
200 opp-microvolt = <900000>;
203 opp-hz = /bits/ 64 <816000000>;
204 opp-microvolt = <900000>;
207 opp-hz = /bits/ 64 <1008000000>;
208 opp-microvolt = <900000>;
211 opp-hz = /bits/ 64 <1200000000>;
212 opp-microvolt = <900000>;
217 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
219 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
220 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
221 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
225 compatible = "arm,armv8-pmuv3";
226 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
230 compatible = "fixed-clock";
232 clock-frequency = <24000000>;
233 clock-output-names = "xin24m";
237 compatible = "arm,amba-bus";
238 #address-cells = <2>;
242 dmac_bus: dma-controller@ff6d0000 {
243 compatible = "arm,pl330", "arm,primecell";
244 reg = <0x0 0xff6d0000 0x0 0x4000>;
245 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cru ACLK_DMAC0_PERILP>;
249 clock-names = "apb_pclk";
252 dmac_peri: dma-controller@ff6e0000 {
253 compatible = "arm,pl330", "arm,primecell";
254 reg = <0x0 0xff6e0000 0x0 0x4000>;
255 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cru ACLK_DMAC1_PERILP>;
259 clock-names = "apb_pclk";
264 compatible = "rockchip,rk3399-gmac";
265 reg = <0x0 0xfe300000 0x0 0x10000>;
266 rockchip,grf = <&grf>;
267 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-names = "macirq";
269 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
270 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
271 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
273 clock-names = "stmmaceth", "mac_clk_rx",
274 "mac_clk_tx", "clk_mac_ref",
275 "clk_mac_refout", "aclk_mac",
277 resets = <&cru SRST_A_GMAC>;
278 reset-names = "stmmaceth";
283 compatible = "rockchip,rk3399-emmc-phy";
284 reg-offset = <0xf780>;
286 rockchip,grf = <&grf>;
290 sdio0: dwmmc@fe310000 {
291 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
292 reg = <0x0 0xfe310000 0x0 0x4000>;
293 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
294 clock-freq-min-max = <400000 150000000>;
295 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
296 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
297 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
298 fifo-depth = <0x100>;
302 sdmmc: dwmmc@fe320000 {
303 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
304 reg = <0x0 0xfe320000 0x0 0x4000>;
305 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
306 clock-freq-min-max = <400000 150000000>;
307 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
308 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
309 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
310 fifo-depth = <0x100>;
314 sdhci: sdhci@fe330000 {
315 compatible = "arasan,sdhci-5.1";
316 reg = <0x0 0xfe330000 0x0 0x10000>;
317 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
319 clock-names = "clk_xin", "clk_ahb";
321 phy-names = "phy_arasan";
326 compatible = "rockchip,rk3399-usb-phy";
327 rockchip,grf = <&grf>;
328 #address-cells = <1>;
331 usb2phy0: usb2-phy0 {
337 usb2phy1: usb2-phy1 {
344 usb_host0_echi: usb@fe380000 {
345 compatible = "generic-ehci";
346 reg = <0x0 0xfe380000 0x0 0x20000>;
347 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
349 clock-names = "hclk_host0", "hclk_host0_arb";
351 phy-names = "usb2_phy0";
355 usb_host0_ohci: usb@fe3a0000 {
356 compatible = "generic-ohci";
357 reg = <0x0 0xfe3a0000 0x0 0x20000>;
358 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
360 clock-names = "hclk_host0", "hclk_host0_arb";
364 usb_host1_echi: usb@fe3c0000 {
365 compatible = "generic-ehci";
366 reg = <0x0 0xfe3c0000 0x0 0x20000>;
367 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
369 clock-names = "hclk_host1", "hclk_host1_arb";
371 phy-names = "usb2_phy1";
375 usb_host1_ohci: usb@fe3e0000 {
376 compatible = "generic-ohci";
377 reg = <0x0 0xfe3e0000 0x0 0x20000>;
378 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
380 clock-names = "hclk_host1", "hclk_host1_arb";
384 usbdrd3_0: usb@fe800000 {
385 compatible = "rockchip,dwc3";
386 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
387 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
388 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
389 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
390 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
391 "aclk_usb3", "aclk_usb3_grf";
392 #address-cells = <2>;
396 usbdrd_dwc3_0: dwc3 {
397 compatible = "snps,dwc3";
398 reg = <0x0 0xfe800000 0x0 0x100000>;
399 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
402 snps,dis_enblslpm_quirk;
403 snps,phyif_utmi_16_bits;
404 snps,dis_u2_freeclk_exists_quirk;
405 snps,dis_del_phy_power_chg_quirk;
410 usbdrd3_1: usb@fe900000 {
411 compatible = "rockchip,dwc3";
412 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
413 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
414 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
415 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
416 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
417 "aclk_usb3", "aclk_usb3_grf";
418 #address-cells = <2>;
422 usbdrd_dwc3_1: dwc3 {
423 compatible = "snps,dwc3";
424 reg = <0x0 0xfe900000 0x0 0x100000>;
425 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
428 snps,dis_enblslpm_quirk;
429 snps,phyif_utmi_16_bits;
430 snps,dis_u2_freeclk_exists_quirk;
431 snps,dis_del_phy_power_chg_quirk;
436 gic: interrupt-controller@fee00000 {
437 compatible = "arm,gic-v3";
438 #interrupt-cells = <3>;
439 #address-cells = <2>;
442 interrupt-controller;
444 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
445 <0x0 0xfef00000 0 0xc0000>, /* GICR */
446 <0x0 0xfff00000 0 0x10000>, /* GICC */
447 <0x0 0xfff10000 0 0x10000>, /* GICH */
448 <0x0 0xfff20000 0 0x10000>; /* GICV */
449 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
450 its: interrupt-controller@fee20000 {
451 compatible = "arm,gic-v3-its";
453 reg = <0x0 0xfee20000 0x0 0x20000>;
457 saradc: saradc@ff100000 {
458 compatible = "rockchip,rk3399-saradc";
459 reg = <0x0 0xff100000 0x0 0x100>;
460 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
461 #io-channel-cells = <1>;
462 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
463 clock-names = "saradc", "apb_pclk";
468 compatible = "rockchip,rk3399-i2c";
469 reg = <0x0 0xff3c0000 0x0 0x1000>;
470 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
471 clock-names = "i2c", "pclk";
472 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&i2c0_xfer>;
475 #address-cells = <1>;
481 compatible = "rockchip,rk3399-i2c";
482 reg = <0x0 0xff110000 0x0 0x1000>;
483 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
484 clock-names = "i2c", "pclk";
485 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&i2c1_xfer>;
488 #address-cells = <1>;
494 compatible = "rockchip,rk3399-i2c";
495 reg = <0x0 0xff120000 0x0 0x1000>;
496 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
497 clock-names = "i2c", "pclk";
498 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&i2c2_xfer>;
501 #address-cells = <1>;
507 compatible = "rockchip,rk3399-i2c";
508 reg = <0x0 0xff130000 0x0 0x1000>;
509 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
510 clock-names = "i2c", "pclk";
511 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&i2c3_xfer>;
514 #address-cells = <1>;
520 compatible = "rockchip,rk3399-i2c";
521 reg = <0x0 0xff140000 0x0 0x1000>;
522 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
523 clock-names = "i2c", "pclk";
524 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&i2c5_xfer>;
527 #address-cells = <1>;
533 compatible = "rockchip,rk3399-i2c";
534 reg = <0x0 0xff150000 0x0 0x1000>;
535 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
536 clock-names = "i2c", "pclk";
537 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c6_xfer>;
540 #address-cells = <1>;
546 compatible = "rockchip,rk3399-i2c";
547 reg = <0x0 0xff160000 0x0 0x1000>;
548 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
549 clock-names = "i2c", "pclk";
550 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c7_xfer>;
553 #address-cells = <1>;
558 uart0: serial@ff180000 {
559 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
560 reg = <0x0 0xff180000 0x0 0x100>;
561 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
562 clock-names = "baudclk", "apb_pclk";
563 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
571 uart1: serial@ff190000 {
572 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
573 reg = <0x0 0xff190000 0x0 0x100>;
574 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
575 clock-names = "baudclk", "apb_pclk";
576 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&uart1_xfer>;
584 uart2: serial@ff1a0000 {
585 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
586 reg = <0x0 0xff1a0000 0x0 0x100>;
587 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
588 clock-names = "baudclk", "apb_pclk";
589 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&uart2c_xfer>;
597 uart3: serial@ff1b0000 {
598 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
599 reg = <0x0 0xff1b0000 0x0 0x100>;
600 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
601 clock-names = "baudclk", "apb_pclk";
602 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
611 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
612 reg = <0x0 0xff1c0000 0x0 0x1000>;
613 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
614 clock-names = "spiclk", "apb_pclk";
615 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
618 #address-cells = <1>;
624 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
625 reg = <0x0 0xff1d0000 0x0 0x1000>;
626 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
627 clock-names = "spiclk", "apb_pclk";
628 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
631 #address-cells = <1>;
637 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
638 reg = <0x0 0xff1e0000 0x0 0x1000>;
639 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
640 clock-names = "spiclk", "apb_pclk";
641 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
644 #address-cells = <1>;
650 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
651 reg = <0x0 0xff1f0000 0x0 0x1000>;
652 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
653 clock-names = "spiclk", "apb_pclk";
654 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
657 #address-cells = <1>;
663 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
664 reg = <0x0 0xff200000 0x0 0x1000>;
665 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
666 clock-names = "spiclk", "apb_pclk";
667 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
670 #address-cells = <1>;
676 #include "rk3368-thermal.dtsi"
679 tsadc: tsadc@ff260000 {
680 compatible = "rockchip,rk3399-tsadc";
681 reg = <0x0 0xff260000 0x0 0x100>;
682 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
683 rockchip,grf = <&grf>;
684 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
685 clock-names = "tsadc", "apb_pclk";
686 assigned-clocks = <&cru SCLK_TSADC>;
687 assigned-clock-rates = <750000>;
688 resets = <&cru SRST_TSADC>;
689 reset-names = "tsadc-apb";
690 pinctrl-names = "init", "default", "sleep";
691 pinctrl-0 = <&otp_gpio>;
692 pinctrl-1 = <&otp_out>;
693 pinctrl-2 = <&otp_gpio>;
694 #thermal-sensor-cells = <1>;
695 rockchip,hw-tshut-temp = <95000>;
699 pmu: power-management@ff31000 {
700 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
701 reg = <0x0 0xff310000 0x0 0x1000>;
703 power: power-controller {
705 compatible = "rockchip,rk3399-power-controller";
706 #power-domain-cells = <1>;
707 #address-cells = <1>;
711 reg = <RK3399_PD_CENTER>;
712 #address-cells = <1>;
716 reg = <RK3399_PD_VDU>;
719 reg = <RK3399_PD_VCODEC>;
722 reg = <RK3399_PD_IEP>;
725 reg = <RK3399_PD_RGA>;
729 reg = <RK3399_PD_VIO>;
730 #address-cells = <1>;
734 reg = <RK3399_PD_ISP0>;
737 reg = <RK3399_PD_ISP1>;
740 reg = <RK3399_PD_HDCP>;
743 reg = <RK3399_PD_VO>;
744 #address-cells = <1>;
748 reg = <RK3399_PD_VOPB>;
751 reg = <RK3399_PD_VOPL>;
756 reg = <RK3399_PD_GPU>;
761 pmugrf: syscon@ff320000 {
762 compatible = "rockchip,rk3399-pmugrf", "syscon";
763 reg = <0x0 0xff320000 0x0 0x1000>;
767 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
768 reg = <0x0 0xff350000 0x0 0x1000>;
769 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
770 clock-names = "spiclk", "apb_pclk";
771 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
772 pinctrl-names = "default";
773 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
774 #address-cells = <1>;
779 uart4: serial@ff370000 {
780 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
781 reg = <0x0 0xff370000 0x0 0x100>;
782 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
783 clock-names = "baudclk", "apb_pclk";
784 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
787 pinctrl-names = "default";
788 pinctrl-0 = <&uart4_xfer>;
793 compatible = "rockchip,rk3399-i2c";
794 reg = <0x0 0xff3d0000 0x0 0x1000>;
795 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
796 clock-names = "i2c", "pclk";
797 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
798 pinctrl-names = "default";
799 pinctrl-0 = <&i2c4_xfer>;
800 #address-cells = <1>;
806 compatible = "rockchip,rk3399-i2c";
807 reg = <0x0 0xff3e0000 0x0 0x1000>;
808 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
809 clock-names = "i2c", "pclk";
810 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
811 pinctrl-names = "default";
812 pinctrl-0 = <&i2c8_xfer>;
813 #address-cells = <1>;
819 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
820 reg = <0x0 0xff420000 0x0 0x10>;
822 pinctrl-names = "default";
823 pinctrl-0 = <&pwm0_pin>;
824 clocks = <&pmucru PCLK_RKPWM_PMU>;
830 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
831 reg = <0x0 0xff420010 0x0 0x10>;
833 pinctrl-names = "default";
834 pinctrl-0 = <&pwm1_pin>;
835 clocks = <&pmucru PCLK_RKPWM_PMU>;
841 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
842 reg = <0x0 0xff420020 0x0 0x10>;
844 pinctrl-names = "default";
845 pinctrl-0 = <&pwm2_pin>;
846 clocks = <&pmucru PCLK_RKPWM_PMU>;
852 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
853 reg = <0x0 0xff420030 0x0 0x10>;
855 pinctrl-names = "default";
856 pinctrl-0 = <&pwm3a_pin>;
857 clocks = <&pmucru PCLK_RKPWM_PMU>;
862 pmucru: pmu-clock-controller@ff750000 {
863 compatible = "rockchip,rk3399-pmucru";
864 reg = <0x0 0xff750000 0x0 0x1000>;
867 assigned-clocks = <&pmucru PLL_PPLL>;
868 assigned-clock-rates = <676000000>;
871 cru: clock-controller@ff760000 {
872 compatible = "rockchip,rk3399-cru";
873 reg = <0x0 0xff760000 0x0 0x1000>;
877 <&cru ARMCLKL>, <&cru ARMCLKB>,
878 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
880 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
882 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
884 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
885 assigned-clock-rates =
886 <816000000>, <1008000000>,
887 <594000000>, <800000000>,
889 <150000000>, <75000000>,
891 <100000000>, <100000000>,
893 <100000000>, <50000000>;
896 grf: syscon@ff770000 {
897 compatible = "rockchip,rk3399-grf", "syscon";
898 reg = <0x0 0xff770000 0x0 0x10000>;
901 wdt0: watchdog@ff840000 {
902 compatible = "snps,dw-wdt";
903 reg = <0x0 0xff840000 0x0 0x100>;
904 clocks = <&cru PCLK_WDT>;
905 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
909 spdif: spdif@ff870000 {
910 compatible = "rockchip,rk3399-spdif";
911 reg = <0x0 0xff870000 0x0 0x1000>;
912 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
913 dmas = <&dmac_bus 7>;
915 clock-names = "mclk", "hclk";
916 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
917 pinctrl-names = "default";
918 pinctrl-0 = <&spdif_bus>;
923 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
924 reg = <0x0 0xff880000 0x0 0x1000>;
925 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
926 #address-cells = <1>;
928 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
929 dma-names = "tx", "rx";
930 clock-names = "i2s_clk", "i2s_hclk";
931 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
932 pinctrl-names = "default";
933 pinctrl-0 = <&i2s0_8ch_bus>;
938 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
939 reg = <0x0 0xff890000 0x0 0x1000>;
940 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
941 #address-cells = <1>;
943 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
944 dma-names = "tx", "rx";
945 clock-names = "i2s_clk", "i2s_hclk";
946 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
947 pinctrl-names = "default";
948 pinctrl-0 = <&i2s1_2ch_bus>;
953 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
954 reg = <0x0 0xff8a0000 0x0 0x1000>;
955 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
956 #address-cells = <1>;
958 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
959 dma-names = "tx", "rx";
960 clock-names = "i2s_clk", "i2s_hclk";
961 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
966 compatible = "arm,malit860",
971 reg = <0x0 0xff9a0000 0x0 0x10000>;
973 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
976 interrupt-names = "GPU", "JOB", "MMU";
978 clocks = <&cru ACLK_GPU>;
979 clock-names = "clk_mali";
980 operating-points-v2 = <&gpu_opp_table>;
984 gpu_opp_table: gpu_opp_table {
985 compatible = "operating-points-v2";
989 opp-hz = /bits/ 64 <200000000>;
990 opp-microvolt = <900000>;
993 opp-hz = /bits/ 64 <300000000>;
994 opp-microvolt = <900000>;
997 opp-hz = /bits/ 64 <400000000>;
998 opp-microvolt = <900000>;
1001 opp-hz = /bits/ 64 <500000000>;
1002 opp-microvolt = <900000>;
1006 vopl: vop@ff8f0000 {
1007 compatible = "rockchip,rk3399-vop-lit";
1008 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1009 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1011 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1012 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1013 reset-names = "axi", "ahb", "dclk";
1014 iommus = <&vopl_mmu>;
1015 status = "disabled";
1018 #address-cells = <1>;
1021 vopl_out_edp: endpoint@0 {
1023 remote-endpoint = <&edp_in_vopl>;
1026 vopl_out_mipi: endpoint@1 {
1028 remote-endpoint = <&mipi_in_vopl>;
1033 vopl_mmu: iommu@ff8f3f00 {
1034 compatible = "rockchip,iommu";
1035 reg = <0x0 0xff8f3f00 0x0 0x100>;
1036 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1037 interrupt-names = "vopl_mmu";
1039 status = "disabled";
1042 vopb: vop@ff900000 {
1043 compatible = "rockchip,rk3399-vop-big";
1044 reg = <0x0 0xff900000 0x0 0x3efc>;
1045 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1047 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1048 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1049 reset-names = "axi", "ahb", "dclk";
1050 iommus = <&vopb_mmu>;
1051 status = "disabled";
1054 #address-cells = <1>;
1057 vopb_out_edp: endpoint@0 {
1059 remote-endpoint = <&edp_in_vopb>;
1062 vopb_out_mipi: endpoint@1 {
1064 remote-endpoint = <&mipi_in_vopb>;
1069 vopb_mmu: iommu@ff903f00 {
1070 compatible = "rockchip,iommu";
1071 reg = <0x0 0xff903f00 0x0 0x100>;
1072 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1073 interrupt-names = "vopb_mmu";
1075 status = "disabled";
1078 mipi_dsi: mipi@ff960000 {
1079 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1080 reg = <0x0 0xff960000 0x0 0x8000>;
1081 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1083 <&cru SCLK_DPHY_TX0_CFG>;
1084 clock-names = "ref", "pclk", "phy_cfg";
1085 rockchip,grf = <&grf>;
1086 #address-cells = <1>;
1088 status = "disabled";
1091 #address-cells = <1>;
1096 #address-cells = <1>;
1099 mipi_in_vopb: endpoint@0 {
1101 remote-endpoint = <&vopb_out_mipi>;
1103 mipi_in_vopl: endpoint@1 {
1105 remote-endpoint = <&vopl_out_mipi>;
1112 compatible = "rockchip,rk3399-edp";
1113 reg = <0x0 0xff970000 0x0 0x8000>;
1114 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1115 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1116 clock-names = "dp", "pclk";
1117 resets = <&cru SRST_P_EDP_CTRL>;
1119 rockchip,grf = <&grf>;
1120 status = "disabled";
1121 pinctrl-names = "default";
1122 pinctrl-0 = <&edp_hpd>;
1125 #address-cells = <1>;
1130 #address-cells = <1>;
1133 edp_in_vopb: endpoint@0 {
1135 remote-endpoint = <&vopb_out_edp>;
1138 edp_in_vopl: endpoint@1 {
1140 remote-endpoint = <&vopl_out_edp>;
1146 display_subsystem: display-subsystem {
1147 compatible = "rockchip,display-subsystem";
1148 ports = <&vopl_out>, <&vopb_out>;
1149 status = "disabled";
1153 compatible = "rockchip,rk3399-pinctrl";
1154 rockchip,grf = <&grf>;
1155 rockchip,pmu = <&pmugrf>;
1156 #address-cells = <0x2>;
1157 #size-cells = <0x2>;
1160 gpio0: gpio0@ff720000 {
1161 compatible = "rockchip,gpio-bank";
1162 reg = <0x0 0xff720000 0x0 0x100>;
1163 clocks = <&pmucru PCLK_GPIO0_PMU>;
1164 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1167 #gpio-cells = <0x2>;
1169 interrupt-controller;
1170 #interrupt-cells = <0x2>;
1173 gpio1: gpio1@ff730000 {
1174 compatible = "rockchip,gpio-bank";
1175 reg = <0x0 0xff730000 0x0 0x100>;
1176 clocks = <&pmucru PCLK_GPIO1_PMU>;
1177 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1180 #gpio-cells = <0x2>;
1182 interrupt-controller;
1183 #interrupt-cells = <0x2>;
1186 gpio2: gpio2@ff780000 {
1187 compatible = "rockchip,gpio-bank";
1188 reg = <0x0 0xff780000 0x0 0x100>;
1189 clocks = <&cru PCLK_GPIO2>;
1190 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1193 #gpio-cells = <0x2>;
1195 interrupt-controller;
1196 #interrupt-cells = <0x2>;
1199 gpio3: gpio3@ff788000 {
1200 compatible = "rockchip,gpio-bank";
1201 reg = <0x0 0xff788000 0x0 0x100>;
1202 clocks = <&cru PCLK_GPIO3>;
1203 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1206 #gpio-cells = <0x2>;
1208 interrupt-controller;
1209 #interrupt-cells = <0x2>;
1212 gpio4: gpio4@ff790000 {
1213 compatible = "rockchip,gpio-bank";
1214 reg = <0x0 0xff790000 0x0 0x100>;
1215 clocks = <&cru PCLK_GPIO4>;
1216 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1219 #gpio-cells = <0x2>;
1221 interrupt-controller;
1222 #interrupt-cells = <0x2>;
1225 pcfg_pull_up: pcfg-pull-up {
1229 pcfg_pull_down: pcfg-pull-down {
1233 pcfg_pull_none: pcfg-pull-none {
1237 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1239 drive-strength = <12>;
1242 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1244 drive-strength = <8>;
1247 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1249 drive-strength = <4>;
1252 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1254 drive-strength = <2>;
1257 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1259 drive-strength = <12>;
1262 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1264 drive-strength = <13>;
1268 emmc_pwr: emmc-pwr {
1270 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1275 rgmii_pins: rgmii-pins {
1278 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1280 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1282 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1284 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1286 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1288 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1290 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1292 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1294 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1296 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1298 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1300 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1302 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1304 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1306 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1309 rmii_pins: rmii-pins {
1312 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1314 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1316 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1318 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1320 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1322 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1324 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1326 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1328 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1330 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1335 i2c0_xfer: i2c0-xfer {
1337 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1338 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1343 i2c1_xfer: i2c1-xfer {
1345 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1346 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1351 i2c2_xfer: i2c2-xfer {
1353 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1354 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1359 i2c3_xfer: i2c3-xfer {
1361 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1362 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1367 i2c4_xfer: i2c4-xfer {
1369 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1370 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1375 i2c5_xfer: i2c5-xfer {
1377 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1378 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1383 i2c6_xfer: i2c6-xfer {
1385 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1386 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1391 i2c7_xfer: i2c7-xfer {
1393 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1394 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1399 i2c8_xfer: i2c8-xfer {
1401 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1402 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1407 i2s0_8ch_bus: i2s0-8ch-bus {
1409 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1410 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1411 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1412 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1413 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1414 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1415 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1416 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1417 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1422 i2s1_2ch_bus: i2s1-2ch-bus {
1424 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1425 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1426 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1427 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1428 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1433 sdio0_bus1: sdio0-bus1 {
1435 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1438 sdio0_bus4: sdio0-bus4 {
1440 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1441 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1442 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1443 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1446 sdio0_cmd: sdio0-cmd {
1448 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1451 sdio0_clk: sdio0-clk {
1453 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1456 sdio0_cd: sdio0-cd {
1458 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1461 sdio0_pwr: sdio0-pwr {
1463 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1466 sdio0_bkpwr: sdio0-bkpwr {
1468 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1471 sdio0_wp: sdio0-wp {
1473 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1476 sdio0_int: sdio0-int {
1478 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1483 sdmmc_bus1: sdmmc-bus1 {
1485 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1488 sdmmc_bus4: sdmmc-bus4 {
1490 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1491 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1492 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1493 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1496 sdmmc_clk: sdmmc-clk {
1498 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1501 sdmmc_cmd: sdmmc-cmd {
1503 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1506 sdmmc_cd: sdmcc-cd {
1508 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1511 sdmmc_wp: sdmmc-wp {
1513 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1518 spdif_bus: spdif-bus {
1520 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1525 spi0_clk: spi0-clk {
1527 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1529 spi0_cs0: spi0-cs0 {
1531 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1533 spi0_cs1: spi0-cs1 {
1535 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1539 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1543 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1548 spi1_clk: spi1-clk {
1550 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1552 spi1_cs0: spi1-cs0 {
1554 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1558 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1562 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1567 spi2_clk: spi2-clk {
1569 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1571 spi2_cs0: spi2-cs0 {
1573 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1577 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1581 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1586 spi3_clk: spi3-clk {
1588 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1590 spi3_cs0: spi3-cs0 {
1592 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1596 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1600 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1605 spi4_clk: spi4-clk {
1607 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1609 spi4_cs0: spi4-cs0 {
1611 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1615 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1619 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1624 spi5_clk: spi5-clk {
1626 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1628 spi5_cs0: spi5-cs0 {
1630 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1634 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1638 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1643 otp_gpio: otp-gpio {
1644 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1648 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1653 uart0_xfer: uart0-xfer {
1655 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1656 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1659 uart0_cts: uart0-cts {
1661 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1664 uart0_rts: uart0-rts {
1666 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1671 uart1_xfer: uart1-xfer {
1673 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1674 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1679 uart2a_xfer: uart2a-xfer {
1681 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1682 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1687 uart2b_xfer: uart2b-xfer {
1689 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1690 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1695 uart2c_xfer: uart2c-xfer {
1697 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1698 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1703 uart3_xfer: uart3-xfer {
1705 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1706 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1709 uart3_cts: uart3-cts {
1711 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1714 uart3_rts: uart3-rts {
1716 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1721 uart4_xfer: uart4-xfer {
1723 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1724 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1729 uarthdcp_xfer: uarthdcp-xfer {
1731 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1732 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1737 pwm0_pin: pwm0-pin {
1739 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1742 vop0_pwm_pin: vop0-pwm-pin {
1744 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1749 pwm1_pin: pwm1-pin {
1751 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1754 vop1_pwm_pin: vop1-pwm-pin {
1756 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1761 pwm2_pin: pwm2-pin {
1763 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1768 pwm3a_pin: pwm3a-pin {
1770 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1775 pwm3b_pin: pwm3b-pin {
1777 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1782 pmic_int_l: pmic-int-l {
1784 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
1791 <4 23 RK_FUNC_2 &pcfg_pull_none>;