arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/suspend/rockchip-rk3399.h>
  51 #include <dt-bindings/thermal/thermal.h>
  52
  53 #include "rk3399-dram-default-timing.dtsi"
  54
  55 / {
  56         compatible = "rockchip,rk3399";
  57
  58         interrupt-parent = <&gic>;
  59         #address-cells = <2>;
  60         #size-cells = <2>;
  61
  62         aliases {
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 i2c6 = &i2c6;
  70                 i2c7 = &i2c7;
  71                 i2c8 = &i2c8;
  72                 serial0 = &uart0;
  73                 serial1 = &uart1;
  74                 serial2 = &uart2;
  75                 serial3 = &uart3;
  76                 serial4 = &uart4;
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         dynamic-power-coefficient = <100>;
 116                         clocks = <&cru ARMCLKL>;
 117                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 118                 };
 119
 120                 cpu_l1: cpu@1 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53", "arm,armv8";
 123                         reg = <0x0 0x1>;
 124                         enable-method = "psci";
 125                         clocks = <&cru ARMCLKL>;
 126                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 127                 };
 128
 129                 cpu_l2: cpu@2 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a53", "arm,armv8";
 132                         reg = <0x0 0x2>;
 133                         enable-method = "psci";
 134                         clocks = <&cru ARMCLKL>;
 135                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 136                 };
 137
 138                 cpu_l3: cpu@3 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a53", "arm,armv8";
 141                         reg = <0x0 0x3>;
 142                         enable-method = "psci";
 143                         clocks = <&cru ARMCLKL>;
 144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 145                 };
 146
 147                 cpu_b0: cpu@100 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x100>;
 151                         enable-method = "psci";
 152                         #cooling-cells = <2>; /* min followed by max */
 153                         dynamic-power-coefficient = <436>;
 154                         clocks = <&cru ARMCLKB>;
 155                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 156                 };
 157
 158                 cpu_b1: cpu@101 {
 159                         device_type = "cpu";
 160                         compatible = "arm,cortex-a72", "arm,armv8";
 161                         reg = <0x0 0x101>;
 162                         enable-method = "psci";
 163                         clocks = <&cru ARMCLKB>;
 164                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 165                 };
 166
 167                 idle-states {
 168                         entry-method = "psci";
 169
 170                         CPU_SLEEP: cpu-sleep {
 171                                 compatible = "arm,idle-state";
 172                                 local-timer-stop;
 173                                 arm,psci-suspend-param = <0x0010000>;
 174                                 entry-latency-us = <120>;
 175                                 exit-latency-us = <250>;
 176                                 min-residency-us = <900>;
 177                         };
 178
 179                         CLUSTER_SLEEP: cluster-sleep {
 180                                 compatible = "arm,idle-state";
 181                                 local-timer-stop;
 182                                 arm,psci-suspend-param = <0x1010000>;
 183                                 entry-latency-us = <400>;
 184                                 exit-latency-us = <500>;
 185                                 min-residency-us = <2000>;
 186                         };
 187                 };
 188         };
 189
 190         pmu_a53 {
 191                 compatible = "arm,cortex-a53-pmu";
 192                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 193         };
 194
 195         pmu_a72 {
 196                 compatible = "arm,cortex-a72-pmu";
 197                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 198         };
 199
 200         psci {
 201                 compatible = "arm,psci-1.0";
 202                 method = "smc";
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv8-timer";
 207                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 208                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 209                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 210                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 211         };
 212
 213         xin24m: xin24m {
 214                 compatible = "fixed-clock";
 215                 clock-frequency = <24000000>;
 216                 clock-output-names = "xin24m";
 217                 #clock-cells = <0>;
 218         };
 219
 220         dummy_cpll: dummy_cpll {
 221                 compatible = "fixed-clock";
 222                 clock-frequency = <0>;
 223                 clock-output-names = "dummy_cpll";
 224                 #clock-cells = <0>;
 225         };
 226
 227         dummy_vpll: dummy_vpll {
 228                 compatible = "fixed-clock";
 229                 clock-frequency = <0>;
 230                 clock-output-names = "dummy_vpll";
 231                 #clock-cells = <0>;
 232         };
 233
 234         amba {
 235                 compatible = "arm,amba-bus";
 236                 #address-cells = <2>;
 237                 #size-cells = <2>;
 238                 ranges;
 239
 240                 dmac_bus: dma-controller@ff6d0000 {
 241                         compatible = "arm,pl330", "arm,primecell";
 242                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 243                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 244                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 245                         #dma-cells = <1>;
 246                         clocks = <&cru ACLK_DMAC0_PERILP>;
 247                         clock-names = "apb_pclk";
 248                         peripherals-req-type-burst;
 249                 };
 250
 251                 dmac_peri: dma-controller@ff6e0000 {
 252                         compatible = "arm,pl330", "arm,primecell";
 253                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 254                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 255                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 256                         #dma-cells = <1>;
 257                         clocks = <&cru ACLK_DMAC1_PERILP>;
 258                         clock-names = "apb_pclk";
 259                         peripherals-req-type-burst;
 260                 };
 261         };
 262
 263         gmac: ethernet@fe300000 {
 264                 compatible = "rockchip,rk3399-gmac";
 265                 reg = <0x0 0xfe300000 0x0 0x10000>;
 266                 rockchip,grf = <&grf>;
 267                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 268                 interrupt-names = "macirq";
 269                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 270                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 271                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 272                          <&cru PCLK_GMAC>;
 273                 clock-names = "stmmaceth", "mac_clk_rx",
 274                               "mac_clk_tx", "clk_mac_ref",
 275                               "clk_mac_refout", "aclk_mac",
 276                               "pclk_mac";
 277                 resets = <&cru SRST_A_GMAC>;
 278                 reset-names = "stmmaceth";
 279                 power-domains = <&power RK3399_PD_GMAC>;
 280                 status = "disabled";
 281         };
 282
 283         sdio0: dwmmc@fe310000 {
 284                 compatible = "rockchip,rk3399-dw-mshc",
 285                              "rockchip,rk3288-dw-mshc";
 286                 reg = <0x0 0xfe310000 0x0 0x4000>;
 287                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 288                 clock-freq-min-max = <400000 150000000>;
 289                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 290                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 291                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 292                 fifo-depth = <0x100>;
 293                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 294                 status = "disabled";
 295         };
 296
 297         sdmmc: dwmmc@fe320000 {
 298                 compatible = "rockchip,rk3399-dw-mshc",
 299                              "rockchip,rk3288-dw-mshc";
 300                 reg = <0x0 0xfe320000 0x0 0x4000>;
 301                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 302                 clock-freq-min-max = <400000 150000000>;
 303                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 304                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 305                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 306                 fifo-depth = <0x100>;
 307                 power-domains = <&power RK3399_PD_SD>;
 308                 status = "disabled";
 309         };
 310
 311         sdhci: sdhci@fe330000 {
 312                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 313                 reg = <0x0 0xfe330000 0x0 0x10000>;
 314                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 315                 arasan,soc-ctl-syscon = <&grf>;
 316                 assigned-clocks = <&cru SCLK_EMMC>;
 317                 assigned-clock-rates = <200000000>;
 318                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 319                 clock-names = "clk_xin", "clk_ahb";
 320                 clock-output-names = "emmc_cardclock";
 321                 #clock-cells = <0>;
 322                 phys = <&emmc_phy>;
 323                 phy-names = "phy_arasan";
 324                 power-domains = <&power RK3399_PD_EMMC>;
 325                 status = "disabled";
 326         };
 327
 328         usb_host0_ehci: usb@fe380000 {
 329                 compatible = "generic-ehci";
 330                 reg = <0x0 0xfe380000 0x0 0x20000>;
 331                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 332                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 333                          <&cru SCLK_USBPHY0_480M_SRC>;
 334                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 335                 phys = <&u2phy0_host>;
 336                 phy-names = "usb";
 337                 power-domains = <&power RK3399_PD_PERIHP>;
 338                 status = "disabled";
 339         };
 340
 341         usb_host0_ohci: usb@fe3a0000 {
 342                 compatible = "generic-ohci";
 343                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 344                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 345                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 346                          <&cru SCLK_USBPHY0_480M_SRC>;
 347                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 348                 phys = <&u2phy0_host>;
 349                 phy-names = "usb";
 350                 power-domains = <&power RK3399_PD_PERIHP>;
 351                 status = "disabled";
 352         };
 353
 354         usb_host1_ehci: usb@fe3c0000 {
 355                 compatible = "generic-ehci";
 356                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 357                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 358                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 359                          <&cru SCLK_USBPHY1_480M_SRC>;
 360                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 361                 phys = <&u2phy1_host>;
 362                 phy-names = "usb";
 363                 power-domains = <&power RK3399_PD_PERIHP>;
 364                 status = "disabled";
 365         };
 366
 367         usb_host1_ohci: usb@fe3e0000 {
 368                 compatible = "generic-ohci";
 369                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 370                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 371                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 372                          <&cru SCLK_USBPHY1_480M_SRC>;
 373                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 374                 phys = <&u2phy1_host>;
 375                 phy-names = "usb";
 376                 power-domains = <&power RK3399_PD_PERIHP>;
 377                 status = "disabled";
 378         };
 379
 380         usbdrd3_0: usb@fe800000 {
 381                 compatible = "rockchip,rk3399-dwc3";
 382                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 383                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 384                 clock-names = "ref_clk", "suspend_clk",
 385                               "bus_clk", "grf_clk";
 386                 power-domains = <&power RK3399_PD_USB3>;
 387                 resets = <&cru SRST_A_USB3_OTG0>;
 388                 reset-names = "usb3-otg";
 389                 #address-cells = <2>;
 390                 #size-cells = <2>;
 391                 ranges;
 392                 status = "disabled";
 393                 usbdrd_dwc3_0: dwc3@fe800000 {
 394                         compatible = "snps,dwc3";
 395                         reg = <0x0 0xfe800000 0x0 0x100000>;
 396                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 397                         dr_mode = "otg";
 398                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 399                         phy-names = "usb2-phy", "usb3-phy";
 400                         phy_type = "utmi_wide";
 401                         snps,dis_enblslpm_quirk;
 402                         snps,dis-u2-freeclk-exists-quirk;
 403                         snps,dis_u2_susphy_quirk;
 404                         snps,dis-del-phy-power-chg-quirk;
 405                         snps,xhci-slow-suspend-quirk;
 406                         status = "disabled";
 407                 };
 408         };
 409
 410         usbdrd3_1: usb@fe900000 {
 411                 compatible = "rockchip,rk3399-dwc3";
 412                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 413                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 414                 clock-names = "ref_clk", "suspend_clk",
 415                               "bus_clk", "grf_clk";
 416                 power-domains = <&power RK3399_PD_USB3>;
 417                 resets = <&cru SRST_A_USB3_OTG1>;
 418                 reset-names = "usb3-otg";
 419                 #address-cells = <2>;
 420                 #size-cells = <2>;
 421                 ranges;
 422                 status = "disabled";
 423                 usbdrd_dwc3_1: dwc3@fe900000 {
 424                         compatible = "snps,dwc3";
 425                         reg = <0x0 0xfe900000 0x0 0x100000>;
 426                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 427                         dr_mode = "host";
 428                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 429                         phy-names = "usb2-phy", "usb3-phy";
 430                         phy_type = "utmi_wide";
 431                         snps,dis_enblslpm_quirk;
 432                         snps,dis-u2-freeclk-exists-quirk;
 433                         snps,dis_u2_susphy_quirk;
 434                         snps,dis-del-phy-power-chg-quirk;
 435                         snps,xhci-slow-suspend-quirk;
 436                         status = "disabled";
 437                 };
 438         };
 439
 440         cdn_dp: dp@fec00000 {
 441                 compatible = "rockchip,rk3399-cdn-dp";
 442                 reg = <0x0 0xfec00000 0x0 0x100000>;
 443                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 444                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 445                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 446                 clock-names = "core-clk", "pclk", "spdif", "grf";
 447                 assigned-clocks = <&cru SCLK_DP_CORE>;
 448                 assigned-clock-rates = <100000000>;
 449                 power-domains = <&power RK3399_PD_HDCP>;
 450                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 451                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 452                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 453                 reset-names = "spdif", "dptx", "apb", "core";
 454                 rockchip,grf = <&grf>;
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 #sound-dai-cells = <1>;
 458                 status = "disabled";
 459
 460                 ports {
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463
 464                         dp_in: port {
 465                                 #address-cells = <1>;
 466                                 #size-cells = <0>;
 467                                 dp_in_vopb: endpoint@0 {
 468                                         reg = <0>;
 469                                         remote-endpoint = <&vopb_out_dp>;
 470                                 };
 471
 472                                 dp_in_vopl: endpoint@1 {
 473                                         reg = <1>;
 474                                         remote-endpoint = <&vopl_out_dp>;
 475                                 };
 476                         };
 477                 };
 478         };
 479
 480         gic: interrupt-controller@fee00000 {
 481                 compatible = "arm,gic-v3";
 482                 #interrupt-cells = <4>;
 483                 #address-cells = <2>;
 484                 #size-cells = <2>;
 485                 ranges;
 486                 interrupt-controller;
 487
 488                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 489                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 490                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 491                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 492                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 493                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 494                 its: interrupt-controller@fee20000 {
 495                         compatible = "arm,gic-v3-its";
 496                         msi-controller;
 497                         reg = <0x0 0xfee20000 0x0 0x20000>;
 498                 };
 499
 500                 ppi-partitions {
 501                         ppi_cluster0: interrupt-partition-0 {
 502                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 503                         };
 504
 505                         ppi_cluster1: interrupt-partition-1 {
 506                                 affinity = <&cpu_b0 &cpu_b1>;
 507                         };
 508                 };
 509         };
 510
 511         saradc: saradc@ff100000 {
 512                 compatible = "rockchip,rk3399-saradc";
 513                 reg = <0x0 0xff100000 0x0 0x100>;
 514                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 515                 #io-channel-cells = <1>;
 516                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 517                 clock-names = "saradc", "apb_pclk";
 518                 resets = <&cru SRST_P_SARADC>;
 519                 reset-names = "saradc-apb";
 520                 status = "disabled";
 521         };
 522
 523         i2c0: i2c@ff3c0000 {
 524                 compatible = "rockchip,rk3399-i2c";
 525                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 526                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 527                 clock-names = "i2c", "pclk";
 528                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 529                 pinctrl-names = "default";
 530                 pinctrl-0 = <&i2c0_xfer>;
 531                 #address-cells = <1>;
 532                 #size-cells = <0>;
 533                 status = "disabled";
 534         };
 535
 536         i2c1: i2c@ff110000 {
 537                 compatible = "rockchip,rk3399-i2c";
 538                 reg = <0x0 0xff110000 0x0 0x1000>;
 539                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 540                 clock-names = "i2c", "pclk";
 541                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 542                 pinctrl-names = "default";
 543                 pinctrl-0 = <&i2c1_xfer>;
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 status = "disabled";
 547         };
 548
 549         i2c2: i2c@ff120000 {
 550                 compatible = "rockchip,rk3399-i2c";
 551                 reg = <0x0 0xff120000 0x0 0x1000>;
 552                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 553                 clock-names = "i2c", "pclk";
 554                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 555                 pinctrl-names = "default";
 556                 pinctrl-0 = <&i2c2_xfer>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 status = "disabled";
 560         };
 561
 562         i2c3: i2c@ff130000 {
 563                 compatible = "rockchip,rk3399-i2c";
 564                 reg = <0x0 0xff130000 0x0 0x1000>;
 565                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 566                 clock-names = "i2c", "pclk";
 567                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 568                 pinctrl-names = "default";
 569                 pinctrl-0 = <&i2c3_xfer>;
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 status = "disabled";
 573         };
 574
 575         i2c5: i2c@ff140000 {
 576                 compatible = "rockchip,rk3399-i2c";
 577                 reg = <0x0 0xff140000 0x0 0x1000>;
 578                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 579                 clock-names = "i2c", "pclk";
 580                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 581                 pinctrl-names = "default";
 582                 pinctrl-0 = <&i2c5_xfer>;
 583                 #address-cells = <1>;
 584                 #size-cells = <0>;
 585                 status = "disabled";
 586         };
 587
 588         i2c6: i2c@ff150000 {
 589                 compatible = "rockchip,rk3399-i2c";
 590                 reg = <0x0 0xff150000 0x0 0x1000>;
 591                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 592                 clock-names = "i2c", "pclk";
 593                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 594                 pinctrl-names = "default";
 595                 pinctrl-0 = <&i2c6_xfer>;
 596                 #address-cells = <1>;
 597                 #size-cells = <0>;
 598                 status = "disabled";
 599         };
 600
 601         i2c7: i2c@ff160000 {
 602                 compatible = "rockchip,rk3399-i2c";
 603                 reg = <0x0 0xff160000 0x0 0x1000>;
 604                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 605                 clock-names = "i2c", "pclk";
 606                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 607                 pinctrl-names = "default";
 608                 pinctrl-0 = <&i2c7_xfer>;
 609                 #address-cells = <1>;
 610                 #size-cells = <0>;
 611                 status = "disabled";
 612         };
 613
 614         uart0: serial@ff180000 {
 615                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 616                 reg = <0x0 0xff180000 0x0 0x100>;
 617                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 618                 clock-names = "baudclk", "apb_pclk";
 619                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 620                 reg-shift = <2>;
 621                 reg-io-width = <4>;
 622                 pinctrl-names = "default";
 623                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 624                 status = "disabled";
 625         };
 626
 627         uart1: serial@ff190000 {
 628                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 629                 reg = <0x0 0xff190000 0x0 0x100>;
 630                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 631                 clock-names = "baudclk", "apb_pclk";
 632                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 633                 reg-shift = <2>;
 634                 reg-io-width = <4>;
 635                 pinctrl-names = "default";
 636                 pinctrl-0 = <&uart1_xfer>;
 637                 status = "disabled";
 638         };
 639
 640         uart2: serial@ff1a0000 {
 641                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 642                 reg = <0x0 0xff1a0000 0x0 0x100>;
 643                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 644                 clock-names = "baudclk", "apb_pclk";
 645                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 646                 reg-shift = <2>;
 647                 reg-io-width = <4>;
 648                 pinctrl-names = "default";
 649                 pinctrl-0 = <&uart2c_xfer>;
 650                 status = "disabled";
 651         };
 652
 653         uart3: serial@ff1b0000 {
 654                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 655                 reg = <0x0 0xff1b0000 0x0 0x100>;
 656                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 657                 clock-names = "baudclk", "apb_pclk";
 658                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 659                 reg-shift = <2>;
 660                 reg-io-width = <4>;
 661                 pinctrl-names = "default";
 662                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 663                 status = "disabled";
 664         };
 665
 666         spi0: spi@ff1c0000 {
 667                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 668                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 669                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 670                 clock-names = "spiclk", "apb_pclk";
 671                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 672                 pinctrl-names = "default";
 673                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 674                 #address-cells = <1>;
 675                 #size-cells = <0>;
 676                 status = "disabled";
 677         };
 678
 679         spi1: spi@ff1d0000 {
 680                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 681                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 682                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 683                 clock-names = "spiclk", "apb_pclk";
 684                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 685                 pinctrl-names = "default";
 686                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 687                 #address-cells = <1>;
 688                 #size-cells = <0>;
 689                 status = "disabled";
 690         };
 691
 692         spi2: spi@ff1e0000 {
 693                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 694                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 695                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 696                 clock-names = "spiclk", "apb_pclk";
 697                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 698                 pinctrl-names = "default";
 699                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 700                 #address-cells = <1>;
 701                 #size-cells = <0>;
 702                 status = "disabled";
 703         };
 704
 705         spi4: spi@ff1f0000 {
 706                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 707                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 708                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 709                 clock-names = "spiclk", "apb_pclk";
 710                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 711                 pinctrl-names = "default";
 712                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 713                 #address-cells = <1>;
 714                 #size-cells = <0>;
 715                 status = "disabled";
 716         };
 717
 718         spi5: spi@ff200000 {
 719                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 720                 reg = <0x0 0xff200000 0x0 0x1000>;
 721                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 722                 clock-names = "spiclk", "apb_pclk";
 723                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 724                 pinctrl-names = "default";
 725                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 726                 #address-cells = <1>;
 727                 #size-cells = <0>;
 728                 status = "disabled";
 729         };
 730
 731         thermal_zones: thermal-zones {
 732                 soc_thermal: soc-thermal {
 733                         polling-delay-passive = <20>; /* milliseconds */
 734                         polling-delay = <1000>; /* milliseconds */
 735                         sustainable-power = <1000>; /* milliwatts */
 736
 737                         thermal-sensors = <&tsadc 0>;
 738
 739                         trips {
 740                                 threshold: trip-point@0 {
 741                                         temperature = <70000>; /* millicelsius */
 742                                         hysteresis = <2000>; /* millicelsius */
 743                                         type = "passive";
 744                                 };
 745                                 target: trip-point@1 {
 746                                         temperature = <85000>; /* millicelsius */
 747                                         hysteresis = <2000>; /* millicelsius */
 748                                         type = "passive";
 749                                 };
 750                                 soc_crit: soc-crit {
 751                                         temperature = <95000>; /* millicelsius */
 752                                         hysteresis = <2000>; /* millicelsius */
 753                                         type = "critical";
 754                                 };
 755                         };
 756
 757                         cooling-maps {
 758                                 map0 {
 759                                         trip = <&target>;
 760                                         cooling-device =
 761                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 762                                         contribution = <4096>;
 763                                 };
 764                                 map1 {
 765                                         trip = <&target>;
 766                                         cooling-device =
 767                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 768                                         contribution = <1024>;
 769                                 };
 770                                 map2 {
 771                                         trip = <&target>;
 772                                         cooling-device =
 773                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 774                                         contribution = <4096>;
 775                                 };
 776                         };
 777                 };
 778
 779                 gpu_thermal: gpu-thermal {
 780                         polling-delay-passive = <100>; /* milliseconds */
 781                         polling-delay = <1000>; /* milliseconds */
 782
 783                         thermal-sensors = <&tsadc 1>;
 784                 };
 785         };
 786
 787         tsadc: tsadc@ff260000 {
 788                 compatible = "rockchip,rk3399-tsadc";
 789                 reg = <0x0 0xff260000 0x0 0x100>;
 790                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 791                 rockchip,grf = <&grf>;
 792                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 793                 clock-names = "tsadc", "apb_pclk";
 794                 assigned-clocks = <&cru SCLK_TSADC>;
 795                 assigned-clock-rates = <750000>;
 796                 resets = <&cru SRST_TSADC>;
 797                 reset-names = "tsadc-apb";
 798                 pinctrl-names = "init", "default", "sleep";
 799                 pinctrl-0 = <&otp_gpio>;
 800                 pinctrl-1 = <&otp_out>;
 801                 pinctrl-2 = <&otp_gpio>;
 802                 #thermal-sensor-cells = <1>;
 803                 rockchip,hw-tshut-temp = <95000>;
 804                 status = "disabled";
 805         };
 806
 807         qos_emmc: qos@ffa58000 {
 808                 compatible = "syscon";
 809                 reg = <0x0 0xffa58000 0x0 0x20>;
 810         };
 811
 812         qos_gmac: qos@ffa5c000 {
 813                 compatible = "syscon";
 814                 reg = <0x0 0xffa5c000 0x0 0x20>;
 815         };
 816
 817         qos_pcie: qos@ffa60080 {
 818                 compatible = "syscon";
 819                 reg = <0x0 0xffa60080 0x0 0x20>;
 820         };
 821
 822         qos_usb_host0: qos@ffa60100 {
 823                 compatible = "syscon";
 824                 reg = <0x0 0xffa60100 0x0 0x20>;
 825         };
 826
 827         qos_usb_host1: qos@ffa60180 {
 828                 compatible = "syscon";
 829                 reg = <0x0 0xffa60180 0x0 0x20>;
 830         };
 831
 832         qos_usb_otg0: qos@ffa70000 {
 833                 compatible = "syscon";
 834                 reg = <0x0 0xffa70000 0x0 0x20>;
 835         };
 836
 837         qos_usb_otg1: qos@ffa70080 {
 838                 compatible = "syscon";
 839                 reg = <0x0 0xffa70080 0x0 0x20>;
 840         };
 841
 842         qos_sd: qos@ffa74000 {
 843                 compatible = "syscon";
 844                 reg = <0x0 0xffa74000 0x0 0x20>;
 845         };
 846
 847         qos_sdioaudio: qos@ffa76000 {
 848                 compatible = "syscon";
 849                 reg = <0x0 0xffa76000 0x0 0x20>;
 850         };
 851
 852         qos_hdcp: qos@ffa90000 {
 853                 compatible = "syscon";
 854                 reg = <0x0 0xffa90000 0x0 0x20>;
 855         };
 856
 857         qos_iep: qos@ffa98000 {
 858                 compatible = "syscon";
 859                 reg = <0x0 0xffa98000 0x0 0x20>;
 860         };
 861
 862         qos_isp0_m0: qos@ffaa0000 {
 863                 compatible = "syscon";
 864                 reg = <0x0 0xffaa0000 0x0 0x20>;
 865         };
 866
 867         qos_isp0_m1: qos@ffaa0080 {
 868                 compatible = "syscon";
 869                 reg = <0x0 0xffaa0080 0x0 0x20>;
 870         };
 871
 872         qos_isp1_m0: qos@ffaa8000 {
 873                 compatible = "syscon";
 874                 reg = <0x0 0xffaa8000 0x0 0x20>;
 875         };
 876
 877         qos_isp1_m1: qos@ffaa8080 {
 878                 compatible = "syscon";
 879                 reg = <0x0 0xffaa8080 0x0 0x20>;
 880         };
 881
 882         qos_rga_r: qos@ffab0000 {
 883                 compatible = "syscon";
 884                 reg = <0x0 0xffab0000 0x0 0x20>;
 885         };
 886
 887         qos_rga_w: qos@ffab0080 {
 888                 compatible = "syscon";
 889                 reg = <0x0 0xffab0080 0x0 0x20>;
 890         };
 891
 892         qos_video_m0: qos@ffab8000 {
 893                 compatible = "syscon";
 894                 reg = <0x0 0xffab8000 0x0 0x20>;
 895         };
 896
 897         qos_video_m1_r: qos@ffac0000 {
 898                 compatible = "syscon";
 899                 reg = <0x0 0xffac0000 0x0 0x20>;
 900         };
 901
 902         qos_video_m1_w: qos@ffac0080 {
 903                 compatible = "syscon";
 904                 reg = <0x0 0xffac0080 0x0 0x20>;
 905         };
 906
 907         qos_vop_big_r: qos@ffac8000 {
 908                 compatible = "syscon";
 909                 reg = <0x0 0xffac8000 0x0 0x20>;
 910         };
 911
 912         qos_vop_big_w: qos@ffac8080 {
 913                 compatible = "syscon";
 914                 reg = <0x0 0xffac8080 0x0 0x20>;
 915         };
 916
 917         qos_vop_little: qos@ffad0000 {
 918                 compatible = "syscon";
 919                 reg = <0x0 0xffad0000 0x0 0x20>;
 920         };
 921
 922         qos_perihp: qos@ffad8080 {
 923                 compatible = "syscon";
 924                 reg = <0x0 0xffad8080 0x0 0x20>;
 925         };
 926
 927         qos_gpu: qos@ffae0000 {
 928                 compatible = "syscon";
 929                 reg = <0x0 0xffae0000 0x0 0x20>;
 930         };
 931
 932         pmu: power-management@ff310000 {
 933                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 934                 reg = <0x0 0xff310000 0x0 0x1000>;
 935
 936                 /*
 937                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 938                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 939                  * Some of the power domains are grouped together for every
 940                  * voltage domain.
 941                  * The detail contents as below.
 942                  */
 943                 power: power-controller {
 944                         compatible = "rockchip,rk3399-power-controller";
 945                         #power-domain-cells = <1>;
 946                         #address-cells = <1>;
 947                         #size-cells = <0>;
 948
 949                         /* These power domains are grouped by VD_CENTER */
 950                         pd_iep@RK3399_PD_IEP {
 951                                 reg = <RK3399_PD_IEP>;
 952                                 clocks = <&cru ACLK_IEP>,
 953                                          <&cru HCLK_IEP>;
 954                                 pm_qos = <&qos_iep>;
 955                         };
 956                         pd_rga@RK3399_PD_RGA {
 957                                 reg = <RK3399_PD_RGA>;
 958                                 clocks = <&cru ACLK_RGA>,
 959                                          <&cru HCLK_RGA>;
 960                                 pm_qos = <&qos_rga_r>,
 961                                          <&qos_rga_w>;
 962                         };
 963                         pd_vcodec@RK3399_PD_VCODEC {
 964                                 reg = <RK3399_PD_VCODEC>;
 965                                 clocks = <&cru ACLK_VCODEC>,
 966                                          <&cru HCLK_VCODEC>;
 967                                 pm_qos = <&qos_video_m0>;
 968                         };
 969                         pd_vdu@RK3399_PD_VDU {
 970                                 reg = <RK3399_PD_VDU>;
 971                                 clocks = <&cru ACLK_VDU>,
 972                                          <&cru HCLK_VDU>;
 973                                 pm_qos = <&qos_video_m1_r>,
 974                                          <&qos_video_m1_w>;
 975                         };
 976
 977                         /* These power domains are grouped by VD_GPU */
 978                         pd_gpu@RK3399_PD_GPU {
 979                                 reg = <RK3399_PD_GPU>;
 980                                 clocks = <&cru ACLK_GPU>;
 981                                 pm_qos = <&qos_gpu>;
 982                         };
 983
 984                         /* These power domains are grouped by VD_LOGIC */
 985                         pd_edp@RK3399_PD_EDP {
 986                                 reg = <RK3399_PD_EDP>;
 987                                 clocks = <&cru PCLK_EDP_CTRL>;
 988                         };
 989                         pd_emmc@RK3399_PD_EMMC {
 990                                 reg = <RK3399_PD_EMMC>;
 991                                 clocks = <&cru ACLK_EMMC>;
 992                                 pm_qos = <&qos_emmc>;
 993                         };
 994                         pd_gmac@RK3399_PD_GMAC {
 995                                 reg = <RK3399_PD_GMAC>;
 996                                 clocks = <&cru ACLK_GMAC>,
 997                                          <&cru PCLK_GMAC>;
 998                                 pm_qos = <&qos_gmac>;
 999                         };
1000                         pd_perihp@RK3399_PD_PERIHP {
1001                                 reg = <RK3399_PD_PERIHP>;
1002                                 #address-cells = <1>;
1003                                 #size-cells = <0>;
1004                                 clocks = <&cru ACLK_PERIHP>;
1005                                 pm_qos = <&qos_perihp>,
1006                                          <&qos_pcie>,
1007                                          <&qos_usb_host0>,
1008                                          <&qos_usb_host1>;
1009
1010                                 pd_sd@RK3399_PD_SD {
1011                                         reg = <RK3399_PD_SD>;
1012                                         clocks = <&cru HCLK_SDMMC>,
1013                                                  <&cru SCLK_SDMMC>;
1014                                         pm_qos = <&qos_sd>;
1015                                 };
1016                         };
1017                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1018                                 reg = <RK3399_PD_SDIOAUDIO>;
1019                                 clocks = <&cru HCLK_SDIO>;
1020                                 pm_qos = <&qos_sdioaudio>;
1021                         };
1022                         pd_usb3@RK3399_PD_USB3 {
1023                                 reg = <RK3399_PD_USB3>;
1024                                 clocks = <&cru ACLK_USB3>;
1025                                 pm_qos = <&qos_usb_otg0>,
1026                                          <&qos_usb_otg1>;
1027                         };
1028                         pd_vio@RK3399_PD_VIO {
1029                                 reg = <RK3399_PD_VIO>;
1030                                 #address-cells = <1>;
1031                                 #size-cells = <0>;
1032
1033                                 pd_hdcp@RK3399_PD_HDCP {
1034                                         reg = <RK3399_PD_HDCP>;
1035                                         clocks = <&cru ACLK_HDCP>,
1036                                                  <&cru HCLK_HDCP>,
1037                                                  <&cru PCLK_HDCP>;
1038                                         pm_qos = <&qos_hdcp>;
1039                                 };
1040                                 pd_isp0@RK3399_PD_ISP0 {
1041                                         reg = <RK3399_PD_ISP0>;
1042                                         clocks = <&cru ACLK_ISP0>,
1043                                                  <&cru HCLK_ISP0>;
1044                                         pm_qos = <&qos_isp0_m0>,
1045                                                  <&qos_isp0_m1>;
1046                                 };
1047                                 pd_isp1@RK3399_PD_ISP1 {
1048                                         reg = <RK3399_PD_ISP1>;
1049                                         clocks = <&cru ACLK_ISP1>,
1050                                                  <&cru HCLK_ISP1>;
1051                                         pm_qos = <&qos_isp1_m0>,
1052                                                  <&qos_isp1_m1>;
1053                                 };
1054                                 pd_tcpc0@RK3399_PD_TCPC0 {
1055                                         reg = <RK3399_PD_TCPD0>;
1056                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1057                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1058                                 };
1059                                 pd_tcpc1@RK3399_PD_TCPC1 {
1060                                         reg = <RK3399_PD_TCPD1>;
1061                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1062                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1063                                 };
1064                                 pd_vo@RK3399_PD_VO {
1065                                         reg = <RK3399_PD_VO>;
1066                                         #address-cells = <1>;
1067                                         #size-cells = <0>;
1068
1069                                         pd_vopb@RK3399_PD_VOPB {
1070                                                 reg = <RK3399_PD_VOPB>;
1071                                                 clocks = <&cru ACLK_VOP0>,
1072                                                          <&cru HCLK_VOP0>;
1073                                                 pm_qos = <&qos_vop_big_r>,
1074                                                          <&qos_vop_big_w>;
1075                                         };
1076                                         pd_vopl@RK3399_PD_VOPL {
1077                                                 reg = <RK3399_PD_VOPL>;
1078                                                 clocks = <&cru ACLK_VOP1>,
1079                                                          <&cru HCLK_VOP1>;
1080                                                 pm_qos = <&qos_vop_little>;
1081                                         };
1082                                 };
1083                         };
1084                 };
1085         };
1086
1087         pmugrf: syscon@ff320000 {
1088                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1089                 reg = <0x0 0xff320000 0x0 0x1000>;
1090                 #address-cells = <1>;
1091                 #size-cells = <1>;
1092
1093                 pmu_io_domains: io-domains {
1094                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1095                         status = "disabled";
1096                 };
1097
1098                 reboot-mode {
1099                         compatible = "syscon-reboot-mode";
1100                         offset = <0x300>;
1101                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
1102                         mode-charge = <BOOT_CHARGING>;
1103                         mode-fastboot = <BOOT_FASTBOOT>;
1104                         mode-loader = <BOOT_BL_DOWNLOAD>;
1105                         mode-normal = <BOOT_NORMAL>;
1106                         mode-recovery = <BOOT_RECOVERY>;
1107                         mode-ums = <BOOT_UMS>;
1108                 };
1109
1110                 pmu_pvtm: pmu-pvtm {
1111                         compatible = "rockchip,rk3399-pmu-pvtm";
1112                         clocks = <&pmucru SCLK_PVTM_PMU>;
1113                         clock-names = "pmu";
1114                         status = "disabled";
1115                 };
1116         };
1117
1118         spi3: spi@ff350000 {
1119                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1120                 reg = <0x0 0xff350000 0x0 0x1000>;
1121                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1122                 clock-names = "spiclk", "apb_pclk";
1123                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1124                 pinctrl-names = "default";
1125                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1126                 #address-cells = <1>;
1127                 #size-cells = <0>;
1128                 status = "disabled";
1129         };
1130
1131         uart4: serial@ff370000 {
1132                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1133                 reg = <0x0 0xff370000 0x0 0x100>;
1134                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1135                 clock-names = "baudclk", "apb_pclk";
1136                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1137                 reg-shift = <2>;
1138                 reg-io-width = <4>;
1139                 pinctrl-names = "default";
1140                 pinctrl-0 = <&uart4_xfer>;
1141                 status = "disabled";
1142         };
1143
1144         i2c4: i2c@ff3d0000 {
1145                 compatible = "rockchip,rk3399-i2c";
1146                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1147                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1148                 clock-names = "i2c", "pclk";
1149                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1150                 pinctrl-names = "default";
1151                 pinctrl-0 = <&i2c4_xfer>;
1152                 #address-cells = <1>;
1153                 #size-cells = <0>;
1154                 status = "disabled";
1155         };
1156
1157         i2c8: i2c@ff3e0000 {
1158                 compatible = "rockchip,rk3399-i2c";
1159                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1160                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1161                 clock-names = "i2c", "pclk";
1162                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1163                 pinctrl-names = "default";
1164                 pinctrl-0 = <&i2c8_xfer>;
1165                 #address-cells = <1>;
1166                 #size-cells = <0>;
1167                 status = "disabled";
1168         };
1169
1170         pcie_phy: phy@e220 {
1171                 compatible = "rockchip,rk3399-pcie-phy";
1172                 #phy-cells = <0>;
1173                 rockchip,grf = <&grf>;
1174                 clocks = <&cru SCLK_PCIEPHY_REF>;
1175                 clock-names = "refclk";
1176                 resets = <&cru SRST_PCIEPHY>;
1177                 reset-names = "phy";
1178                 status = "disabled";
1179         };
1180
1181         pcie0: pcie@f8000000 {
1182                 compatible = "rockchip,rk3399-pcie";
1183                 #address-cells = <3>;
1184                 #size-cells = <2>;
1185                 aspm-no-l0s;
1186                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1187                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1188                 clock-names = "aclk", "aclk-perf",
1189                               "hclk", "pm";
1190                 bus-range = <0x0 0x1>;
1191                 max-link-speed = <1>;
1192                 linux,pci-domain = <0>;
1193                 msi-map = <0x0 &its 0x0 0x1000>;
1194                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1195                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1196                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1197                 interrupt-names = "sys", "legacy", "client";
1198                 #interrupt-cells = <1>;
1199                 interrupt-map-mask = <0 0 0 7>;
1200                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1201                                 <0 0 0 2 &pcie0_intc 1>,
1202                                 <0 0 0 3 &pcie0_intc 2>,
1203                                 <0 0 0 4 &pcie0_intc 3>;
1204                 phys = <&pcie_phy>;
1205                 phy-names = "pcie-phy";
1206                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1207                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1208                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1209                       <0x0 0xfd000000 0x0 0x1000000>;
1210                 reg-names = "axi-base", "apb-base";
1211                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1212                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1213                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1214                          <&cru SRST_A_PCIE>;
1215                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1216                               "pm", "pclk", "aclk";
1217                 status = "disabled";
1218                 pcie0_intc: interrupt-controller {
1219                         interrupt-controller;
1220                         #address-cells = <0>;
1221                         #interrupt-cells = <1>;
1222                 };
1223         };
1224
1225         pwm0: pwm@ff420000 {
1226                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1227                 reg = <0x0 0xff420000 0x0 0x10>;
1228                 #pwm-cells = <3>;
1229                 pinctrl-names = "default";
1230                 pinctrl-0 = <&pwm0_pin>;
1231                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1232                 clock-names = "pwm";
1233                 status = "disabled";
1234         };
1235
1236         pwm1: pwm@ff420010 {
1237                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1238                 reg = <0x0 0xff420010 0x0 0x10>;
1239                 #pwm-cells = <3>;
1240                 pinctrl-names = "default";
1241                 pinctrl-0 = <&pwm1_pin>;
1242                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1243                 clock-names = "pwm";
1244                 status = "disabled";
1245         };
1246
1247         pwm2: pwm@ff420020 {
1248                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1249                 reg = <0x0 0xff420020 0x0 0x10>;
1250                 #pwm-cells = <3>;
1251                 pinctrl-names = "default";
1252                 pinctrl-0 = <&pwm2_pin>;
1253                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1254                 clock-names = "pwm";
1255                 status = "disabled";
1256         };
1257
1258         pwm3: pwm@ff420030 {
1259                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1260                 reg = <0x0 0xff420030 0x0 0x10>;
1261                 #pwm-cells = <3>;
1262                 pinctrl-names = "default";
1263                 pinctrl-0 = <&pwm3a_pin>;
1264                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1265                 clock-names = "pwm";
1266                 status = "disabled";
1267         };
1268
1269         dfi: dfi@ff630000 {
1270                 reg = <0x00 0xff630000 0x00 0x4000>;
1271                 compatible = "rockchip,rk3399-dfi";
1272                 rockchip,pmu = <&pmugrf>;
1273                 clocks = <&cru PCLK_DDR_MON>;
1274                 clock-names = "pclk_ddr_mon";
1275                 status = "disabled";
1276         };
1277
1278         dmc: dmc {
1279                 compatible = "rockchip,rk3399-dmc";
1280                 devfreq-events = <&dfi>;
1281                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1282                 clocks = <&cru SCLK_DDRCLK>;
1283                 clock-names = "dmc_clk";
1284                 ddr_timing = <&ddr_timing>;
1285                 status = "disabled";
1286         };
1287
1288         vpu: vpu_service@ff650000 {
1289                 compatible = "rockchip,vpu_service";
1290                 rockchip,grf = <&grf>;
1291                 iommus = <&vpu_mmu>;
1292                 iommu_enabled = <1>;
1293                 reg = <0x0 0xff650000 0x0 0x800>;
1294                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1295                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1296                 interrupt-names = "irq_dec", "irq_enc";
1297                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1298                 clock-names = "aclk_vcodec", "hclk_vcodec";
1299                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1300                 reset-names = "video_h", "video_a";
1301                 power-domains = <&power RK3399_PD_VCODEC>;
1302                 name = "vpu_service";
1303                 dev_mode = <0>;
1304                 /* 0 means ion, 1 means drm */
1305                 allocator = <1>;
1306                 status = "disabled";
1307         };
1308
1309         vpu_mmu: iommu@ff650800 {
1310                 compatible = "rockchip,iommu";
1311                 reg = <0x0 0xff650800 0x0 0x40>;
1312                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1313                 interrupt-names = "vpu_mmu";
1314                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1315                 clock-names = "aclk", "hclk";
1316                 power-domains = <&power RK3399_PD_VCODEC>;
1317                 #iommu-cells = <0>;
1318         };
1319
1320         rkvdec: rkvdec@ff660000 {
1321                 compatible = "rockchip,rkvdec";
1322                 rockchip,grf = <&grf>;
1323                 iommus = <&vdec_mmu>;
1324                 iommu_enabled = <1>;
1325                 reg = <0x0 0xff660000 0x0 0x400>;
1326                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1327                 interrupt-names = "irq_dec";
1328                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1329                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1330                 clock-names = "aclk_vcodec", "hclk_vcodec",
1331                               "clk_cabac", "clk_core";
1332                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
1333                 reset-names = "video_h", "video_a";
1334                 power-domains = <&power RK3399_PD_VDU>;
1335                 dev_mode = <2>;
1336                 name = "rkvdec";
1337                 /* 0 means ion, 1 means drm */
1338                 allocator = <1>;
1339                 status = "disabled";
1340         };
1341
1342         vdec_mmu: iommu@ff660480 {
1343                 compatible = "rockchip,iommu";
1344                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1345                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1346                 interrupt-names = "vdec_mmu";
1347                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1348                 clock-names = "aclk", "hclk";
1349                 power-domains = <&power RK3399_PD_VDU>;
1350                 #iommu-cells = <0>;
1351         };
1352
1353         iep: iep@ff670000 {
1354                 compatible = "rockchip,iep";
1355                 iommu_enabled = <1>;
1356                 iommus = <&iep_mmu>;
1357                 reg = <0x0 0xff670000 0x0 0x800>;
1358                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1359                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1360                 clock-names = "aclk_iep", "hclk_iep";
1361                 power-domains = <&power RK3399_PD_IEP>;
1362                 allocator = <1>;
1363                 version = <2>;
1364                 status = "disabled";
1365         };
1366
1367         iep_mmu: iommu@ff670800 {
1368                 compatible = "rockchip,iommu";
1369                 reg = <0x0 0xff670800 0x0 0x40>;
1370                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1371                 interrupt-names = "iep_mmu";
1372                 #iommu-cells = <0>;
1373                 status = "disabled";
1374         };
1375
1376         rga: rga@ff680000 {
1377                 compatible = "rockchip,rk3399-rga";
1378                 reg = <0x0 0xff680000 0x0 0x10000>;
1379                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1380                 interrupt-names = "rga";
1381                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1382                 clock-names = "aclk", "hclk", "sclk";
1383                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1384                 reset-names = "core", "axi", "ahb";
1385                 power-domains = <&power RK3399_PD_RGA>;
1386                 status = "disabled";
1387         };
1388
1389         efuse0: efuse@ff690000 {
1390                 compatible = "rockchip,rk3399-efuse";
1391                 reg = <0x0 0xff690000 0x0 0x80>;
1392                 #address-cells = <1>;
1393                 #size-cells = <1>;
1394                 clocks = <&cru PCLK_EFUSE1024NS>;
1395                 clock-names = "pclk_efuse";
1396
1397                 /* Data cells */
1398                 efuse_id: id {
1399                         reg = <0x07 0x10>;
1400                 };
1401                 cpul_leakage: cpul-leakage {
1402                         reg = <0x1a 0x1>;
1403                 };
1404                 cpub_leakage: cpub-leakage {
1405                         reg = <0x17 0x1>;
1406                 };
1407                 gpu_leakage: gpu-leakage {
1408                         reg = <0x18 0x1>;
1409                 };
1410                 center_leakage: center-leakage {
1411                         reg = <0x19 0x1>;
1412                 };
1413                 logic_leakage: logic-leakage {
1414                         reg = <0x1b 0x1>;
1415                 };
1416                 wafer_info: wafer-info {
1417                         reg = <0x1c 0x1>;
1418                 };
1419         };
1420
1421         pmucru: pmu-clock-controller@ff750000 {
1422                 compatible = "rockchip,rk3399-pmucru";
1423                 reg = <0x0 0xff750000 0x0 0x1000>;
1424                 #clock-cells = <1>;
1425                 #reset-cells = <1>;
1426                 assigned-clocks = <&pmucru PLL_PPLL>;
1427                 assigned-clock-rates = <676000000>;
1428         };
1429
1430         cru: clock-controller@ff760000 {
1431                 compatible = "rockchip,rk3399-cru";
1432                 reg = <0x0 0xff760000 0x0 0x1000>;
1433                 #clock-cells = <1>;
1434                 #reset-cells = <1>;
1435                 assigned-clocks =
1436                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1437                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1438                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1439                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1440                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1441                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1442                         <&cru PCLK_PERIHP>,
1443                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1444                         <&cru PCLK_PERILP0>,
1445                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1446                 assigned-clock-rates =
1447                          <400000000>,  <200000000>,
1448                          <400000000>,  <200000000>,
1449                          <816000000>, <816000000>,
1450                          <594000000>,  <800000000>,
1451                          <200000000>, <1000000000>,
1452                          <150000000>,   <75000000>,
1453                           <37500000>,
1454                          <100000000>,  <100000000>,
1455                           <50000000>,
1456                          <100000000>,   <50000000>;
1457         };
1458
1459         grf: syscon@ff770000 {
1460                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1461                 reg = <0x0 0xff770000 0x0 0x10000>;
1462                 #address-cells = <1>;
1463                 #size-cells = <1>;
1464
1465                 io_domains: io-domains {
1466                         compatible = "rockchip,rk3399-io-voltage-domain";
1467                         status = "disabled";
1468                 };
1469
1470                 emmc_phy: phy@f780 {
1471                         compatible = "rockchip,rk3399-emmc-phy";
1472                         reg = <0xf780 0x24>;
1473                         clocks = <&sdhci>;
1474                         clock-names = "emmcclk";
1475                         #phy-cells = <0>;
1476                         status = "disabled";
1477                 };
1478
1479                 u2phy0: usb2-phy@e450 {
1480                         compatible = "rockchip,rk3399-usb2phy";
1481                         reg = <0xe450 0x10>;
1482                         clocks = <&cru SCLK_USB2PHY0_REF>;
1483                         clock-names = "phyclk";
1484                         #clock-cells = <0>;
1485                         clock-output-names = "clk_usbphy0_480m";
1486                         status = "disabled";
1487
1488                         u2phy0_otg: otg-port {
1489                                 #phy-cells = <0>;
1490                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1491                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1492                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1493                                 interrupt-names = "otg-bvalid", "otg-id",
1494                                                   "linestate";
1495                                 status = "disabled";
1496                         };
1497
1498                         u2phy0_host: host-port {
1499                                 #phy-cells = <0>;
1500                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1501                                 interrupt-names = "linestate";
1502                                 status = "disabled";
1503                         };
1504                 };
1505
1506                 u2phy1: usb2-phy@e460 {
1507                         compatible = "rockchip,rk3399-usb2phy";
1508                         reg = <0xe460 0x10>;
1509                         clocks = <&cru SCLK_USB2PHY1_REF>;
1510                         clock-names = "phyclk";
1511                         #clock-cells = <0>;
1512                         clock-output-names = "clk_usbphy1_480m";
1513                         status = "disabled";
1514
1515                         u2phy1_otg: otg-port {
1516                                 #phy-cells = <0>;
1517                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1518                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1519                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1520                                 interrupt-names = "otg-bvalid", "otg-id",
1521                                                   "linestate";
1522                                 status = "disabled";
1523                         };
1524
1525                         u2phy1_host: host-port {
1526                                 #phy-cells = <0>;
1527                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1528                                 interrupt-names = "linestate";
1529                                 status = "disabled";
1530                         };
1531                 };
1532
1533                 pvtm: pvtm {
1534                         compatible = "rockchip,rk3399-pvtm";
1535                         clocks = <&cru SCLK_PVTM_CORE_L>,
1536                                  <&cru SCLK_PVTM_CORE_B>,
1537                                  <&cru SCLK_PVTM_GPU>,
1538                                  <&cru SCLK_PVTM_DDR>;
1539                         clock-names = "core_l", "core_b", "gpu", "ddr";
1540                         status = "disabled";
1541                 };
1542         };
1543
1544         tcphy0: phy@ff7c0000 {
1545                 compatible = "rockchip,rk3399-typec-phy";
1546                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1547                 rockchip,grf = <&grf>;
1548                 #phy-cells = <1>;
1549                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1550                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1551                 clock-names = "tcpdcore", "tcpdphy-ref";
1552                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1553                 assigned-clock-rates = <50000000>;
1554                 power-domains = <&power RK3399_PD_TCPD0>;
1555                 resets = <&cru SRST_UPHY0>,
1556                          <&cru SRST_UPHY0_PIPE_L00>,
1557                          <&cru SRST_P_UPHY0_TCPHY>;
1558                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1559                 rockchip,typec-conn-dir = <0xe580 0 16>;
1560                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1561                 rockchip,usb3-host-disable = <0x2434 0 16>;
1562                 rockchip,usb3-host-port = <0x2434 12 28>;
1563                 rockchip,external-psm = <0xe588 14 30>;
1564                 rockchip,pipe-status = <0xe5c0 0 0>;
1565                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1566                 status = "disabled";
1567
1568                 tcphy0_dp: dp-port {
1569                         #phy-cells = <0>;
1570                 };
1571
1572                 tcphy0_usb3: usb3-port {
1573                         #phy-cells = <0>;
1574                 };
1575         };
1576
1577         tcphy1: phy@ff800000 {
1578                 compatible = "rockchip,rk3399-typec-phy";
1579                 reg = <0x0 0xff800000 0x0 0x40000>;
1580                 rockchip,grf = <&grf>;
1581                 #phy-cells = <1>;
1582                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1583                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1584                 clock-names = "tcpdcore", "tcpdphy-ref";
1585                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1586                 assigned-clock-rates = <50000000>;
1587                 power-domains = <&power RK3399_PD_TCPD1>;
1588                 resets = <&cru SRST_UPHY1>,
1589                          <&cru SRST_UPHY1_PIPE_L00>,
1590                          <&cru SRST_P_UPHY1_TCPHY>;
1591                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1592                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1593                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1594                 rockchip,usb3-host-disable = <0x2444 0 16>;
1595                 rockchip,usb3-host-port = <0x2444 12 28>;
1596                 rockchip,external-psm = <0xe594 14 30>;
1597                 rockchip,pipe-status = <0xe5c0 16 16>;
1598                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1599                 status = "disabled";
1600
1601                 tcphy1_dp: dp-port {
1602                         #phy-cells = <0>;
1603                 };
1604
1605                 tcphy1_usb3: usb3-port {
1606                         #phy-cells = <0>;
1607                 };
1608         };
1609
1610         watchdog@ff848000 {
1611                 compatible = "snps,dw-wdt";
1612                 reg = <0x0 0xff848000 0x0 0x100>;
1613                 clocks = <&cru PCLK_WDT>;
1614                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1615         };
1616
1617         rktimer: rktimer@ff850000 {
1618                 compatible = "rockchip,rk3399-timer";
1619                 reg = <0x0 0xff850000 0x0 0x1000>;
1620                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1621                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1622                 clock-names = "pclk", "timer";
1623         };
1624
1625         spdif: spdif@ff870000 {
1626                 compatible = "rockchip,rk3399-spdif";
1627                 reg = <0x0 0xff870000 0x0 0x1000>;
1628                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1629                 dmas = <&dmac_bus 7>;
1630                 dma-names = "tx";
1631                 clock-names = "mclk", "hclk";
1632                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1633                 pinctrl-names = "default";
1634                 pinctrl-0 = <&spdif_bus>;
1635                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1636                 status = "disabled";
1637         };
1638
1639         i2s0: i2s@ff880000 {
1640                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1641                 reg = <0x0 0xff880000 0x0 0x1000>;
1642                 rockchip,grf = <&grf>;
1643                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1644                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1645                 dma-names = "tx", "rx";
1646                 clock-names = "i2s_clk", "i2s_hclk";
1647                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1648                 pinctrl-names = "default";
1649                 pinctrl-0 = <&i2s0_8ch_bus>;
1650                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1651                 status = "disabled";
1652         };
1653
1654         i2s1: i2s@ff890000 {
1655                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1656                 reg = <0x0 0xff890000 0x0 0x1000>;
1657                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1658                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1659                 dma-names = "tx", "rx";
1660                 clock-names = "i2s_clk", "i2s_hclk";
1661                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1662                 pinctrl-names = "default";
1663                 pinctrl-0 = <&i2s1_2ch_bus>;
1664                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1665                 status = "disabled";
1666         };
1667
1668         i2s2: i2s@ff8a0000 {
1669                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1670                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1671                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1672                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1673                 dma-names = "tx", "rx";
1674                 clock-names = "i2s_clk", "i2s_hclk";
1675                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1676                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1677                 status = "disabled";
1678         };
1679
1680         gpu: gpu@ff9a0000 {
1681                 compatible = "arm,malit860",
1682                              "arm,malit86x",
1683                              "arm,malit8xx",
1684                              "arm,mali-midgard";
1685
1686                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1687
1688                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1689                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1690                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1691                 interrupt-names = "GPU", "JOB", "MMU";
1692
1693                 clocks = <&cru ACLK_GPU>;
1694                 clock-names = "clk_mali";
1695                 #cooling-cells = <2>; /* min followed by max */
1696                 power-domains = <&power RK3399_PD_GPU>;
1697                 power-off-delay-ms = <200>;
1698                 status = "disabled";
1699
1700                 gpu_power_model: power_model {
1701                         compatible = "arm,mali-simple-power-model";
1702                         voltage = <900>;
1703                         frequency = <500>;
1704                         static-power = <300>;
1705                         dynamic-power = <396>;
1706                         ts = <32000 4700 (-80) 2>;
1707                         thermal-zone = "gpu-thermal";
1708                 };
1709         };
1710
1711         vopl: vop@ff8f0000 {
1712                 compatible = "rockchip,rk3399-vop-lit";
1713                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1714                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1715                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1716                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1717                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1718                 reset-names = "axi", "ahb", "dclk";
1719                 power-domains = <&power RK3399_PD_VOPL>;
1720                 iommus = <&vopl_mmu>;
1721                 status = "disabled";
1722
1723                 vopl_out: port {
1724                         #address-cells = <1>;
1725                         #size-cells = <0>;
1726
1727                         vopl_out_mipi: endpoint@0 {
1728                                 reg = <0>;
1729                                 remote-endpoint = <&mipi_in_vopl>;
1730                         };
1731
1732                         vopl_out_edp: endpoint@1 {
1733                                 reg = <1>;
1734                                 remote-endpoint = <&edp_in_vopl>;
1735                         };
1736
1737                         vopl_out_hdmi: endpoint@2 {
1738                                 reg = <2>;
1739                                 remote-endpoint = <&hdmi_in_vopl>;
1740                         };
1741
1742                         vopl_out_dp: endpoint@3 {
1743                                 reg = <3>;
1744                                 remote-endpoint = <&dp_in_vopl>;
1745                         };
1746                 };
1747         };
1748
1749         vop1_pwm: voppwm@ff8f01a0 {
1750                 compatible = "rockchip,vop-pwm";
1751                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1752                 #pwm-cells = <3>;
1753                 pinctrl-names = "default";
1754                 pinctrl-0 = <&vop1_pwm_pin>;
1755                 clocks = <&cru SCLK_VOP1_PWM>;
1756                 clock-names = "pwm";
1757                 status = "disabled";
1758         };
1759
1760         vopl_mmu: iommu@ff8f3f00 {
1761                 compatible = "rockchip,iommu";
1762                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1763                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1764                 interrupt-names = "vopl_mmu";
1765                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1766                 clock-names = "aclk", "hclk";
1767                 power-domains = <&power RK3399_PD_VOPL>;
1768                 #iommu-cells = <0>;
1769                 status = "disabled";
1770         };
1771
1772         vopb: vop@ff900000 {
1773                 compatible = "rockchip,rk3399-vop-big";
1774                 reg = <0x0 0xff900000 0x0 0x3efc>;
1775                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1776                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1777                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1778                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1779                 reset-names = "axi", "ahb", "dclk";
1780                 power-domains = <&power RK3399_PD_VOPB>;
1781                 iommus = <&vopb_mmu>;
1782                 status = "disabled";
1783
1784                 vopb_out: port {
1785                         #address-cells = <1>;
1786                         #size-cells = <0>;
1787
1788                         vopb_out_edp: endpoint@0 {
1789                                 reg = <0>;
1790                                 remote-endpoint = <&edp_in_vopb>;
1791                         };
1792
1793                         vopb_out_mipi: endpoint@1 {
1794                                 reg = <1>;
1795                                 remote-endpoint = <&mipi_in_vopb>;
1796                         };
1797
1798                         vopb_out_hdmi: endpoint@2 {
1799                                 reg = <2>;
1800                                 remote-endpoint = <&hdmi_in_vopb>;
1801                         };
1802
1803                         vopb_out_dp: endpoint@3 {
1804                                 reg = <3>;
1805                                 remote-endpoint = <&dp_in_vopb>;
1806                         };
1807                 };
1808         };
1809
1810         vop0_pwm: voppwm@ff9001a0 {
1811                 compatible = "rockchip,vop-pwm";
1812                 reg = <0x0 0xff9001a0 0x0 0x10>;
1813                 #pwm-cells = <3>;
1814                 pinctrl-names = "default";
1815                 pinctrl-0 = <&vop0_pwm_pin>;
1816                 clocks = <&cru SCLK_VOP0_PWM>;
1817                 clock-names = "pwm";
1818                 status = "disabled";
1819         };
1820
1821         vopb_mmu: iommu@ff903f00 {
1822                 compatible = "rockchip,iommu";
1823                 reg = <0x0 0xff903f00 0x0 0x100>;
1824                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1825                 interrupt-names = "vopb_mmu";
1826                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1827                 clock-names = "aclk", "hclk";
1828                 power-domains = <&power RK3399_PD_VOPB>;
1829                 #iommu-cells = <0>;
1830                 status = "disabled";
1831         };
1832
1833         isp0_mmu: iommu@ff914000 {
1834                 compatible = "rockchip,iommu";
1835                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1836                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1837                 interrupt-names = "isp0_mmu";
1838                 #iommu-cells = <0>;
1839                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1840                 clock-names = "aclk", "hclk";
1841                 power-domains = <&power RK3399_PD_ISP0>;
1842                 rk_iommu,disable_reset_quirk;
1843                 status = "disabled";
1844         };
1845
1846         isp1_mmu: iommu@ff924000 {
1847                 compatible = "rockchip,iommu";
1848                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1849                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1850                 interrupt-names = "isp1_mmu";
1851                 #iommu-cells = <0>;
1852                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1853                 clock-names = "aclk", "hclk";
1854                 power-domains = <&power RK3399_PD_ISP1>;
1855                 rk_iommu,disable_reset_quirk;
1856                 status = "disabled";
1857         };
1858
1859         hdmi: hdmi@ff940000 {
1860                 compatible = "rockchip,rk3399-dw-hdmi";
1861                 reg = <0x0 0xff940000 0x0 0x20000>;
1862                 reg-io-width = <4>;
1863                 rockchip,grf = <&grf>;
1864                 pinctrl-names = "default";
1865                 pinctrl-0 = <&hdmi_i2c_xfer>;
1866                 power-domains = <&power RK3399_PD_HDCP>;
1867                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1868                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1869                 clock-names = "iahb", "isfr", "vpll", "grf";
1870                 status = "disabled";
1871
1872                 ports {
1873                         hdmi_in: port {
1874                                 #address-cells = <1>;
1875                                 #size-cells = <0>;
1876                                 hdmi_in_vopb: endpoint@0 {
1877                                         reg = <0>;
1878                                         remote-endpoint = <&vopb_out_hdmi>;
1879                                 };
1880                                 hdmi_in_vopl: endpoint@1 {
1881                                         reg = <1>;
1882                                         remote-endpoint = <&vopl_out_hdmi>;
1883                                 };
1884                         };
1885                 };
1886         };
1887
1888         mipi_dsi: mipi@ff960000 {
1889                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1890                 reg = <0x0 0xff960000 0x0 0x8000>;
1891                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1892                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1893                          <&cru SCLK_DPHY_TX0_CFG>;
1894                 clock-names = "ref", "pclk", "phy_cfg";
1895                 power-domains = <&power RK3399_PD_VIO>;
1896                 rockchip,grf = <&grf>;
1897                 #address-cells = <1>;
1898                 #size-cells = <0>;
1899                 status = "disabled";
1900
1901                 ports {
1902                         #address-cells = <1>;
1903                         #size-cells = <0>;
1904                         reg = <1>;
1905
1906                         mipi_in: port {
1907                                 #address-cells = <1>;
1908                                 #size-cells = <0>;
1909
1910                                 mipi_in_vopb: endpoint@0 {
1911                                         reg = <0>;
1912                                         remote-endpoint = <&vopb_out_mipi>;
1913                                 };
1914                                 mipi_in_vopl: endpoint@1 {
1915                                         reg = <1>;
1916                                         remote-endpoint = <&vopl_out_mipi>;
1917                                 };
1918                         };
1919                 };
1920         };
1921
1922         edp: edp@ff970000 {
1923                 compatible = "rockchip,rk3399-edp";
1924                 reg = <0x0 0xff970000 0x0 0x8000>;
1925                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1926                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1927                 clock-names = "dp", "pclk";
1928                 power-domains = <&power RK3399_PD_EDP>;
1929                 resets = <&cru SRST_P_EDP_CTRL>;
1930                 reset-names = "dp";
1931                 rockchip,grf = <&grf>;
1932                 status = "disabled";
1933                 pinctrl-names = "default";
1934                 pinctrl-0 = <&edp_hpd>;
1935
1936                 ports {
1937                         #address-cells = <1>;
1938                         #size-cells = <0>;
1939
1940                         edp_in: port@0 {
1941                                 reg = <0>;
1942                                 #address-cells = <1>;
1943                                 #size-cells = <0>;
1944
1945                                 edp_in_vopb: endpoint@0 {
1946                                         reg = <0>;
1947                                         remote-endpoint = <&vopb_out_edp>;
1948                                 };
1949
1950                                 edp_in_vopl: endpoint@1 {
1951                                         reg = <1>;
1952                                         remote-endpoint = <&vopl_out_edp>;
1953                                 };
1954                         };
1955                 };
1956         };
1957
1958         display_subsystem: display-subsystem {
1959                 compatible = "rockchip,display-subsystem";
1960                 ports = <&vopl_out>, <&vopb_out>;
1961                 status = "disabled";
1962         };
1963
1964         pinctrl: pinctrl {
1965                 compatible = "rockchip,rk3399-pinctrl";
1966                 rockchip,grf = <&grf>;
1967                 rockchip,pmu = <&pmugrf>;
1968                 #address-cells = <0x2>;
1969                 #size-cells = <0x2>;
1970                 ranges;
1971
1972                 gpio0: gpio0@ff720000 {
1973                         compatible = "rockchip,gpio-bank";
1974                         reg = <0x0 0xff720000 0x0 0x100>;
1975                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1976                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1977
1978                         gpio-controller;
1979                         #gpio-cells = <0x2>;
1980
1981                         interrupt-controller;
1982                         #interrupt-cells = <0x2>;
1983                 };
1984
1985                 gpio1: gpio1@ff730000 {
1986                         compatible = "rockchip,gpio-bank";
1987                         reg = <0x0 0xff730000 0x0 0x100>;
1988                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1989                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1990
1991                         gpio-controller;
1992                         #gpio-cells = <0x2>;
1993
1994                         interrupt-controller;
1995                         #interrupt-cells = <0x2>;
1996                 };
1997
1998                 gpio2: gpio2@ff780000 {
1999                         compatible = "rockchip,gpio-bank";
2000                         reg = <0x0 0xff780000 0x0 0x100>;
2001                         clocks = <&cru PCLK_GPIO2>;
2002                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2003
2004                         gpio-controller;
2005                         #gpio-cells = <0x2>;
2006
2007                         interrupt-controller;
2008                         #interrupt-cells = <0x2>;
2009                 };
2010
2011                 gpio3: gpio3@ff788000 {
2012                         compatible = "rockchip,gpio-bank";
2013                         reg = <0x0 0xff788000 0x0 0x100>;
2014                         clocks = <&cru PCLK_GPIO3>;
2015                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2016
2017                         gpio-controller;
2018                         #gpio-cells = <0x2>;
2019
2020                         interrupt-controller;
2021                         #interrupt-cells = <0x2>;
2022                 };
2023
2024                 gpio4: gpio4@ff790000 {
2025                         compatible = "rockchip,gpio-bank";
2026                         reg = <0x0 0xff790000 0x0 0x100>;
2027                         clocks = <&cru PCLK_GPIO4>;
2028                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2029
2030                         gpio-controller;
2031                         #gpio-cells = <0x2>;
2032
2033                         interrupt-controller;
2034                         #interrupt-cells = <0x2>;
2035                 };
2036
2037                 pcfg_pull_up: pcfg-pull-up {
2038                         bias-pull-up;
2039                 };
2040
2041                 pcfg_pull_down: pcfg-pull-down {
2042                         bias-pull-down;
2043                 };
2044
2045                 pcfg_pull_none: pcfg-pull-none {
2046                         bias-disable;
2047                 };
2048
2049                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2050                         bias-pull-up;
2051                         drive-strength = <20>;
2052                 };
2053
2054                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2055                         bias-disable;
2056                         drive-strength = <20>;
2057                 };
2058
2059                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2060                         bias-disable;
2061                         drive-strength = <18>;
2062                 };
2063
2064                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2065                         bias-disable;
2066                         drive-strength = <12>;
2067                 };
2068
2069                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2070                         bias-pull-up;
2071                         drive-strength = <8>;
2072                 };
2073
2074                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2075                         bias-pull-down;
2076                         drive-strength = <4>;
2077                 };
2078
2079                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2080                         bias-pull-up;
2081                         drive-strength = <2>;
2082                 };
2083
2084                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2085                         bias-pull-down;
2086                         drive-strength = <12>;
2087                 };
2088
2089                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2090                         bias-disable;
2091                         drive-strength = <13>;
2092                 };
2093
2094                 pcfg_output_high: pcfg-output-high {
2095                         output-high;
2096                 };
2097
2098                 pcfg_output_low: pcfg-output-low {
2099                         output-low;
2100                 };
2101
2102                 pcfg_input: pcfg-input {
2103                         input-enable;
2104                 };
2105
2106                 emmc {
2107                         emmc_pwr: emmc-pwr {
2108                                 rockchip,pins =
2109                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
2110                         };
2111                 };
2112
2113                 gmac {
2114                         rgmii_pins: rgmii-pins {
2115                                 rockchip,pins =
2116                                         /* mac_txclk */
2117                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2118                                         /* mac_rxclk */
2119                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2120                                         /* mac_mdio */
2121                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2122                                         /* mac_txen */
2123                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2124                                         /* mac_clk */
2125                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2126                                         /* mac_rxdv */
2127                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2128                                         /* mac_mdc */
2129                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2130                                         /* mac_rxd1 */
2131                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2132                                         /* mac_rxd0 */
2133                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2134                                         /* mac_txd1 */
2135                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2136                                         /* mac_txd0 */
2137                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2138                                         /* mac_rxd3 */
2139                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2140                                         /* mac_rxd2 */
2141                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2142                                         /* mac_txd3 */
2143                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2144                                         /* mac_txd2 */
2145                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2146                         };
2147
2148                         rmii_pins: rmii-pins {
2149                                 rockchip,pins =
2150                                         /* mac_mdio */
2151                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2152                                         /* mac_txen */
2153                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2154                                         /* mac_clk */
2155                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2156                                         /* mac_rxer */
2157                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2158                                         /* mac_rxdv */
2159                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2160                                         /* mac_mdc */
2161                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2162                                         /* mac_rxd1 */
2163                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2164                                         /* mac_rxd0 */
2165                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2166                                         /* mac_txd1 */
2167                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2168                                         /* mac_txd0 */
2169                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2170                         };
2171                 };
2172
2173                 i2c0 {
2174                         i2c0_xfer: i2c0-xfer {
2175                                 rockchip,pins =
2176                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2177                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2178                         };
2179                 };
2180
2181                 i2c1 {
2182                         i2c1_xfer: i2c1-xfer {
2183                                 rockchip,pins =
2184                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2185                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2186                         };
2187                 };
2188
2189                 i2c2 {
2190                         i2c2_xfer: i2c2-xfer {
2191                                 rockchip,pins =
2192                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2193                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2194                         };
2195                 };
2196
2197                 i2c3 {
2198                         i2c3_xfer: i2c3-xfer {
2199                                 rockchip,pins =
2200                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2201                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2202                         };
2203
2204                         i2c3_gpio: i2c3_gpio {
2205                                 rockchip,pins =
2206                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2207                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2208                         };
2209
2210                 };
2211
2212                 i2c4 {
2213                         i2c4_xfer: i2c4-xfer {
2214                                 rockchip,pins =
2215                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2216                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2217                         };
2218                 };
2219
2220                 i2c5 {
2221                         i2c5_xfer: i2c5-xfer {
2222                                 rockchip,pins =
2223                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2224                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2225                         };
2226                 };
2227
2228                 i2c6 {
2229                         i2c6_xfer: i2c6-xfer {
2230                                 rockchip,pins =
2231                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2232                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2233                         };
2234                 };
2235
2236                 i2c7 {
2237                         i2c7_xfer: i2c7-xfer {
2238                                 rockchip,pins =
2239                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2240                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2241                         };
2242                 };
2243
2244                 i2c8 {
2245                         i2c8_xfer: i2c8-xfer {
2246                                 rockchip,pins =
2247                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2248                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2249                         };
2250                 };
2251
2252                 i2s0 {
2253                         i2s0_8ch_bus: i2s0-8ch-bus {
2254                                 rockchip,pins =
2255                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2256                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2257                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2258                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2259                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2260                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2261                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2262                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2263                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2264                         };
2265                 };
2266
2267                 i2s1 {
2268                         i2s1_2ch_bus: i2s1-2ch-bus {
2269                                 rockchip,pins =
2270                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2271                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2272                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2273                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2274                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2275                         };
2276                 };
2277
2278                 sdio0 {
2279                         sdio0_bus1: sdio0-bus1 {
2280                                 rockchip,pins =
2281                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2282                         };
2283
2284                         sdio0_bus4: sdio0-bus4 {
2285                                 rockchip,pins =
2286                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2287                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2288                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2289                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2290                         };
2291
2292                         sdio0_cmd: sdio0-cmd {
2293                                 rockchip,pins =
2294                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2295                         };
2296
2297                         sdio0_clk: sdio0-clk {
2298                                 rockchip,pins =
2299                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2300                         };
2301
2302                         sdio0_cd: sdio0-cd {
2303                                 rockchip,pins =
2304                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2305                         };
2306
2307                         sdio0_pwr: sdio0-pwr {
2308                                 rockchip,pins =
2309                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2310                         };
2311
2312                         sdio0_bkpwr: sdio0-bkpwr {
2313                                 rockchip,pins =
2314                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2315                         };
2316
2317                         sdio0_wp: sdio0-wp {
2318                                 rockchip,pins =
2319                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2320                         };
2321
2322                         sdio0_int: sdio0-int {
2323                                 rockchip,pins =
2324                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2325                         };
2326                 };
2327
2328                 sdmmc {
2329                         sdmmc_bus1: sdmmc-bus1 {
2330                                 rockchip,pins =
2331                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2332                         };
2333
2334                         sdmmc_bus4: sdmmc-bus4 {
2335                                 rockchip,pins =
2336                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2337                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2338                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2339                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2340                         };
2341
2342                         sdmmc_clk: sdmmc-clk {
2343                                 rockchip,pins =
2344                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2345                         };
2346
2347                         sdmmc_cmd: sdmmc-cmd {
2348                                 rockchip,pins =
2349                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2350                         };
2351
2352                         sdmmc_cd: sdmcc-cd {
2353                                 rockchip,pins =
2354                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2355                         };
2356
2357                         sdmmc_wp: sdmmc-wp {
2358                                 rockchip,pins =
2359                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2360                         };
2361                 };
2362
2363                 spdif {
2364                         spdif_bus: spdif-bus {
2365                                 rockchip,pins =
2366                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2367                         };
2368
2369                         spdif_bus_1: spdif-bus-1 {
2370                                 rockchip,pins =
2371                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2372                         };
2373                 };
2374
2375                 spi0 {
2376                         spi0_clk: spi0-clk {
2377                                 rockchip,pins =
2378                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2379                         };
2380                         spi0_cs0: spi0-cs0 {
2381                                 rockchip,pins =
2382                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2383                         };
2384                         spi0_cs1: spi0-cs1 {
2385                                 rockchip,pins =
2386                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2387                         };
2388                         spi0_tx: spi0-tx {
2389                                 rockchip,pins =
2390                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2391                         };
2392                         spi0_rx: spi0-rx {
2393                                 rockchip,pins =
2394                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2395                         };
2396                 };
2397
2398                 spi1 {
2399                         spi1_clk: spi1-clk {
2400                                 rockchip,pins =
2401                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2402                         };
2403                         spi1_cs0: spi1-cs0 {
2404                                 rockchip,pins =
2405                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2406                         };
2407                         spi1_rx: spi1-rx {
2408                                 rockchip,pins =
2409                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2410                         };
2411                         spi1_tx: spi1-tx {
2412                                 rockchip,pins =
2413                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2414                         };
2415                 };
2416
2417                 spi2 {
2418                         spi2_clk: spi2-clk {
2419                                 rockchip,pins =
2420                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2421                         };
2422                         spi2_cs0: spi2-cs0 {
2423                                 rockchip,pins =
2424                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2425                         };
2426                         spi2_rx: spi2-rx {
2427                                 rockchip,pins =
2428                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2429                         };
2430                         spi2_tx: spi2-tx {
2431                                 rockchip,pins =
2432                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2433                         };
2434                 };
2435
2436                 spi3 {
2437                         spi3_clk: spi3-clk {
2438                                 rockchip,pins =
2439                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2440                         };
2441                         spi3_cs0: spi3-cs0 {
2442                                 rockchip,pins =
2443                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2444                         };
2445                         spi3_rx: spi3-rx {
2446                                 rockchip,pins =
2447                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2448                         };
2449                         spi3_tx: spi3-tx {
2450                                 rockchip,pins =
2451                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2452                         };
2453                 };
2454
2455                 spi4 {
2456                         spi4_clk: spi4-clk {
2457                                 rockchip,pins =
2458                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2459                         };
2460                         spi4_cs0: spi4-cs0 {
2461                                 rockchip,pins =
2462                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2463                         };
2464                         spi4_rx: spi4-rx {
2465                                 rockchip,pins =
2466                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2467                         };
2468                         spi4_tx: spi4-tx {
2469                                 rockchip,pins =
2470                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2471                         };
2472                 };
2473
2474                 spi5 {
2475                         spi5_clk: spi5-clk {
2476                                 rockchip,pins =
2477                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2478                         };
2479                         spi5_cs0: spi5-cs0 {
2480                                 rockchip,pins =
2481                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2482                         };
2483                         spi5_rx: spi5-rx {
2484                                 rockchip,pins =
2485                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2486                         };
2487                         spi5_tx: spi5-tx {
2488                                 rockchip,pins =
2489                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2490                         };
2491                 };
2492
2493                 tsadc {
2494                         otp_gpio: otp-gpio {
2495                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2496                         };
2497
2498                         otp_out: otp-out {
2499                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2500                         };
2501                 };
2502
2503                 uart0 {
2504                         uart0_xfer: uart0-xfer {
2505                                 rockchip,pins =
2506                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2507                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2508                         };
2509
2510                         uart0_cts: uart0-cts {
2511                                 rockchip,pins =
2512                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2513                         };
2514
2515                         uart0_rts: uart0-rts {
2516                                 rockchip,pins =
2517                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2518                         };
2519                 };
2520
2521                 uart1 {
2522                         uart1_xfer: uart1-xfer {
2523                                 rockchip,pins =
2524                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2525                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2526                         };
2527                 };
2528
2529                 uart2a {
2530                         uart2a_xfer: uart2a-xfer {
2531                                 rockchip,pins =
2532                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2533                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2534                         };
2535                 };
2536
2537                 uart2b {
2538                         uart2b_xfer: uart2b-xfer {
2539                                 rockchip,pins =
2540                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2541                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2542                         };
2543                 };
2544
2545                 uart2c {
2546                         uart2c_xfer: uart2c-xfer {
2547                                 rockchip,pins =
2548                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2549                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2550                         };
2551                 };
2552
2553                 uart3 {
2554                         uart3_xfer: uart3-xfer {
2555                                 rockchip,pins =
2556                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2557                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2558                         };
2559
2560                         uart3_cts: uart3-cts {
2561                                 rockchip,pins =
2562                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2563                         };
2564
2565                         uart3_rts: uart3-rts {
2566                                 rockchip,pins =
2567                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2568                         };
2569                 };
2570
2571                 uart4 {
2572                         uart4_xfer: uart4-xfer {
2573                                 rockchip,pins =
2574                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2575                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2576                         };
2577                 };
2578
2579                 uarthdcp {
2580                         uarthdcp_xfer: uarthdcp-xfer {
2581                                 rockchip,pins =
2582                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2583                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2584                         };
2585                 };
2586
2587                 pwm0 {
2588                         pwm0_pin: pwm0-pin {
2589                                 rockchip,pins =
2590                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2591                         };
2592
2593                         vop0_pwm_pin: vop0-pwm-pin {
2594                                 rockchip,pins =
2595                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2596                         };
2597                 };
2598
2599                 pwm1 {
2600                         pwm1_pin: pwm1-pin {
2601                                 rockchip,pins =
2602                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2603                         };
2604
2605                         vop1_pwm_pin: vop1-pwm-pin {
2606                                 rockchip,pins =
2607                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2608                         };
2609                 };
2610
2611                 pwm2 {
2612                         pwm2_pin: pwm2-pin {
2613                                 rockchip,pins =
2614                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2615                         };
2616                 };
2617
2618                 pwm3a {
2619                         pwm3a_pin: pwm3a-pin {
2620                                 rockchip,pins =
2621                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2622                         };
2623                 };
2624
2625                 pwm3b {
2626                         pwm3b_pin: pwm3b-pin {
2627                                 rockchip,pins =
2628                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2629                         };
2630                 };
2631
2632                 edp {
2633                         edp_hpd: edp-hpd {
2634                                 rockchip,pins =
2635                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2636                         };
2637                 };
2638
2639                 hdmi {
2640                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2641                                 rockchip,pins =
2642                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2643                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2644                         };
2645
2646                         hdmi_cec: hdmi-cec {
2647                                 rockchip,pins =
2648                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2649                         };
2650                 };
2651
2652                 pcie {
2653                         pcie_clkreqn: pci-clkreqn {
2654                                 rockchip,pins =
2655                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2656                         };
2657
2658                         pcie_clkreqnb: pci-clkreqnb {
2659                                 rockchip,pins =
2660                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2661                         };
2662
2663                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2664                                 /*
2665                                  * Since our pcie doesn't support
2666                                  * ClockPM(CPM), we want to hack this as
2667                                  * gpio, so the EP could be able to
2668                                  * de-assert it along and make ClockPM(CPM)
2669                                  * work.
2670                                  */
2671                                 rockchip,pins =
2672                                         <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2673                         };
2674
2675                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2676                                 rockchip,pins =
2677                                         <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2678                         };
2679                 };
2680         };
2681
2682         rockchip_suspend: rockchip-suspend {
2683                 compatible = "rockchip,pm-rk3399";
2684                 status = "disabled";
2685                 rockchip,sleep-debug-en = <0>;
2686                 rockchip,virtual-poweroff = <0>;
2687                 rockchip,sleep-mode-config = <
2688                         (0
2689                         | RKPM_SLP_ARMPD
2690                         | RKPM_SLP_PERILPPD
2691                         | RKPM_SLP_DDR_RET
2692                         | RKPM_SLP_PLLPD
2693                         | RKPM_SLP_OSC_DIS
2694                         | RKPM_SLP_CENTER_PD
2695                         | RKPM_SLP_AP_PWROFF
2696                         )
2697                 >;
2698                 rockchip,wakeup-config = <
2699                         (0
2700                         | RKPM_GPIO_WKUP_EN
2701                         )
2702                 >;
2703         };
2704 };