2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/suspend/rockchip-rk3399.h>
51 #include <dt-bindings/thermal/thermal.h>
53 #include "rk3399-dram-default-timing.dtsi"
56 compatible = "rockchip,rk3399";
58 interrupt-parent = <&gic>;
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 dynamic-power-coefficient = <100>;
116 clocks = <&cru ARMCLKL>;
117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
122 compatible = "arm,cortex-a53", "arm,armv8";
124 enable-method = "psci";
125 clocks = <&cru ARMCLKL>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 compatible = "arm,cortex-a53", "arm,armv8";
133 enable-method = "psci";
134 clocks = <&cru ARMCLKL>;
135 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
140 compatible = "arm,cortex-a53", "arm,armv8";
142 enable-method = "psci";
143 clocks = <&cru ARMCLKL>;
144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
149 compatible = "arm,cortex-a72", "arm,armv8";
151 enable-method = "psci";
152 #cooling-cells = <2>; /* min followed by max */
153 dynamic-power-coefficient = <436>;
154 clocks = <&cru ARMCLKB>;
155 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
160 compatible = "arm,cortex-a72", "arm,armv8";
162 enable-method = "psci";
163 clocks = <&cru ARMCLKB>;
164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
168 entry-method = "psci";
170 CPU_SLEEP: cpu-sleep {
171 compatible = "arm,idle-state";
173 arm,psci-suspend-param = <0x0010000>;
174 entry-latency-us = <120>;
175 exit-latency-us = <250>;
176 min-residency-us = <900>;
179 CLUSTER_SLEEP: cluster-sleep {
180 compatible = "arm,idle-state";
182 arm,psci-suspend-param = <0x1010000>;
183 entry-latency-us = <400>;
184 exit-latency-us = <500>;
185 min-residency-us = <2000>;
191 compatible = "arm,cortex-a53-pmu";
192 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
196 compatible = "arm,cortex-a72-pmu";
197 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
201 compatible = "arm,psci-1.0";
206 compatible = "arm,armv8-timer";
207 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
208 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
209 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
210 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
214 compatible = "fixed-clock";
215 clock-frequency = <24000000>;
216 clock-output-names = "xin24m";
220 dummy_cpll: dummy_cpll {
221 compatible = "fixed-clock";
222 clock-frequency = <0>;
223 clock-output-names = "dummy_cpll";
227 dummy_vpll: dummy_vpll {
228 compatible = "fixed-clock";
229 clock-frequency = <0>;
230 clock-output-names = "dummy_vpll";
235 compatible = "arm,amba-bus";
236 #address-cells = <2>;
240 dmac_bus: dma-controller@ff6d0000 {
241 compatible = "arm,pl330", "arm,primecell";
242 reg = <0x0 0xff6d0000 0x0 0x4000>;
243 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
244 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
246 clocks = <&cru ACLK_DMAC0_PERILP>;
247 clock-names = "apb_pclk";
248 peripherals-req-type-burst;
251 dmac_peri: dma-controller@ff6e0000 {
252 compatible = "arm,pl330", "arm,primecell";
253 reg = <0x0 0xff6e0000 0x0 0x4000>;
254 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
255 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
257 clocks = <&cru ACLK_DMAC1_PERILP>;
258 clock-names = "apb_pclk";
259 peripherals-req-type-burst;
263 gmac: ethernet@fe300000 {
264 compatible = "rockchip,rk3399-gmac";
265 reg = <0x0 0xfe300000 0x0 0x10000>;
266 rockchip,grf = <&grf>;
267 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
268 interrupt-names = "macirq";
269 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
270 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
271 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
273 clock-names = "stmmaceth", "mac_clk_rx",
274 "mac_clk_tx", "clk_mac_ref",
275 "clk_mac_refout", "aclk_mac",
277 resets = <&cru SRST_A_GMAC>;
278 reset-names = "stmmaceth";
279 power-domains = <&power RK3399_PD_GMAC>;
283 sdio0: dwmmc@fe310000 {
284 compatible = "rockchip,rk3399-dw-mshc",
285 "rockchip,rk3288-dw-mshc";
286 reg = <0x0 0xfe310000 0x0 0x4000>;
287 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
288 clock-freq-min-max = <400000 150000000>;
289 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
290 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
291 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
292 fifo-depth = <0x100>;
293 power-domains = <&power RK3399_PD_SDIOAUDIO>;
297 sdmmc: dwmmc@fe320000 {
298 compatible = "rockchip,rk3399-dw-mshc",
299 "rockchip,rk3288-dw-mshc";
300 reg = <0x0 0xfe320000 0x0 0x4000>;
301 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
302 clock-freq-min-max = <400000 150000000>;
303 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
304 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
305 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
306 fifo-depth = <0x100>;
307 power-domains = <&power RK3399_PD_SD>;
311 sdhci: sdhci@fe330000 {
312 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
313 reg = <0x0 0xfe330000 0x0 0x10000>;
314 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
315 arasan,soc-ctl-syscon = <&grf>;
316 assigned-clocks = <&cru SCLK_EMMC>;
317 assigned-clock-rates = <200000000>;
318 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
319 clock-names = "clk_xin", "clk_ahb";
320 clock-output-names = "emmc_cardclock";
323 phy-names = "phy_arasan";
324 power-domains = <&power RK3399_PD_EMMC>;
328 usb_host0_ehci: usb@fe380000 {
329 compatible = "generic-ehci";
330 reg = <0x0 0xfe380000 0x0 0x20000>;
331 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
332 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
333 <&cru SCLK_USBPHY0_480M_SRC>;
334 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
335 phys = <&u2phy0_host>;
337 power-domains = <&power RK3399_PD_PERIHP>;
341 usb_host0_ohci: usb@fe3a0000 {
342 compatible = "generic-ohci";
343 reg = <0x0 0xfe3a0000 0x0 0x20000>;
344 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
345 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
346 <&cru SCLK_USBPHY0_480M_SRC>;
347 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
348 phys = <&u2phy0_host>;
350 power-domains = <&power RK3399_PD_PERIHP>;
354 usb_host1_ehci: usb@fe3c0000 {
355 compatible = "generic-ehci";
356 reg = <0x0 0xfe3c0000 0x0 0x20000>;
357 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
358 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
359 <&cru SCLK_USBPHY1_480M_SRC>;
360 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
361 phys = <&u2phy1_host>;
363 power-domains = <&power RK3399_PD_PERIHP>;
367 usb_host1_ohci: usb@fe3e0000 {
368 compatible = "generic-ohci";
369 reg = <0x0 0xfe3e0000 0x0 0x20000>;
370 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
371 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
372 <&cru SCLK_USBPHY1_480M_SRC>;
373 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
374 phys = <&u2phy1_host>;
376 power-domains = <&power RK3399_PD_PERIHP>;
380 usbdrd3_0: usb@fe800000 {
381 compatible = "rockchip,rk3399-dwc3";
382 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
383 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
384 clock-names = "ref_clk", "suspend_clk",
385 "bus_clk", "grf_clk";
386 power-domains = <&power RK3399_PD_USB3>;
387 resets = <&cru SRST_A_USB3_OTG0>;
388 reset-names = "usb3-otg";
389 #address-cells = <2>;
393 usbdrd_dwc3_0: dwc3@fe800000 {
394 compatible = "snps,dwc3";
395 reg = <0x0 0xfe800000 0x0 0x100000>;
396 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
398 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
399 phy-names = "usb2-phy", "usb3-phy";
400 phy_type = "utmi_wide";
401 snps,dis_enblslpm_quirk;
402 snps,dis-u2-freeclk-exists-quirk;
403 snps,dis_u2_susphy_quirk;
404 snps,dis-del-phy-power-chg-quirk;
405 snps,tx-ipgap-linecheck-dis-quirk;
406 snps,xhci-slow-suspend-quirk;
407 snps,usb3-warm-reset-on-resume-quirk;
412 usbdrd3_1: usb@fe900000 {
413 compatible = "rockchip,rk3399-dwc3";
414 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
415 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
416 clock-names = "ref_clk", "suspend_clk",
417 "bus_clk", "grf_clk";
418 power-domains = <&power RK3399_PD_USB3>;
419 resets = <&cru SRST_A_USB3_OTG1>;
420 reset-names = "usb3-otg";
421 #address-cells = <2>;
425 usbdrd_dwc3_1: dwc3@fe900000 {
426 compatible = "snps,dwc3";
427 reg = <0x0 0xfe900000 0x0 0x100000>;
428 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
430 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
431 phy-names = "usb2-phy", "usb3-phy";
432 phy_type = "utmi_wide";
433 snps,dis_enblslpm_quirk;
434 snps,dis-u2-freeclk-exists-quirk;
435 snps,dis_u2_susphy_quirk;
436 snps,dis-del-phy-power-chg-quirk;
437 snps,tx-ipgap-linecheck-dis-quirk;
438 snps,xhci-slow-suspend-quirk;
439 snps,usb3-warm-reset-on-resume-quirk;
444 cdn_dp: dp@fec00000 {
445 compatible = "rockchip,rk3399-cdn-dp";
446 reg = <0x0 0xfec00000 0x0 0x100000>;
447 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
449 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
450 clock-names = "core-clk", "pclk", "spdif", "grf";
451 assigned-clocks = <&cru SCLK_DP_CORE>;
452 assigned-clock-rates = <100000000>;
453 power-domains = <&power RK3399_PD_HDCP>;
454 phys = <&tcphy0_dp>, <&tcphy1_dp>;
455 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
456 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
457 reset-names = "spdif", "dptx", "apb", "core";
458 rockchip,grf = <&grf>;
459 #address-cells = <1>;
461 #sound-dai-cells = <1>;
465 #address-cells = <1>;
469 #address-cells = <1>;
471 dp_in_vopb: endpoint@0 {
473 remote-endpoint = <&vopb_out_dp>;
476 dp_in_vopl: endpoint@1 {
478 remote-endpoint = <&vopl_out_dp>;
484 gic: interrupt-controller@fee00000 {
485 compatible = "arm,gic-v3";
486 #interrupt-cells = <4>;
487 #address-cells = <2>;
490 interrupt-controller;
492 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
493 <0x0 0xfef00000 0 0xc0000>, /* GICR */
494 <0x0 0xfff00000 0 0x10000>, /* GICC */
495 <0x0 0xfff10000 0 0x10000>, /* GICH */
496 <0x0 0xfff20000 0 0x10000>; /* GICV */
497 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
498 its: interrupt-controller@fee20000 {
499 compatible = "arm,gic-v3-its";
501 reg = <0x0 0xfee20000 0x0 0x20000>;
505 ppi_cluster0: interrupt-partition-0 {
506 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
509 ppi_cluster1: interrupt-partition-1 {
510 affinity = <&cpu_b0 &cpu_b1>;
515 saradc: saradc@ff100000 {
516 compatible = "rockchip,rk3399-saradc";
517 reg = <0x0 0xff100000 0x0 0x100>;
518 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
519 #io-channel-cells = <1>;
520 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
521 clock-names = "saradc", "apb_pclk";
522 resets = <&cru SRST_P_SARADC>;
523 reset-names = "saradc-apb";
528 compatible = "rockchip,rk3399-i2c";
529 reg = <0x0 0xff3c0000 0x0 0x1000>;
530 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
531 clock-names = "i2c", "pclk";
532 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c0_xfer>;
535 #address-cells = <1>;
541 compatible = "rockchip,rk3399-i2c";
542 reg = <0x0 0xff110000 0x0 0x1000>;
543 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
544 clock-names = "i2c", "pclk";
545 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c1_xfer>;
548 #address-cells = <1>;
554 compatible = "rockchip,rk3399-i2c";
555 reg = <0x0 0xff120000 0x0 0x1000>;
556 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
557 clock-names = "i2c", "pclk";
558 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c2_xfer>;
561 #address-cells = <1>;
567 compatible = "rockchip,rk3399-i2c";
568 reg = <0x0 0xff130000 0x0 0x1000>;
569 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
570 clock-names = "i2c", "pclk";
571 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c3_xfer>;
574 #address-cells = <1>;
580 compatible = "rockchip,rk3399-i2c";
581 reg = <0x0 0xff140000 0x0 0x1000>;
582 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
583 clock-names = "i2c", "pclk";
584 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c5_xfer>;
587 #address-cells = <1>;
593 compatible = "rockchip,rk3399-i2c";
594 reg = <0x0 0xff150000 0x0 0x1000>;
595 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
596 clock-names = "i2c", "pclk";
597 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&i2c6_xfer>;
600 #address-cells = <1>;
606 compatible = "rockchip,rk3399-i2c";
607 reg = <0x0 0xff160000 0x0 0x1000>;
608 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
609 clock-names = "i2c", "pclk";
610 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&i2c7_xfer>;
613 #address-cells = <1>;
618 uart0: serial@ff180000 {
619 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
620 reg = <0x0 0xff180000 0x0 0x100>;
621 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
622 clock-names = "baudclk", "apb_pclk";
623 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
631 uart1: serial@ff190000 {
632 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
633 reg = <0x0 0xff190000 0x0 0x100>;
634 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
635 clock-names = "baudclk", "apb_pclk";
636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&uart1_xfer>;
644 uart2: serial@ff1a0000 {
645 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
646 reg = <0x0 0xff1a0000 0x0 0x100>;
647 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
648 clock-names = "baudclk", "apb_pclk";
649 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&uart2c_xfer>;
657 uart3: serial@ff1b0000 {
658 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
659 reg = <0x0 0xff1b0000 0x0 0x100>;
660 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
661 clock-names = "baudclk", "apb_pclk";
662 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
665 pinctrl-names = "default";
666 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
671 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
672 reg = <0x0 0xff1c0000 0x0 0x1000>;
673 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
674 clock-names = "spiclk", "apb_pclk";
675 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
678 #address-cells = <1>;
684 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
685 reg = <0x0 0xff1d0000 0x0 0x1000>;
686 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
687 clock-names = "spiclk", "apb_pclk";
688 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
691 #address-cells = <1>;
697 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
698 reg = <0x0 0xff1e0000 0x0 0x1000>;
699 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
700 clock-names = "spiclk", "apb_pclk";
701 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
704 #address-cells = <1>;
710 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
711 reg = <0x0 0xff1f0000 0x0 0x1000>;
712 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
713 clock-names = "spiclk", "apb_pclk";
714 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
717 #address-cells = <1>;
723 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
724 reg = <0x0 0xff200000 0x0 0x1000>;
725 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
726 clock-names = "spiclk", "apb_pclk";
727 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
728 pinctrl-names = "default";
729 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
730 #address-cells = <1>;
735 thermal_zones: thermal-zones {
736 soc_thermal: soc-thermal {
737 polling-delay-passive = <20>; /* milliseconds */
738 polling-delay = <1000>; /* milliseconds */
739 sustainable-power = <1000>; /* milliwatts */
741 thermal-sensors = <&tsadc 0>;
744 threshold: trip-point@0 {
745 temperature = <70000>; /* millicelsius */
746 hysteresis = <2000>; /* millicelsius */
749 target: trip-point@1 {
750 temperature = <85000>; /* millicelsius */
751 hysteresis = <2000>; /* millicelsius */
755 temperature = <95000>; /* millicelsius */
756 hysteresis = <2000>; /* millicelsius */
765 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
766 contribution = <4096>;
771 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
772 contribution = <1024>;
777 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
778 contribution = <4096>;
783 gpu_thermal: gpu-thermal {
784 polling-delay-passive = <100>; /* milliseconds */
785 polling-delay = <1000>; /* milliseconds */
787 thermal-sensors = <&tsadc 1>;
791 tsadc: tsadc@ff260000 {
792 compatible = "rockchip,rk3399-tsadc";
793 reg = <0x0 0xff260000 0x0 0x100>;
794 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
795 rockchip,grf = <&grf>;
796 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
797 clock-names = "tsadc", "apb_pclk";
798 assigned-clocks = <&cru SCLK_TSADC>;
799 assigned-clock-rates = <750000>;
800 resets = <&cru SRST_TSADC>;
801 reset-names = "tsadc-apb";
802 pinctrl-names = "init", "default", "sleep";
803 pinctrl-0 = <&otp_gpio>;
804 pinctrl-1 = <&otp_out>;
805 pinctrl-2 = <&otp_gpio>;
806 #thermal-sensor-cells = <1>;
807 rockchip,hw-tshut-temp = <95000>;
811 qos_emmc: qos@ffa58000 {
812 compatible = "syscon";
813 reg = <0x0 0xffa58000 0x0 0x20>;
816 qos_gmac: qos@ffa5c000 {
817 compatible = "syscon";
818 reg = <0x0 0xffa5c000 0x0 0x20>;
821 qos_pcie: qos@ffa60080 {
822 compatible = "syscon";
823 reg = <0x0 0xffa60080 0x0 0x20>;
826 qos_usb_host0: qos@ffa60100 {
827 compatible = "syscon";
828 reg = <0x0 0xffa60100 0x0 0x20>;
831 qos_usb_host1: qos@ffa60180 {
832 compatible = "syscon";
833 reg = <0x0 0xffa60180 0x0 0x20>;
836 qos_usb_otg0: qos@ffa70000 {
837 compatible = "syscon";
838 reg = <0x0 0xffa70000 0x0 0x20>;
841 qos_usb_otg1: qos@ffa70080 {
842 compatible = "syscon";
843 reg = <0x0 0xffa70080 0x0 0x20>;
846 qos_sd: qos@ffa74000 {
847 compatible = "syscon";
848 reg = <0x0 0xffa74000 0x0 0x20>;
851 qos_sdioaudio: qos@ffa76000 {
852 compatible = "syscon";
853 reg = <0x0 0xffa76000 0x0 0x20>;
856 qos_hdcp: qos@ffa90000 {
857 compatible = "syscon";
858 reg = <0x0 0xffa90000 0x0 0x20>;
861 qos_iep: qos@ffa98000 {
862 compatible = "syscon";
863 reg = <0x0 0xffa98000 0x0 0x20>;
866 qos_isp0_m0: qos@ffaa0000 {
867 compatible = "syscon";
868 reg = <0x0 0xffaa0000 0x0 0x20>;
871 qos_isp0_m1: qos@ffaa0080 {
872 compatible = "syscon";
873 reg = <0x0 0xffaa0080 0x0 0x20>;
876 qos_isp1_m0: qos@ffaa8000 {
877 compatible = "syscon";
878 reg = <0x0 0xffaa8000 0x0 0x20>;
881 qos_isp1_m1: qos@ffaa8080 {
882 compatible = "syscon";
883 reg = <0x0 0xffaa8080 0x0 0x20>;
886 qos_rga_r: qos@ffab0000 {
887 compatible = "syscon";
888 reg = <0x0 0xffab0000 0x0 0x20>;
891 qos_rga_w: qos@ffab0080 {
892 compatible = "syscon";
893 reg = <0x0 0xffab0080 0x0 0x20>;
896 qos_video_m0: qos@ffab8000 {
897 compatible = "syscon";
898 reg = <0x0 0xffab8000 0x0 0x20>;
901 qos_video_m1_r: qos@ffac0000 {
902 compatible = "syscon";
903 reg = <0x0 0xffac0000 0x0 0x20>;
906 qos_video_m1_w: qos@ffac0080 {
907 compatible = "syscon";
908 reg = <0x0 0xffac0080 0x0 0x20>;
911 qos_vop_big_r: qos@ffac8000 {
912 compatible = "syscon";
913 reg = <0x0 0xffac8000 0x0 0x20>;
916 qos_vop_big_w: qos@ffac8080 {
917 compatible = "syscon";
918 reg = <0x0 0xffac8080 0x0 0x20>;
921 qos_vop_little: qos@ffad0000 {
922 compatible = "syscon";
923 reg = <0x0 0xffad0000 0x0 0x20>;
926 qos_perihp: qos@ffad8080 {
927 compatible = "syscon";
928 reg = <0x0 0xffad8080 0x0 0x20>;
931 qos_gpu: qos@ffae0000 {
932 compatible = "syscon";
933 reg = <0x0 0xffae0000 0x0 0x20>;
936 pmu: power-management@ff310000 {
937 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
938 reg = <0x0 0xff310000 0x0 0x1000>;
941 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
942 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
943 * Some of the power domains are grouped together for every
945 * The detail contents as below.
947 power: power-controller {
948 compatible = "rockchip,rk3399-power-controller";
949 #power-domain-cells = <1>;
950 #address-cells = <1>;
953 /* These power domains are grouped by VD_CENTER */
954 pd_iep@RK3399_PD_IEP {
955 reg = <RK3399_PD_IEP>;
956 clocks = <&cru ACLK_IEP>,
960 pd_rga@RK3399_PD_RGA {
961 reg = <RK3399_PD_RGA>;
962 clocks = <&cru ACLK_RGA>,
964 pm_qos = <&qos_rga_r>,
967 pd_vcodec@RK3399_PD_VCODEC {
968 reg = <RK3399_PD_VCODEC>;
969 clocks = <&cru ACLK_VCODEC>,
971 pm_qos = <&qos_video_m0>;
973 pd_vdu@RK3399_PD_VDU {
974 reg = <RK3399_PD_VDU>;
975 clocks = <&cru ACLK_VDU>,
977 pm_qos = <&qos_video_m1_r>,
981 /* These power domains are grouped by VD_GPU */
982 pd_gpu@RK3399_PD_GPU {
983 reg = <RK3399_PD_GPU>;
984 clocks = <&cru ACLK_GPU>;
988 /* These power domains are grouped by VD_LOGIC */
989 pd_edp@RK3399_PD_EDP {
990 reg = <RK3399_PD_EDP>;
991 clocks = <&cru PCLK_EDP_CTRL>;
993 pd_emmc@RK3399_PD_EMMC {
994 reg = <RK3399_PD_EMMC>;
995 clocks = <&cru ACLK_EMMC>;
996 pm_qos = <&qos_emmc>;
998 pd_gmac@RK3399_PD_GMAC {
999 reg = <RK3399_PD_GMAC>;
1000 clocks = <&cru ACLK_GMAC>,
1002 pm_qos = <&qos_gmac>;
1004 pd_perihp@RK3399_PD_PERIHP {
1005 reg = <RK3399_PD_PERIHP>;
1006 #address-cells = <1>;
1008 clocks = <&cru ACLK_PERIHP>;
1009 pm_qos = <&qos_perihp>,
1014 pd_sd@RK3399_PD_SD {
1015 reg = <RK3399_PD_SD>;
1016 clocks = <&cru HCLK_SDMMC>,
1021 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1022 reg = <RK3399_PD_SDIOAUDIO>;
1023 clocks = <&cru HCLK_SDIO>;
1024 pm_qos = <&qos_sdioaudio>;
1026 pd_usb3@RK3399_PD_USB3 {
1027 reg = <RK3399_PD_USB3>;
1028 clocks = <&cru ACLK_USB3>;
1029 pm_qos = <&qos_usb_otg0>,
1032 pd_vio@RK3399_PD_VIO {
1033 reg = <RK3399_PD_VIO>;
1034 #address-cells = <1>;
1037 pd_hdcp@RK3399_PD_HDCP {
1038 reg = <RK3399_PD_HDCP>;
1039 clocks = <&cru ACLK_HDCP>,
1042 pm_qos = <&qos_hdcp>;
1044 pd_isp0@RK3399_PD_ISP0 {
1045 reg = <RK3399_PD_ISP0>;
1046 clocks = <&cru ACLK_ISP0>,
1048 pm_qos = <&qos_isp0_m0>,
1051 pd_isp1@RK3399_PD_ISP1 {
1052 reg = <RK3399_PD_ISP1>;
1053 clocks = <&cru ACLK_ISP1>,
1055 pm_qos = <&qos_isp1_m0>,
1058 pd_tcpc0@RK3399_PD_TCPC0 {
1059 reg = <RK3399_PD_TCPD0>;
1060 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1061 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1063 pd_tcpc1@RK3399_PD_TCPC1 {
1064 reg = <RK3399_PD_TCPD1>;
1065 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1066 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1068 pd_vo@RK3399_PD_VO {
1069 reg = <RK3399_PD_VO>;
1070 #address-cells = <1>;
1073 pd_vopb@RK3399_PD_VOPB {
1074 reg = <RK3399_PD_VOPB>;
1075 clocks = <&cru ACLK_VOP0>,
1077 pm_qos = <&qos_vop_big_r>,
1080 pd_vopl@RK3399_PD_VOPL {
1081 reg = <RK3399_PD_VOPL>;
1082 clocks = <&cru ACLK_VOP1>,
1084 pm_qos = <&qos_vop_little>;
1091 pmugrf: syscon@ff320000 {
1092 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1093 reg = <0x0 0xff320000 0x0 0x1000>;
1094 #address-cells = <1>;
1097 pmu_io_domains: io-domains {
1098 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1099 status = "disabled";
1103 compatible = "syscon-reboot-mode";
1105 mode-bootloader = <BOOT_BL_DOWNLOAD>;
1106 mode-charge = <BOOT_CHARGING>;
1107 mode-fastboot = <BOOT_FASTBOOT>;
1108 mode-loader = <BOOT_BL_DOWNLOAD>;
1109 mode-normal = <BOOT_NORMAL>;
1110 mode-recovery = <BOOT_RECOVERY>;
1111 mode-ums = <BOOT_UMS>;
1114 pmu_pvtm: pmu-pvtm {
1115 compatible = "rockchip,rk3399-pmu-pvtm";
1116 clocks = <&pmucru SCLK_PVTM_PMU>;
1117 clock-names = "pmu";
1118 status = "disabled";
1122 spi3: spi@ff350000 {
1123 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1124 reg = <0x0 0xff350000 0x0 0x1000>;
1125 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1126 clock-names = "spiclk", "apb_pclk";
1127 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1130 #address-cells = <1>;
1132 status = "disabled";
1135 uart4: serial@ff370000 {
1136 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1137 reg = <0x0 0xff370000 0x0 0x100>;
1138 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1139 clock-names = "baudclk", "apb_pclk";
1140 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1143 pinctrl-names = "default";
1144 pinctrl-0 = <&uart4_xfer>;
1145 status = "disabled";
1148 i2c4: i2c@ff3d0000 {
1149 compatible = "rockchip,rk3399-i2c";
1150 reg = <0x0 0xff3d0000 0x0 0x1000>;
1151 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1152 clock-names = "i2c", "pclk";
1153 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1154 pinctrl-names = "default";
1155 pinctrl-0 = <&i2c4_xfer>;
1156 #address-cells = <1>;
1158 status = "disabled";
1161 i2c8: i2c@ff3e0000 {
1162 compatible = "rockchip,rk3399-i2c";
1163 reg = <0x0 0xff3e0000 0x0 0x1000>;
1164 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1165 clock-names = "i2c", "pclk";
1166 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1167 pinctrl-names = "default";
1168 pinctrl-0 = <&i2c8_xfer>;
1169 #address-cells = <1>;
1171 status = "disabled";
1174 pcie_phy: phy@e220 {
1175 compatible = "rockchip,rk3399-pcie-phy";
1177 rockchip,grf = <&grf>;
1178 clocks = <&cru SCLK_PCIEPHY_REF>;
1179 clock-names = "refclk";
1180 resets = <&cru SRST_PCIEPHY>;
1181 reset-names = "phy";
1182 status = "disabled";
1185 pcie0: pcie@f8000000 {
1186 compatible = "rockchip,rk3399-pcie";
1187 #address-cells = <3>;
1190 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1191 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1192 clock-names = "aclk", "aclk-perf",
1194 bus-range = <0x0 0x1>;
1195 max-link-speed = <1>;
1196 linux,pci-domain = <0>;
1197 msi-map = <0x0 &its 0x0 0x1000>;
1198 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1199 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1200 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1201 interrupt-names = "sys", "legacy", "client";
1202 #interrupt-cells = <1>;
1203 interrupt-map-mask = <0 0 0 7>;
1204 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1205 <0 0 0 2 &pcie0_intc 1>,
1206 <0 0 0 3 &pcie0_intc 2>,
1207 <0 0 0 4 &pcie0_intc 3>;
1209 phy-names = "pcie-phy";
1210 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1211 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1212 reg = <0x0 0xf8000000 0x0 0x2000000>,
1213 <0x0 0xfd000000 0x0 0x1000000>;
1214 reg-names = "axi-base", "apb-base";
1215 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1216 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1217 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1219 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1220 "pm", "pclk", "aclk";
1221 status = "disabled";
1222 pcie0_intc: interrupt-controller {
1223 interrupt-controller;
1224 #address-cells = <0>;
1225 #interrupt-cells = <1>;
1229 pwm0: pwm@ff420000 {
1230 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1231 reg = <0x0 0xff420000 0x0 0x10>;
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&pwm0_pin>;
1235 clocks = <&pmucru PCLK_RKPWM_PMU>;
1236 clock-names = "pwm";
1237 status = "disabled";
1240 pwm1: pwm@ff420010 {
1241 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1242 reg = <0x0 0xff420010 0x0 0x10>;
1244 pinctrl-names = "default";
1245 pinctrl-0 = <&pwm1_pin>;
1246 clocks = <&pmucru PCLK_RKPWM_PMU>;
1247 clock-names = "pwm";
1248 status = "disabled";
1251 pwm2: pwm@ff420020 {
1252 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1253 reg = <0x0 0xff420020 0x0 0x10>;
1255 pinctrl-names = "default";
1256 pinctrl-0 = <&pwm2_pin>;
1257 clocks = <&pmucru PCLK_RKPWM_PMU>;
1258 clock-names = "pwm";
1259 status = "disabled";
1262 pwm3: pwm@ff420030 {
1263 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1264 reg = <0x0 0xff420030 0x0 0x10>;
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&pwm3a_pin>;
1268 clocks = <&pmucru PCLK_RKPWM_PMU>;
1269 clock-names = "pwm";
1270 status = "disabled";
1274 reg = <0x00 0xff630000 0x00 0x4000>;
1275 compatible = "rockchip,rk3399-dfi";
1276 rockchip,pmu = <&pmugrf>;
1277 clocks = <&cru PCLK_DDR_MON>;
1278 clock-names = "pclk_ddr_mon";
1279 status = "disabled";
1283 compatible = "rockchip,rk3399-dmc";
1284 devfreq-events = <&dfi>;
1285 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1286 clocks = <&cru SCLK_DDRCLK>;
1287 clock-names = "dmc_clk";
1288 ddr_timing = <&ddr_timing>;
1289 status = "disabled";
1292 vpu: vpu_service@ff650000 {
1293 compatible = "rockchip,vpu_service";
1294 rockchip,grf = <&grf>;
1295 iommus = <&vpu_mmu>;
1296 iommu_enabled = <1>;
1297 reg = <0x0 0xff650000 0x0 0x800>;
1298 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1299 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1300 interrupt-names = "irq_dec", "irq_enc";
1301 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1302 clock-names = "aclk_vcodec", "hclk_vcodec";
1303 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1304 reset-names = "video_h", "video_a";
1305 power-domains = <&power RK3399_PD_VCODEC>;
1306 name = "vpu_service";
1308 /* 0 means ion, 1 means drm */
1310 status = "disabled";
1313 vpu_mmu: iommu@ff650800 {
1314 compatible = "rockchip,iommu";
1315 reg = <0x0 0xff650800 0x0 0x40>;
1316 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1317 interrupt-names = "vpu_mmu";
1318 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1319 clock-names = "aclk", "hclk";
1320 power-domains = <&power RK3399_PD_VCODEC>;
1324 rkvdec: rkvdec@ff660000 {
1325 compatible = "rockchip,rkvdec";
1326 rockchip,grf = <&grf>;
1327 iommus = <&vdec_mmu>;
1328 iommu_enabled = <1>;
1329 reg = <0x0 0xff660000 0x0 0x400>;
1330 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1331 interrupt-names = "irq_dec";
1332 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1333 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1334 clock-names = "aclk_vcodec", "hclk_vcodec",
1335 "clk_cabac", "clk_core";
1336 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
1337 reset-names = "video_h", "video_a";
1338 power-domains = <&power RK3399_PD_VDU>;
1341 /* 0 means ion, 1 means drm */
1343 status = "disabled";
1346 vdec_mmu: iommu@ff660480 {
1347 compatible = "rockchip,iommu";
1348 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1349 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1350 interrupt-names = "vdec_mmu";
1351 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1352 clock-names = "aclk", "hclk";
1353 power-domains = <&power RK3399_PD_VDU>;
1358 compatible = "rockchip,iep";
1359 iommu_enabled = <1>;
1360 iommus = <&iep_mmu>;
1361 reg = <0x0 0xff670000 0x0 0x800>;
1362 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1363 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1364 clock-names = "aclk_iep", "hclk_iep";
1365 power-domains = <&power RK3399_PD_IEP>;
1368 status = "disabled";
1371 iep_mmu: iommu@ff670800 {
1372 compatible = "rockchip,iommu";
1373 reg = <0x0 0xff670800 0x0 0x40>;
1374 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1375 interrupt-names = "iep_mmu";
1377 status = "disabled";
1381 compatible = "rockchip,rk3399-rga";
1382 reg = <0x0 0xff680000 0x0 0x10000>;
1383 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1384 interrupt-names = "rga";
1385 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1386 clock-names = "aclk", "hclk", "sclk";
1387 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1388 reset-names = "core", "axi", "ahb";
1389 power-domains = <&power RK3399_PD_RGA>;
1390 status = "disabled";
1393 efuse0: efuse@ff690000 {
1394 compatible = "rockchip,rk3399-efuse";
1395 reg = <0x0 0xff690000 0x0 0x80>;
1396 #address-cells = <1>;
1398 clocks = <&cru PCLK_EFUSE1024NS>;
1399 clock-names = "pclk_efuse";
1405 cpul_leakage: cpul-leakage {
1408 cpub_leakage: cpub-leakage {
1411 gpu_leakage: gpu-leakage {
1414 center_leakage: center-leakage {
1417 logic_leakage: logic-leakage {
1420 wafer_info: wafer-info {
1425 pmucru: pmu-clock-controller@ff750000 {
1426 compatible = "rockchip,rk3399-pmucru";
1427 reg = <0x0 0xff750000 0x0 0x1000>;
1430 assigned-clocks = <&pmucru PLL_PPLL>;
1431 assigned-clock-rates = <676000000>;
1434 cru: clock-controller@ff760000 {
1435 compatible = "rockchip,rk3399-cru";
1436 reg = <0x0 0xff760000 0x0 0x1000>;
1440 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1441 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1442 <&cru ARMCLKL>, <&cru ARMCLKB>,
1443 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1444 <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1445 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1447 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1448 <&cru PCLK_PERILP0>,
1449 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1450 assigned-clock-rates =
1451 <400000000>, <200000000>,
1452 <400000000>, <200000000>,
1453 <816000000>, <816000000>,
1454 <594000000>, <800000000>,
1455 <200000000>, <1000000000>,
1456 <150000000>, <75000000>,
1458 <100000000>, <100000000>,
1460 <100000000>, <50000000>;
1463 grf: syscon@ff770000 {
1464 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1465 reg = <0x0 0xff770000 0x0 0x10000>;
1466 #address-cells = <1>;
1469 io_domains: io-domains {
1470 compatible = "rockchip,rk3399-io-voltage-domain";
1471 status = "disabled";
1474 emmc_phy: phy@f780 {
1475 compatible = "rockchip,rk3399-emmc-phy";
1476 reg = <0xf780 0x24>;
1478 clock-names = "emmcclk";
1480 status = "disabled";
1483 u2phy0: usb2-phy@e450 {
1484 compatible = "rockchip,rk3399-usb2phy";
1485 reg = <0xe450 0x10>;
1486 clocks = <&cru SCLK_USB2PHY0_REF>;
1487 clock-names = "phyclk";
1489 clock-output-names = "clk_usbphy0_480m";
1490 status = "disabled";
1492 u2phy0_otg: otg-port {
1494 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1495 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1496 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1497 interrupt-names = "otg-bvalid", "otg-id",
1499 status = "disabled";
1502 u2phy0_host: host-port {
1504 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1505 interrupt-names = "linestate";
1506 status = "disabled";
1510 u2phy1: usb2-phy@e460 {
1511 compatible = "rockchip,rk3399-usb2phy";
1512 reg = <0xe460 0x10>;
1513 clocks = <&cru SCLK_USB2PHY1_REF>;
1514 clock-names = "phyclk";
1516 clock-output-names = "clk_usbphy1_480m";
1517 status = "disabled";
1519 u2phy1_otg: otg-port {
1521 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1522 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1523 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1524 interrupt-names = "otg-bvalid", "otg-id",
1526 status = "disabled";
1529 u2phy1_host: host-port {
1531 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1532 interrupt-names = "linestate";
1533 status = "disabled";
1538 compatible = "rockchip,rk3399-pvtm";
1539 clocks = <&cru SCLK_PVTM_CORE_L>,
1540 <&cru SCLK_PVTM_CORE_B>,
1541 <&cru SCLK_PVTM_GPU>,
1542 <&cru SCLK_PVTM_DDR>;
1543 clock-names = "core_l", "core_b", "gpu", "ddr";
1544 status = "disabled";
1548 tcphy0: phy@ff7c0000 {
1549 compatible = "rockchip,rk3399-typec-phy";
1550 reg = <0x0 0xff7c0000 0x0 0x40000>;
1551 rockchip,grf = <&grf>;
1553 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1554 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1555 clock-names = "tcpdcore", "tcpdphy-ref";
1556 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1557 assigned-clock-rates = <50000000>;
1558 power-domains = <&power RK3399_PD_TCPD0>;
1559 resets = <&cru SRST_UPHY0>,
1560 <&cru SRST_UPHY0_PIPE_L00>,
1561 <&cru SRST_P_UPHY0_TCPHY>;
1562 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1563 rockchip,typec-conn-dir = <0xe580 0 16>;
1564 rockchip,usb3tousb2-en = <0xe580 3 19>;
1565 rockchip,usb3-host-disable = <0x2434 0 16>;
1566 rockchip,usb3-host-port = <0x2434 12 28>;
1567 rockchip,external-psm = <0xe588 14 30>;
1568 rockchip,pipe-status = <0xe5c0 0 0>;
1569 rockchip,uphy-dp-sel = <0x6268 19 19>;
1570 status = "disabled";
1572 tcphy0_dp: dp-port {
1576 tcphy0_usb3: usb3-port {
1581 tcphy1: phy@ff800000 {
1582 compatible = "rockchip,rk3399-typec-phy";
1583 reg = <0x0 0xff800000 0x0 0x40000>;
1584 rockchip,grf = <&grf>;
1586 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1587 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1588 clock-names = "tcpdcore", "tcpdphy-ref";
1589 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1590 assigned-clock-rates = <50000000>;
1591 power-domains = <&power RK3399_PD_TCPD1>;
1592 resets = <&cru SRST_UPHY1>,
1593 <&cru SRST_UPHY1_PIPE_L00>,
1594 <&cru SRST_P_UPHY1_TCPHY>;
1595 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1596 rockchip,typec-conn-dir = <0xe58c 0 16>;
1597 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1598 rockchip,usb3-host-disable = <0x2444 0 16>;
1599 rockchip,usb3-host-port = <0x2444 12 28>;
1600 rockchip,external-psm = <0xe594 14 30>;
1601 rockchip,pipe-status = <0xe5c0 16 16>;
1602 rockchip,uphy-dp-sel = <0x6268 3 19>;
1603 status = "disabled";
1605 tcphy1_dp: dp-port {
1609 tcphy1_usb3: usb3-port {
1615 compatible = "snps,dw-wdt";
1616 reg = <0x0 0xff848000 0x0 0x100>;
1617 clocks = <&cru PCLK_WDT>;
1618 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1621 rktimer: rktimer@ff850000 {
1622 compatible = "rockchip,rk3399-timer";
1623 reg = <0x0 0xff850000 0x0 0x1000>;
1624 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1625 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1626 clock-names = "pclk", "timer";
1629 spdif: spdif@ff870000 {
1630 compatible = "rockchip,rk3399-spdif";
1631 reg = <0x0 0xff870000 0x0 0x1000>;
1632 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1633 dmas = <&dmac_bus 7>;
1635 clock-names = "mclk", "hclk";
1636 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1637 pinctrl-names = "default";
1638 pinctrl-0 = <&spdif_bus>;
1639 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1640 status = "disabled";
1643 i2s0: i2s@ff880000 {
1644 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1645 reg = <0x0 0xff880000 0x0 0x1000>;
1646 rockchip,grf = <&grf>;
1647 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1648 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1649 dma-names = "tx", "rx";
1650 clock-names = "i2s_clk", "i2s_hclk";
1651 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1652 pinctrl-names = "default";
1653 pinctrl-0 = <&i2s0_8ch_bus>;
1654 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1655 status = "disabled";
1658 i2s1: i2s@ff890000 {
1659 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1660 reg = <0x0 0xff890000 0x0 0x1000>;
1661 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1662 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1663 dma-names = "tx", "rx";
1664 clock-names = "i2s_clk", "i2s_hclk";
1665 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1666 pinctrl-names = "default";
1667 pinctrl-0 = <&i2s1_2ch_bus>;
1668 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1669 status = "disabled";
1672 i2s2: i2s@ff8a0000 {
1673 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1674 reg = <0x0 0xff8a0000 0x0 0x1000>;
1675 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1676 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1677 dma-names = "tx", "rx";
1678 clock-names = "i2s_clk", "i2s_hclk";
1679 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1680 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1681 status = "disabled";
1685 compatible = "arm,malit860",
1690 reg = <0x0 0xff9a0000 0x0 0x10000>;
1692 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1693 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1694 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1695 interrupt-names = "GPU", "JOB", "MMU";
1697 clocks = <&cru ACLK_GPU>;
1698 clock-names = "clk_mali";
1699 #cooling-cells = <2>; /* min followed by max */
1700 power-domains = <&power RK3399_PD_GPU>;
1701 power-off-delay-ms = <200>;
1702 status = "disabled";
1704 gpu_power_model: power_model {
1705 compatible = "arm,mali-simple-power-model";
1708 static-power = <300>;
1709 dynamic-power = <396>;
1710 ts = <32000 4700 (-80) 2>;
1711 thermal-zone = "gpu-thermal";
1715 vopl: vop@ff8f0000 {
1716 compatible = "rockchip,rk3399-vop-lit";
1717 reg = <0x0 0xff8f0000 0x0 0x600>,
1718 <0x0 0xff8f1c00 0x0 0x200>,
1719 <0x0 0xff8f2000 0x0 0x400>;
1720 reg-names = "regs", "cabc_lut", "gamma_lut";
1721 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1722 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>;
1723 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
1724 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1725 reset-names = "axi", "ahb", "dclk";
1726 power-domains = <&power RK3399_PD_VOPL>;
1727 iommus = <&vopl_mmu>;
1728 status = "disabled";
1731 #address-cells = <1>;
1734 vopl_out_dsi: endpoint@0 {
1736 remote-endpoint = <&dsi_in_vopl>;
1739 vopl_out_edp: endpoint@1 {
1741 remote-endpoint = <&edp_in_vopl>;
1744 vopl_out_hdmi: endpoint@2 {
1746 remote-endpoint = <&hdmi_in_vopl>;
1749 vopl_out_dp: endpoint@3 {
1751 remote-endpoint = <&dp_in_vopl>;
1756 vop1_pwm: voppwm@ff8f01a0 {
1757 compatible = "rockchip,vop-pwm";
1758 reg = <0x0 0xff8f01a0 0x0 0x10>;
1760 pinctrl-names = "default";
1761 pinctrl-0 = <&vop1_pwm_pin>;
1762 clocks = <&cru SCLK_VOP1_PWM>;
1763 clock-names = "pwm";
1764 status = "disabled";
1767 vopl_mmu: iommu@ff8f3f00 {
1768 compatible = "rockchip,iommu";
1769 reg = <0x0 0xff8f3f00 0x0 0x100>;
1770 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1771 interrupt-names = "vopl_mmu";
1772 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1773 clock-names = "aclk", "hclk";
1774 power-domains = <&power RK3399_PD_VOPL>;
1776 status = "disabled";
1779 vopb: vop@ff900000 {
1780 compatible = "rockchip,rk3399-vop-big";
1781 reg = <0x0 0xff900000 0x0 0x600>,
1782 <0x0 0xff901c00 0x0 0x200>,
1783 <0x0 0xff902000 0x0 0x1000>;
1784 reg-names = "regs", "cabc_lut", "gamma_lut";
1785 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1786 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>;
1787 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
1788 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1789 reset-names = "axi", "ahb", "dclk";
1790 power-domains = <&power RK3399_PD_VOPB>;
1791 iommus = <&vopb_mmu>;
1792 status = "disabled";
1795 #address-cells = <1>;
1798 vopb_out_edp: endpoint@0 {
1800 remote-endpoint = <&edp_in_vopb>;
1803 vopb_out_dsi: endpoint@1 {
1805 remote-endpoint = <&dsi_in_vopb>;
1808 vopb_out_hdmi: endpoint@2 {
1810 remote-endpoint = <&hdmi_in_vopb>;
1813 vopb_out_dp: endpoint@3 {
1815 remote-endpoint = <&dp_in_vopb>;
1820 vop0_pwm: voppwm@ff9001a0 {
1821 compatible = "rockchip,vop-pwm";
1822 reg = <0x0 0xff9001a0 0x0 0x10>;
1824 pinctrl-names = "default";
1825 pinctrl-0 = <&vop0_pwm_pin>;
1826 clocks = <&cru SCLK_VOP0_PWM>;
1827 clock-names = "pwm";
1828 status = "disabled";
1831 vopb_mmu: iommu@ff903f00 {
1832 compatible = "rockchip,iommu";
1833 reg = <0x0 0xff903f00 0x0 0x100>;
1834 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1835 interrupt-names = "vopb_mmu";
1836 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1837 clock-names = "aclk", "hclk";
1838 power-domains = <&power RK3399_PD_VOPB>;
1840 status = "disabled";
1843 isp0_mmu: iommu@ff914000 {
1844 compatible = "rockchip,iommu";
1845 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1846 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1847 interrupt-names = "isp0_mmu";
1849 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1850 clock-names = "aclk", "hclk";
1851 power-domains = <&power RK3399_PD_ISP0>;
1852 rk_iommu,disable_reset_quirk;
1853 status = "disabled";
1856 isp1_mmu: iommu@ff924000 {
1857 compatible = "rockchip,iommu";
1858 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1859 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1860 interrupt-names = "isp1_mmu";
1862 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1863 clock-names = "aclk", "hclk";
1864 power-domains = <&power RK3399_PD_ISP1>;
1865 rk_iommu,disable_reset_quirk;
1866 status = "disabled";
1869 hdmi: hdmi@ff940000 {
1870 compatible = "rockchip,rk3399-dw-hdmi";
1871 reg = <0x0 0xff940000 0x0 0x20000>;
1873 rockchip,grf = <&grf>;
1874 pinctrl-names = "default";
1875 pinctrl-0 = <&hdmi_i2c_xfer>;
1876 power-domains = <&power RK3399_PD_HDCP>;
1877 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1878 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1879 clock-names = "iahb", "isfr", "vpll", "grf";
1880 status = "disabled";
1884 #address-cells = <1>;
1886 hdmi_in_vopb: endpoint@0 {
1888 remote-endpoint = <&vopb_out_hdmi>;
1890 hdmi_in_vopl: endpoint@1 {
1892 remote-endpoint = <&vopl_out_hdmi>;
1899 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1900 reg = <0x0 0xff960000 0x0 0x8000>;
1901 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1902 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1903 <&cru SCLK_DPHY_TX0_CFG>;
1904 clock-names = "ref", "pclk", "phy_cfg";
1905 power-domains = <&power RK3399_PD_VIO>;
1906 rockchip,grf = <&grf>;
1907 #address-cells = <1>;
1909 status = "disabled";
1913 #address-cells = <1>;
1916 dsi_in_vopb: endpoint@0 {
1918 remote-endpoint = <&vopb_out_dsi>;
1921 dsi_in_vopl: endpoint@1 {
1923 remote-endpoint = <&vopl_out_dsi>;
1930 compatible = "rockchip,rk3399-edp";
1931 reg = <0x0 0xff970000 0x0 0x8000>;
1932 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1933 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1934 clock-names = "dp", "pclk";
1935 power-domains = <&power RK3399_PD_EDP>;
1936 resets = <&cru SRST_P_EDP_CTRL>;
1938 rockchip,grf = <&grf>;
1939 status = "disabled";
1940 pinctrl-names = "default";
1941 pinctrl-0 = <&edp_hpd>;
1944 #address-cells = <1>;
1949 #address-cells = <1>;
1952 edp_in_vopb: endpoint@0 {
1954 remote-endpoint = <&vopb_out_edp>;
1957 edp_in_vopl: endpoint@1 {
1959 remote-endpoint = <&vopl_out_edp>;
1965 display_subsystem: display-subsystem {
1966 compatible = "rockchip,display-subsystem";
1967 ports = <&vopl_out>, <&vopb_out>;
1968 clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>;
1969 clock-names = "hdmi-tmds-pll", "default-vop-pll";
1970 status = "disabled";
1974 compatible = "rockchip,rk3399-pinctrl";
1975 rockchip,grf = <&grf>;
1976 rockchip,pmu = <&pmugrf>;
1977 #address-cells = <0x2>;
1978 #size-cells = <0x2>;
1981 gpio0: gpio0@ff720000 {
1982 compatible = "rockchip,gpio-bank";
1983 reg = <0x0 0xff720000 0x0 0x100>;
1984 clocks = <&pmucru PCLK_GPIO0_PMU>;
1985 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1988 #gpio-cells = <0x2>;
1990 interrupt-controller;
1991 #interrupt-cells = <0x2>;
1994 gpio1: gpio1@ff730000 {
1995 compatible = "rockchip,gpio-bank";
1996 reg = <0x0 0xff730000 0x0 0x100>;
1997 clocks = <&pmucru PCLK_GPIO1_PMU>;
1998 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
2001 #gpio-cells = <0x2>;
2003 interrupt-controller;
2004 #interrupt-cells = <0x2>;
2007 gpio2: gpio2@ff780000 {
2008 compatible = "rockchip,gpio-bank";
2009 reg = <0x0 0xff780000 0x0 0x100>;
2010 clocks = <&cru PCLK_GPIO2>;
2011 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2014 #gpio-cells = <0x2>;
2016 interrupt-controller;
2017 #interrupt-cells = <0x2>;
2020 gpio3: gpio3@ff788000 {
2021 compatible = "rockchip,gpio-bank";
2022 reg = <0x0 0xff788000 0x0 0x100>;
2023 clocks = <&cru PCLK_GPIO3>;
2024 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2027 #gpio-cells = <0x2>;
2029 interrupt-controller;
2030 #interrupt-cells = <0x2>;
2033 gpio4: gpio4@ff790000 {
2034 compatible = "rockchip,gpio-bank";
2035 reg = <0x0 0xff790000 0x0 0x100>;
2036 clocks = <&cru PCLK_GPIO4>;
2037 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2040 #gpio-cells = <0x2>;
2042 interrupt-controller;
2043 #interrupt-cells = <0x2>;
2046 pcfg_pull_up: pcfg-pull-up {
2050 pcfg_pull_down: pcfg-pull-down {
2054 pcfg_pull_none: pcfg-pull-none {
2058 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2060 drive-strength = <20>;
2063 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2065 drive-strength = <20>;
2068 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2070 drive-strength = <18>;
2073 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2075 drive-strength = <12>;
2078 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2080 drive-strength = <8>;
2083 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2085 drive-strength = <4>;
2088 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2090 drive-strength = <2>;
2093 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2095 drive-strength = <12>;
2098 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2100 drive-strength = <13>;
2103 pcfg_output_high: pcfg-output-high {
2107 pcfg_output_low: pcfg-output-low {
2111 pcfg_input: pcfg-input {
2116 emmc_pwr: emmc-pwr {
2118 <0 5 RK_FUNC_1 &pcfg_pull_up>;
2123 rgmii_pins: rgmii-pins {
2126 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2128 <3 14 RK_FUNC_1 &pcfg_pull_none>,
2130 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2132 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2134 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2136 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2138 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2140 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2142 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2144 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2146 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2148 <3 3 RK_FUNC_1 &pcfg_pull_none>,
2150 <3 2 RK_FUNC_1 &pcfg_pull_none>,
2152 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2154 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2157 rmii_pins: rmii-pins {
2160 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2162 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2164 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2166 <3 10 RK_FUNC_1 &pcfg_pull_none>,
2168 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2170 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2172 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2174 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2176 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2178 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2183 i2c0_xfer: i2c0-xfer {
2185 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2186 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2191 i2c1_xfer: i2c1-xfer {
2193 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2194 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2199 i2c2_xfer: i2c2-xfer {
2201 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2202 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2207 i2c3_xfer: i2c3-xfer {
2209 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2210 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2213 i2c3_gpio: i2c3_gpio {
2215 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2216 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2222 i2c4_xfer: i2c4-xfer {
2224 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2225 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2230 i2c5_xfer: i2c5-xfer {
2232 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2233 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2238 i2c6_xfer: i2c6-xfer {
2240 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2241 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2246 i2c7_xfer: i2c7-xfer {
2248 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2249 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2254 i2c8_xfer: i2c8-xfer {
2256 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2257 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2262 i2s0_8ch_bus: i2s0-8ch-bus {
2264 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2265 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2266 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2267 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2268 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2269 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2270 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2271 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2272 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2277 i2s1_2ch_bus: i2s1-2ch-bus {
2279 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2280 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2281 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2282 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2283 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2288 sdio0_bus1: sdio0-bus1 {
2290 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2293 sdio0_bus4: sdio0-bus4 {
2295 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2296 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2297 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2298 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2301 sdio0_cmd: sdio0-cmd {
2303 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2306 sdio0_clk: sdio0-clk {
2308 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2311 sdio0_cd: sdio0-cd {
2313 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2316 sdio0_pwr: sdio0-pwr {
2318 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2321 sdio0_bkpwr: sdio0-bkpwr {
2323 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2326 sdio0_wp: sdio0-wp {
2328 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2331 sdio0_int: sdio0-int {
2333 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2338 sdmmc_bus1: sdmmc-bus1 {
2340 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2343 sdmmc_bus4: sdmmc-bus4 {
2345 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2346 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2347 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2348 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2351 sdmmc_clk: sdmmc-clk {
2353 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2356 sdmmc_cmd: sdmmc-cmd {
2358 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2361 sdmmc_cd: sdmcc-cd {
2363 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2366 sdmmc_wp: sdmmc-wp {
2368 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2373 spdif_bus: spdif-bus {
2375 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2378 spdif_bus_1: spdif-bus-1 {
2380 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2385 spi0_clk: spi0-clk {
2387 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2389 spi0_cs0: spi0-cs0 {
2391 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2393 spi0_cs1: spi0-cs1 {
2395 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2399 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2403 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2408 spi1_clk: spi1-clk {
2410 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2412 spi1_cs0: spi1-cs0 {
2414 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2418 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2422 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2427 spi2_clk: spi2-clk {
2429 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2431 spi2_cs0: spi2-cs0 {
2433 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2437 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2441 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2446 spi3_clk: spi3-clk {
2448 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2450 spi3_cs0: spi3-cs0 {
2452 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2456 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2460 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2465 spi4_clk: spi4-clk {
2467 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2469 spi4_cs0: spi4-cs0 {
2471 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2475 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2479 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2484 spi5_clk: spi5-clk {
2486 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2488 spi5_cs0: spi5-cs0 {
2490 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2494 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2498 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2503 otp_gpio: otp-gpio {
2504 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2508 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2513 uart0_xfer: uart0-xfer {
2515 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2516 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2519 uart0_cts: uart0-cts {
2521 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2524 uart0_rts: uart0-rts {
2526 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2531 uart1_xfer: uart1-xfer {
2533 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2534 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2539 uart2a_xfer: uart2a-xfer {
2541 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2542 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2547 uart2b_xfer: uart2b-xfer {
2549 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2550 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2555 uart2c_xfer: uart2c-xfer {
2557 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2558 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2563 uart3_xfer: uart3-xfer {
2565 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2566 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2569 uart3_cts: uart3-cts {
2571 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2574 uart3_rts: uart3-rts {
2576 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2581 uart4_xfer: uart4-xfer {
2583 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2584 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2589 uarthdcp_xfer: uarthdcp-xfer {
2591 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2592 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2597 pwm0_pin: pwm0-pin {
2599 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2602 vop0_pwm_pin: vop0-pwm-pin {
2604 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2609 pwm1_pin: pwm1-pin {
2611 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2614 vop1_pwm_pin: vop1-pwm-pin {
2616 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2621 pwm2_pin: pwm2-pin {
2623 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2628 pwm3a_pin: pwm3a-pin {
2630 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2635 pwm3b_pin: pwm3b-pin {
2637 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2644 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2649 hdmi_i2c_xfer: hdmi-i2c-xfer {
2651 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2652 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2655 hdmi_cec: hdmi-cec {
2657 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2662 pcie_clkreqn: pci-clkreqn {
2664 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2667 pcie_clkreqnb: pci-clkreqnb {
2669 <4 24 RK_FUNC_1 &pcfg_pull_none>;
2672 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2674 * Since our pcie doesn't support
2675 * ClockPM(CPM), we want to hack this as
2676 * gpio, so the EP could be able to
2677 * de-assert it along and make ClockPM(CPM)
2681 <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2684 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2686 <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2691 rockchip_suspend: rockchip-suspend {
2692 compatible = "rockchip,pm-rk3399";
2693 status = "disabled";
2694 rockchip,sleep-debug-en = <0>;
2695 rockchip,virtual-poweroff = <0>;
2696 rockchip,sleep-mode-config = <
2703 | RKPM_SLP_CENTER_PD
2704 | RKPM_SLP_AP_PWROFF
2707 rockchip,wakeup-config = <