arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/clock/rk3399-cru.h>
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/pinctrl/rockchip.h>
  47 #include <dt-bindings/thermal/thermal.h>
  48
  49 / {
  50         compatible = "rockchip,rk3399";
  51         interrupt-parent = <&gic>;
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 i2c6 = &i2c6;
  63                 i2c7 = &i2c7;
  64                 i2c8 = &i2c8;
  65                 serial0 = &uart0;
  66                 serial1 = &uart1;
  67                 serial2 = &uart2;
  68                 serial3 = &uart3;
  69         };
  70
  71         cpus {
  72                 #address-cells = <2>;
  73                 #size-cells = <0>;
  74
  75                 cpu-map {
  76                         cluster0 {
  77                                 core0 {
  78                                         cpu = <&cpu_l0>;
  79                                 };
  80                                 core1 {
  81                                         cpu = <&cpu_l1>;
  82                                 };
  83                                 core2 {
  84                                         cpu = <&cpu_l2>;
  85                                 };
  86                                 core3 {
  87                                         cpu = <&cpu_l3>;
  88                                 };
  89                         };
  90
  91                         cluster1 {
  92                                 core0 {
  93                                         cpu = <&cpu_b0>;
  94                                 };
  95                                 core1 {
  96                                         cpu = <&cpu_b1>;
  97                                 };
  98                         };
  99                 };
 100
 101                 cpu_l0: cpu@0 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53", "arm,armv8";
 104                         reg = <0x0 0x0>;
 105
 106                         #cooling-cells = <2>; /* min followed by max */
 107                 };
 108
 109                 cpu_l1: cpu@1 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x1>;
 113                 };
 114
 115                 cpu_l2: cpu@2 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53", "arm,armv8";
 118                         reg = <0x0 0x2>;
 119                 };
 120
 121                 cpu_l3: cpu@3 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a53", "arm,armv8";
 124                         reg = <0x0 0x3>;
 125                 };
 126
 127                 cpu_b0: cpu@100 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a72", "arm,armv8";
 130                         reg = <0x0 0x100>;
 131
 132                         #cooling-cells = <2>; /* min followed by max */
 133                 };
 134
 135                 cpu_b1: cpu@101 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a72", "arm,armv8";
 138                         reg = <0x0 0x101>;
 139                 };
 140         };
 141
 142         timer {
 143                 compatible = "arm,armv8-timer";
 144                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 148         };
 149
 150         xin24m: xin24m {
 151                 compatible = "fixed-clock";
 152                 #clock-cells = <0>;
 153                 clock-frequency = <24000000>;
 154                 clock-output-names = "xin24m";
 155         };
 156
 157         gic: interrupt-controller@fee00000 {
 158                 compatible = "arm,gic-v3";
 159                 #interrupt-cells = <3>;
 160                 #address-cells = <2>;
 161                 #size-cells = <2>;
 162                 ranges;
 163                 interrupt-controller;
 164
 165                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 166                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 167                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 168                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 169                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 170                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 171                 its: interrupt-controller@fee20000 {
 172                         compatible = "arm,gic-v3-its";
 173                         msi-controller;
 174                         reg = <0x0 0xfee20000 0x0 0x20000>;
 175                 };
 176         };
 177
 178         amba {
 179                 compatible = "arm,amba-bus";
 180                 #address-cells = <2>;
 181                 #size-cells = <2>;
 182                 ranges;
 183
 184                 dmac_bus: dma-controller@ff6d0000 {
 185                         compatible = "arm,pl330", "arm,primecell";
 186                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 187                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 188                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 189                         #dma-cells = <1>;
 190                         clocks = <&cru ACLK_DMAC0_PERILP>;
 191                         clock-names = "apb_pclk";
 192                 };
 193
 194                 dmac_peri: dma-controller@ff6e0000 {
 195                         compatible = "arm,pl330", "arm,primecell";
 196                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 197                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 199                         #dma-cells = <1>;
 200                         clocks = <&cru ACLK_DMAC1_PERILP>;
 201                         clock-names = "apb_pclk";
 202                 };
 203         };
 204
 205         i2c0: i2c@ff3c0000 {
 206                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 207                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 208                 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
 209                 clock-names = "i2c", "i2c_sclk";
 210                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&i2c0_xfer>;
 213                 #address-cells = <1>;
 214                 #size-cells = <0>;
 215                 status = "disabled";
 216         };
 217
 218         i2c1: i2c@ff110000 {
 219                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 220                 reg = <0x0 0xff110000 0x0 0x1000>;
 221                 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
 222                 clock-names = "i2c", "i2c_sclk";
 223                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 224                 pinctrl-names = "default";
 225                 pinctrl-0 = <&i2c1_xfer>;
 226                 #address-cells = <1>;
 227                 #size-cells = <0>;
 228                 status = "disabled";
 229         };
 230
 231         i2c2: i2c@ff120000 {
 232                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 233                 reg = <0x0 0xff120000 0x0 0x1000>;
 234                 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
 235                 clock-names = "i2c", "i2c_sclk";
 236                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 237                 pinctrl-names = "default";
 238                 pinctrl-0 = <&i2c2_xfer>;
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241                 status = "disabled";
 242         };
 243
 244         i2c3: i2c@ff130000 {
 245                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 246                 reg = <0x0 0xff130000 0x0 0x1000>;
 247                 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
 248                 clock-names = "i2c", "i2c_sclk";
 249                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&i2c3_xfer>;
 252                 #address-cells = <1>;
 253                 #size-cells = <0>;
 254                 status = "disabled";
 255         };
 256
 257         i2c5: i2c@ff140000 {
 258                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 259                 reg = <0x0 0xff140000 0x0 0x1000>;
 260                 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
 261                 clock-names = "i2c", "i2c_sclk";
 262                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 263                 pinctrl-names = "default";
 264                 pinctrl-0 = <&i2c5_xfer>;
 265                 #address-cells = <1>;
 266                 #size-cells = <0>;
 267                 status = "disabled";
 268         };
 269
 270         i2c6: i2c@ff150000 {
 271                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 272                 reg = <0x0 0xff150000 0x0 0x1000>;
 273                 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
 274                 clock-names = "i2c", "i2c_sclk";
 275                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&i2c6_xfer>;
 278                 #address-cells = <1>;
 279                 #size-cells = <0>;
 280                 status = "disabled";
 281         };
 282
 283         i2c7: i2c@ff160000 {
 284                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 285                 reg = <0x0 0xff160000 0x0 0x1000>;
 286                 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
 287                 clock-names = "i2c", "i2c_sclk";
 288                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 289                 pinctrl-names = "default";
 290                 pinctrl-0 = <&i2c7_xfer>;
 291                 #address-cells = <1>;
 292                 #size-cells = <0>;
 293                 status = "disabled";
 294         };
 295
 296         uart0: serial@ff180000 {
 297                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 298                 reg = <0x0 0xff180000 0x0 0x100>;
 299                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 300                 clock-names = "baudclk", "apb_pclk";
 301                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 302                 reg-shift = <2>;
 303                 reg-io-width = <4>;
 304                 status = "disabled";
 305         };
 306
 307         uart1: serial@ff190000 {
 308                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 309                 reg = <0x0 0xff190000 0x0 0x100>;
 310                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 311                 clock-names = "baudclk", "apb_pclk";
 312                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 313                 reg-shift = <2>;
 314                 reg-io-width = <4>;
 315                 status = "disabled";
 316         };
 317
 318         uart2: serial@ff1a0000 {
 319                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 320                 reg = <0x0 0xff1a0000 0x0 0x100>;
 321                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 322                 clock-names = "baudclk", "apb_pclk";
 323                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 324                 reg-shift = <2>;
 325                 reg-io-width = <4>;
 326                 status = "disabled";
 327         };
 328
 329         uart3: serial@ff1b0000 {
 330                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 331                 reg = <0x0 0xff1b0000 0x0 0x100>;
 332                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 333                 clock-names = "baudclk", "apb_pclk";
 334                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 335                 reg-shift = <2>;
 336                 reg-io-width = <4>;
 337                 status = "disabled";
 338         };
 339
 340         spi0: spi@ff1c0000 {
 341                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 342                 reg = <0x0 0xff110000 0x0 0x1000>;
 343                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 344                 clock-names = "spiclk", "apb_pclk";
 345                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 346                 pinctrl-names = "default";
 347                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350                 status = "disabled";
 351         };
 352
 353         spi1: spi@ff1d0000 {
 354                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 355                 reg = <0x0 0xff120000 0x0 0x1000>;
 356                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 357                 clock-names = "spiclk", "apb_pclk";
 358                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 status = "disabled";
 364         };
 365
 366         spi2: spi@ff1e0000 {
 367                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 368                 reg = <0x0 0xff130000 0x0 0x1000>;
 369                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 370                 clock-names = "spiclk", "apb_pclk";
 371                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 status = "disabled";
 377         };
 378
 379         spi4: spi@ff1f0000 {
 380                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 381                 reg = <0x0 0xff120000 0x0 0x1000>;
 382                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 383                 clock-names = "spiclk", "apb_pclk";
 384                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 status = "disabled";
 390         };
 391
 392         spi5: spi@ff200000 {
 393                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 394                 reg = <0x0 0xff130000 0x0 0x1000>;
 395                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 396                 clock-names = "spiclk", "apb_pclk";
 397                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 status = "disabled";
 403         };
 404
 405         thermal-zones {
 406                 #include "rk3368-thermal.dtsi"
 407         };
 408
 409         tsadc: tsadc@ff260000 {
 410                 compatible = "rockchip,rk3399-tsadc";
 411                 reg = <0x0 0xff260000 0x0 0x100>;
 412                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 413                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 414                 clock-names = "tsadc", "apb_pclk";
 415                 resets = <&cru SRST_TSADC>;
 416                 reset-names = "tsadc-apb";
 417                 pinctrl-names = "init", "default", "sleep";
 418                 pinctrl-0 = <&otp_gpio>;
 419                 pinctrl-1 = <&otp_out>;
 420                 pinctrl-2 = <&otp_gpio>;
 421                 #thermal-sensor-cells = <1>;
 422                 rockchip,hw-tshut-temp = <95000>;
 423                 status = "disabled";
 424         };
 425
 426         pmugrf: syscon@ff320000 {
 427                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 428                 reg = <0x0 0xff320000 0x0 0x1000>;
 429         };
 430
 431         spi3: spi@ff350000 {
 432                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 433                 reg = <0x0 0xff110000 0x0 0x1000>;
 434                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 435                 clock-names = "spiclk", "apb_pclk";
 436                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 439                 #address-cells = <1>;
 440                 #size-cells = <0>;
 441                 status = "disabled";
 442         };
 443
 444         uart4: serial@ff370000 {
 445                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 446                 reg = <0x0 0xff370000 0x0 0x100>;
 447                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 448                 clock-names = "baudclk", "apb_pclk";
 449                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 450                 reg-shift = <2>;
 451                 reg-io-width = <4>;
 452                 status = "disabled";
 453         };
 454
 455         i2c4: i2c@ff3d0000 {
 456                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 457                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 458                 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
 459                 clock-names = "i2c", "i2c_sclk";
 460                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&i2c4_xfer>;
 463                 #address-cells = <1>;
 464                 #size-cells = <0>;
 465                 status = "disabled";
 466         };
 467
 468         i2c8: i2c@ff3e0000 {
 469                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 470                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 471                 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
 472                 clock-names = "i2c", "i2c_sclk";
 473                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&i2c8_xfer>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 status = "disabled";
 479         };
 480
 481         pmucru: pmu-clock-controller@ff750000 {
 482                 compatible = "rockchip,rk3399-pmucru";
 483                 reg = <0x0 0xff750000 0x0 0x1000>;
 484                 rockchip,grf = <&pmugrf>;
 485                 #clock-cells = <1>;
 486                 #reset-cells = <1>;
 487         };
 488
 489         cru: clock-controller@ff760000 {
 490                 compatible = "rockchip,rk3399-cru";
 491                 reg = <0x0 0xff760000 0x0 0x1000>;
 492                 rockchip,grf = <&grf>;
 493                 #clock-cells = <1>;
 494                 #reset-cells = <1>;
 495         };
 496
 497         grf: syscon@ff770000 {
 498                 compatible = "rockchip,rk3399-grf", "syscon";
 499                 reg = <0x0 0xff770000 0x0 0x10000>;
 500         };
 501
 502         spdif: spdif@ff870000 {
 503                 compatible = "rockchip,rk3399-spdif";
 504                 reg = <0x0 0xff870000 0x0 0x1000>;
 505                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 506                 dmas = <&dmac_bus 7>;
 507                 dma-names = "tx";
 508                 clock-names = "hclk", "mclk";
 509                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 510                 pinctrl-names = "default";
 511                 pinctrl-0 = <&spdif_bus>;
 512                 status = "disabled";
 513         };
 514
 515         i2s0: i2s@ff880000 {
 516                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 517                 reg = <0x0 0xff880000 0x0 0x1000>;
 518                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 522                 dma-names = "tx", "rx";
 523                 clock-names = "i2s_hclk", "i2s_clk";
 524                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 525                 pinctrl-names = "default";
 526                 pinctrl-0 = <&i2s0_8ch_bus>;
 527                 status = "disabled";
 528         };
 529
 530         i2s1: i2s@ff890000 {
 531                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 532                 reg = <0x0 0xff890000 0x0 0x1000>;
 533                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 534                 #address-cells = <1>;
 535                 #size-cells = <0>;
 536                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 537                 dma-names = "tx", "rx";
 538                 clock-names = "i2s_hclk", "i2s_clk";
 539                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&i2s1_2ch_bus>;
 542                 status = "disabled";
 543         };
 544
 545         i2s2: i2s@ff8a0000 {
 546                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 547                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 548                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 549                 #address-cells = <1>;
 550                 #size-cells = <0>;
 551                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 552                 dma-names = "tx", "rx";
 553                 clock-names = "i2s_hclk", "i2s_clk";
 554                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 555                 status = "disabled";
 556         };
 557
 558         pinctrl: pinctrl {
 559                 compatible = "rockchip,rk3399-pinctrl";
 560                 rockchip,grf = <&grf>;
 561                 rockchip,pmu = <&pmugrf>;
 562                 #address-cells = <0x2>;
 563                 #size-cells = <0x2>;
 564                 ranges;
 565
 566                 gpio0: gpio0@ff720000 {
 567                         compatible = "rockchip,gpio-bank";
 568                         reg = <0x0 0xff720000 0x0 0x100>;
 569                         clocks = <&xin24m>;
 570                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 571
 572                         gpio-controller;
 573                         #gpio-cells = <0x2>;
 574
 575                         interrupt-controller;
 576                         #interrupt-cells = <0x2>;
 577                 };
 578
 579                 gpio1: gpio1@ff730000 {
 580                         compatible = "rockchip,gpio-bank";
 581                         reg = <0x0 0xff730000 0x0 0x100>;
 582                         clocks = <&xin24m>;
 583                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 584
 585                         gpio-controller;
 586                         #gpio-cells = <0x2>;
 587
 588                         interrupt-controller;
 589                         #interrupt-cells = <0x2>;
 590                 };
 591
 592                 gpio2: gpio2@ff780000 {
 593                         compatible = "rockchip,gpio-bank";
 594                         reg = <0x0 0xff780000 0x0 0x100>;
 595                         clocks = <&xin24m>;
 596                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 597
 598                         gpio-controller;
 599                         #gpio-cells = <0x2>;
 600
 601                         interrupt-controller;
 602                         #interrupt-cells = <0x2>;
 603                 };
 604
 605                 gpio3: gpio3@ff788000 {
 606                         compatible = "rockchip,gpio-bank";
 607                         reg = <0x0 0xff788000 0x0 0x100>;
 608                         clocks = <&xin24m>;
 609                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 610
 611                         gpio-controller;
 612                         #gpio-cells = <0x2>;
 613
 614                         interrupt-controller;
 615                         #interrupt-cells = <0x2>;
 616                 };
 617
 618                 gpio4: gpio4@ff790000 {
 619                         compatible = "rockchip,gpio-bank";
 620                         reg = <0x0 0xff790000 0x0 0x100>;
 621                         clocks = <&xin24m>;
 622                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 623
 624                         gpio-controller;
 625                         #gpio-cells = <0x2>;
 626
 627                         interrupt-controller;
 628                         #interrupt-cells = <0x2>;
 629                 };
 630
 631                 pcfg_pull_up: pcfg-pull-up {
 632                         bias-pull-up;
 633                 };
 634
 635                 pcfg_pull_down: pcfg-pull-down {
 636                         bias-pull-down;
 637                 };
 638
 639                 pcfg_pull_none: pcfg-pull-none {
 640                         bias-disable;
 641                 };
 642
 643                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 644                         bias-disable;
 645                         drive-strength = <12>;
 646                 };
 647
 648                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 649                         bias-pull-up;
 650                         drive-strength = <8>;
 651                 };
 652
 653                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 654                         bias-pull-down;
 655                         drive-strength = <4>;
 656                 };
 657
 658                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 659                         bias-pull-up;
 660                         drive-strength = <2>;
 661                 };
 662
 663                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 664                         bias-pull-down;
 665                         drive-strength = <12>;
 666                 };
 667
 668                 emmc {
 669                         emmc_pwr: emmc-pwr {
 670                                 rockchip,pins =
 671                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 672                         };
 673                 };
 674
 675                 gmac {
 676                         rgmii_pins: rgmii-pins {
 677                                 rockchip,pins =
 678                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 679                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 680                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 681                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 682                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 683                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 684                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 685                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 686                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 687                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 688                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 689                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 690                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 691                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 692                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 693                         };
 694
 695                         rmii_pins: rmii-pins {
 696                                 rockchip,pins =
 697                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 698                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 699                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 700                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 701                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 702                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 703                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 704                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 705                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 706                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 707                         };
 708                 };
 709
 710                 i2c0 {
 711                         i2c0_xfer: i2c0-xfer {
 712                                 rockchip,pins =
 713                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 714                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 715                         };
 716                 };
 717
 718                 i2c1 {
 719                         i2c1_xfer: i2c1-xfer {
 720                                 rockchip,pins =
 721                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 722                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 723                         };
 724                 };
 725
 726                 i2c2 {
 727                         i2c2_xfer: i2c2-xfer {
 728                                 rockchip,pins =
 729                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 730                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 731                         };
 732                 };
 733
 734                 i2c3 {
 735                         i2c3_xfer: i2c3-xfer {
 736                                 rockchip,pins =
 737                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 738                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 739                         };
 740                 };
 741
 742                 i2c4 {
 743                         i2c4_xfer: i2c4-xfer {
 744                                 rockchip,pins =
 745                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 746                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 747                         };
 748                 };
 749
 750                 i2c5 {
 751                         i2c5_xfer: i2c5-xfer {
 752                                 rockchip,pins =
 753                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 754                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 755                         };
 756                 };
 757
 758                 i2c6 {
 759                         i2c6_xfer: i2c6-xfer {
 760                                 rockchip,pins =
 761                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 762                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 763                         };
 764                 };
 765
 766                 i2c7 {
 767                         i2c7_xfer: i2c7-xfer {
 768                                 rockchip,pins =
 769                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 770                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 771                         };
 772                 };
 773
 774                 i2c8 {
 775                         i2c8_xfer: i2c8-xfer {
 776                                 rockchip,pins =
 777                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 778                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 779                         };
 780                 };
 781
 782                 i2s0 {
 783                         i2s0_8ch_bus: i2s0-8ch-bus {
 784                                 rockchip,pins =
 785                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 786                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 787                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 788                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 789                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 790                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 791                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 792                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 793                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 794                         };
 795                 };
 796
 797                 i2s1 {
 798                         i2s1_2ch_bus: i2s1-2ch-bus {
 799                                 rockchip,pins =
 800                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 801                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 802                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 803                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 804                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 805                         };
 806                 };
 807
 808                 sdio0 {
 809                         sdio0_bus1: sdio0-bus1 {
 810                                 rockchip,pins =
 811                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
 812                         };
 813
 814                         sdio0_bus4: sdio0-bus4 {
 815                                 rockchip,pins =
 816                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
 817                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
 818                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
 819                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
 820                         };
 821
 822                         sdio0_cmd: sdio0-cmd {
 823                                 rockchip,pins =
 824                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
 825                         };
 826
 827                         sdio0_clk: sdio0-clk {
 828                                 rockchip,pins =
 829                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 830                         };
 831
 832                         sdio0_cd: sdio0-cd {
 833                                 rockchip,pins =
 834                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
 835                         };
 836
 837                         sdio0_pwr: sdio0-pwr {
 838                                 rockchip,pins =
 839                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
 840                         };
 841
 842                         sdio0_bkpwr: sdio0-bkpwr {
 843                                 rockchip,pins =
 844                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
 845                         };
 846
 847                         sdio0_wp: sdio0-wp {
 848                                 rockchip,pins =
 849                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
 850                         };
 851
 852                         sdio0_int: sdio0-int {
 853                                 rockchip,pins =
 854                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
 855                         };
 856                 };
 857
 858                 sdmmc {
 859                         sdmmc_bus1: sdmmc-bus1 {
 860                                 rockchip,pins =
 861                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
 862                         };
 863
 864                         sdmmc_bus4: sdmmc-bus4 {
 865                                 rockchip,pins =
 866                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
 867                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
 868                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
 869                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
 870                         };
 871
 872                         sdmmc_clk: sdmmc-clk {
 873                                 rockchip,pins =
 874                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
 875                         };
 876
 877                         sdmmc_cmd: sdmmc-cmd {
 878                                 rockchip,pins =
 879                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
 880                         };
 881
 882                         sdmmc_cd: sdmcc-cd {
 883                                 rockchip,pins =
 884                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
 885                         };
 886
 887                         sdmmc_wp: sdmmc-wp {
 888                                 rockchip,pins =
 889                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
 890                         };
 891                 };
 892
 893                 spdif {
 894                         spdif_bus: spdif-bus {
 895                                 rockchip,pins =
 896                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
 897                         };
 898                 };
 899
 900                 spi0 {
 901                         spi0_clk: spi0-clk {
 902                                 rockchip,pins =
 903                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
 904                         };
 905                         spi0_cs0: spi0-cs0 {
 906                                 rockchip,pins =
 907                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
 908                         };
 909                         spi0_cs1: spi0-cs1 {
 910                                 rockchip,pins =
 911                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
 912                         };
 913                         spi0_tx: spi0-tx {
 914                                 rockchip,pins =
 915                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
 916                         };
 917                         spi0_rx: spi0-rx {
 918                                 rockchip,pins =
 919                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
 920                         };
 921                 };
 922
 923                 spi1 {
 924                         spi1_clk: spi1-clk {
 925                                 rockchip,pins =
 926                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
 927                         };
 928                         spi1_cs0: spi1-cs0 {
 929                                 rockchip,pins =
 930                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
 931                         };
 932                         spi1_rx: spi1-rx {
 933                                 rockchip,pins =
 934                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
 935                         };
 936                         spi1_tx: spi1-tx {
 937                                 rockchip,pins =
 938                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
 939                         };
 940                 };
 941
 942                 spi2 {
 943                         spi2_clk: spi2-clk {
 944                                 rockchip,pins =
 945                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 946                         };
 947                         spi2_cs0: spi2-cs0 {
 948                                 rockchip,pins =
 949                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 950                         };
 951                         spi2_rx: spi2-rx {
 952                                 rockchip,pins =
 953                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 954                         };
 955                         spi2_tx: spi2-tx {
 956                                 rockchip,pins =
 957                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 958                         };
 959                 };
 960
 961                 spi3 {
 962                         spi3_clk: spi3-clk {
 963                                 rockchip,pins =
 964                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
 965                         };
 966                         spi3_cs0: spi3-cs0 {
 967                                 rockchip,pins =
 968                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
 969                         };
 970                         spi3_rx: spi3-rx {
 971                                 rockchip,pins =
 972                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
 973                         };
 974                         spi3_tx: spi3-tx {
 975                                 rockchip,pins =
 976                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
 977                         };
 978                 };
 979
 980                 spi4 {
 981                         spi4_clk: spi4-clk {
 982                                 rockchip,pins =
 983                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
 984                         };
 985                         spi4_cs0: spi4-cs0 {
 986                                 rockchip,pins =
 987                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
 988                         };
 989                         spi4_rx: spi4-rx {
 990                                 rockchip,pins =
 991                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
 992                         };
 993                         spi4_tx: spi4-tx {
 994                                 rockchip,pins =
 995                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
 996                         };
 997                 };
 998
 999                 spi5 {
1000                         spi5_clk: spi5-clk {
1001                                 rockchip,pins =
1002                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1003                         };
1004                         spi5_cs0: spi5-cs0 {
1005                                 rockchip,pins =
1006                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1007                         };
1008                         spi5_rx: spi5-rx {
1009                                 rockchip,pins =
1010                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1011                         };
1012                         spi5_tx: spi5-tx {
1013                                 rockchip,pins =
1014                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1015                         };
1016                 };
1017
1018                 tsadc {
1019                         otp_gpio: otp-gpio {
1020                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1021                         };
1022
1023                         otp_out: otp-out {
1024                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1025                         };
1026                 };
1027
1028                 uart0 {
1029                         uart0_xfer: uart0-xfer {
1030                                 rockchip,pins =
1031                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1032                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1033                         };
1034
1035                         uart0_cts: uart0-cts {
1036                                 rockchip,pins =
1037                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1038                         };
1039
1040                         uart0_rts: uart0-rts {
1041                                 rockchip,pins =
1042                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1043                         };
1044                 };
1045
1046                 uart1 {
1047                         uart1_xfer: uart1-xfer {
1048                                 rockchip,pins =
1049                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1050                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1051                         };
1052                 };
1053
1054                 uart2a {
1055                         uart2a_xfer: uart2a-xfer {
1056                                 rockchip,pins =
1057                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1058                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1059                         };
1060                 };
1061
1062                 uart2b {
1063                         uart2b_xfer: uart2b-xfer {
1064                                 rockchip,pins =
1065                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1066                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1067                         };
1068                 };
1069
1070                 uart2c {
1071                         uart2c_xfer: uart2c-xfer {
1072                                 rockchip,pins =
1073                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1074                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1075                         };
1076                 };
1077
1078                 uart3 {
1079                         uart3_xfer: uart3-xfer {
1080                                 rockchip,pins =
1081                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1082                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1083                         };
1084
1085                         uart3_cts: uart3-cts {
1086                                 rockchip,pins =
1087                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1088                         };
1089
1090                         uart3_rts: uart3-rts {
1091                                 rockchip,pins =
1092                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1093                         };
1094                 };
1095
1096                 uart4 {
1097                         uart4_xfer: uart4-xfer {
1098                                 rockchip,pins =
1099                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1100                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1101                         };
1102                 };
1103
1104                 uarthdcp {
1105                         uarthdcp_xfer: uarthdcp-xfer {
1106                                 rockchip,pins =
1107                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1108                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1109                         };
1110                 };
1111
1112                 pwm0 {
1113                         pwm0_pin: pwm0-pin {
1114                                 rockchip,pins =
1115                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1116                         };
1117
1118                         vop0_pwm_pin: vop0-pwm-pin {
1119                                 rockchip,pins =
1120                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1121                         };
1122                 };
1123
1124                 pwm1 {
1125                         pwm1_pin: pwm1-pin {
1126                                 rockchip,pins =
1127                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1128                         };
1129
1130                         vop1_pwm_pin: vop1-pwm-pin {
1131                                 rockchip,pins =
1132                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1133                         };
1134                 };
1135         };
1136 };