2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3399";
55 interrupt-parent = <&gic>;
77 compatible = "arm,psci-1.0";
113 compatible = "arm,cortex-a53", "arm,armv8";
115 enable-method = "psci";
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <100>;
118 clocks = <&cru ARMCLKL>;
119 cpu-idle-states = <&cpu_sleep>;
120 operating-points-v2 = <&cluster0_opp>;
121 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 cpu-idle-states = <&cpu_sleep>;
131 operating-points-v2 = <&cluster0_opp>;
132 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 enable-method = "psci";
140 clocks = <&cru ARMCLKL>;
141 cpu-idle-states = <&cpu_sleep>;
142 operating-points-v2 = <&cluster0_opp>;
143 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 cpu-idle-states = <&cpu_sleep>;
153 operating-points-v2 = <&cluster0_opp>;
154 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
159 compatible = "arm,cortex-a72", "arm,armv8";
161 enable-method = "psci";
162 #cooling-cells = <2>; /* min followed by max */
163 dynamic-power-coefficient = <436>;
164 clocks = <&cru ARMCLKB>;
165 cpu-idle-states = <&cpu_sleep>;
166 operating-points-v2 = <&cluster1_opp>;
167 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
172 compatible = "arm,cortex-a72", "arm,armv8";
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 cpu-idle-states = <&cpu_sleep>;
177 operating-points-v2 = <&cluster1_opp>;
178 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
182 entry-method = "psci";
183 cpu_sleep: cpu-sleep-0 {
184 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x0010000>;
187 entry-latency-us = <350>;
188 exit-latency-us = <600>;
189 min-residency-us = <1150>;
193 /include/ "rk3399-sched-energy.dtsi"
197 cluster0_opp: opp_table0 {
198 compatible = "operating-points-v2";
202 opp-hz = /bits/ 64 <408000000>;
203 opp-microvolt = <800000>;
204 clock-latency-ns = <40000>;
207 opp-hz = /bits/ 64 <600000000>;
208 opp-microvolt = <800000>;
211 opp-hz = /bits/ 64 <816000000>;
212 opp-microvolt = <800000>;
215 opp-hz = /bits/ 64 <1008000000>;
216 opp-microvolt = <875000>;
219 opp-hz = /bits/ 64 <1200000000>;
220 opp-microvolt = <925000>;
223 opp-hz = /bits/ 64 <1416000000>;
224 opp-microvolt = <1025000>;
228 cluster1_opp: opp_table1 {
229 compatible = "operating-points-v2";
233 opp-hz = /bits/ 64 <408000000>;
234 opp-microvolt = <800000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <600000000>;
239 opp-microvolt = <800000>;
242 opp-hz = /bits/ 64 <816000000>;
243 opp-microvolt = <800000>;
246 opp-hz = /bits/ 64 <1008000000>;
247 opp-microvolt = <850000>;
250 opp-hz = /bits/ 64 <1200000000>;
251 opp-microvolt = <925000>;
256 compatible = "arm,armv8-timer";
257 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
258 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
259 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
260 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
264 compatible = "arm,cortex-a53-pmu";
265 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
269 compatible = "arm,cortex-a72-pmu";
270 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
274 compatible = "fixed-clock";
276 clock-frequency = <24000000>;
277 clock-output-names = "xin24m";
281 compatible = "arm,amba-bus";
282 #address-cells = <2>;
286 dmac_bus: dma-controller@ff6d0000 {
287 compatible = "arm,pl330", "arm,primecell";
288 reg = <0x0 0xff6d0000 0x0 0x4000>;
289 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
290 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
292 clocks = <&cru ACLK_DMAC0_PERILP>;
293 clock-names = "apb_pclk";
294 peripherals-req-type-burst;
297 dmac_peri: dma-controller@ff6e0000 {
298 compatible = "arm,pl330", "arm,primecell";
299 reg = <0x0 0xff6e0000 0x0 0x4000>;
300 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
301 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
303 clocks = <&cru ACLK_DMAC1_PERILP>;
304 clock-names = "apb_pclk";
305 peripherals-req-type-burst;
310 compatible = "rockchip,rk3399-gmac";
311 reg = <0x0 0xfe300000 0x0 0x10000>;
312 rockchip,grf = <&grf>;
313 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
314 interrupt-names = "macirq";
315 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
316 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
317 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
319 clock-names = "stmmaceth", "mac_clk_rx",
320 "mac_clk_tx", "clk_mac_ref",
321 "clk_mac_refout", "aclk_mac",
323 resets = <&cru SRST_A_GMAC>;
324 reset-names = "stmmaceth";
325 power-domains = <&power RK3399_PD_GMAC>;
330 compatible = "rockchip,rk3399-emmc-phy";
331 reg-offset = <0xf780>;
333 rockchip,grf = <&grf>;
334 ctrl-base = <0xfe330000>;
338 sdio0: dwmmc@fe310000 {
339 compatible = "rockchip,rk3399-dw-mshc",
340 "rockchip,rk3288-dw-mshc";
341 reg = <0x0 0xfe310000 0x0 0x4000>;
342 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
343 clock-freq-min-max = <400000 150000000>;
344 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
345 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
346 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
347 fifo-depth = <0x100>;
348 power-domains = <&power RK3399_PD_SDIOAUDIO>;
352 sdmmc: dwmmc@fe320000 {
353 compatible = "rockchip,rk3399-dw-mshc",
354 "rockchip,rk3288-dw-mshc";
355 reg = <0x0 0xfe320000 0x0 0x4000>;
356 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
357 clock-freq-min-max = <400000 150000000>;
358 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
359 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
360 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
361 fifo-depth = <0x100>;
362 power-domains = <&power RK3399_PD_SD>;
366 sdhci: sdhci@fe330000 {
367 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
368 reg = <0x0 0xfe330000 0x0 0x10000>;
369 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
370 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
371 clock-names = "clk_xin", "clk_ahb";
372 assigned-clocks = <&cru SCLK_EMMC>;
373 assigned-clock-parents = <&cru PLL_CPLL>;
374 assigned-clock-rates = <200000000>;
376 phy-names = "phy_arasan";
377 power-domains = <&power RK3399_PD_EMMC>;
381 usb_host0_ehci: usb@fe380000 {
382 compatible = "generic-ehci";
383 reg = <0x0 0xfe380000 0x0 0x20000>;
384 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
385 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
386 <&cru SCLK_USBPHY0_480M_SRC>;
387 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
388 phys = <&u2phy0_host>;
390 power-domains = <&power RK3399_PD_PERIHP>;
394 usb_host0_ohci: usb@fe3a0000 {
395 compatible = "generic-ohci";
396 reg = <0x0 0xfe3a0000 0x0 0x20000>;
397 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
398 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
399 <&cru SCLK_USBPHY0_480M_SRC>;
400 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
401 phys = <&u2phy0_host>;
403 power-domains = <&power RK3399_PD_PERIHP>;
407 usb_host1_ehci: usb@fe3c0000 {
408 compatible = "generic-ehci";
409 reg = <0x0 0xfe3c0000 0x0 0x20000>;
410 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
411 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
412 <&cru SCLK_USBPHY1_480M_SRC>;
413 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
414 phys = <&u2phy1_host>;
416 power-domains = <&power RK3399_PD_PERIHP>;
420 usb_host1_ohci: usb@fe3e0000 {
421 compatible = "generic-ohci";
422 reg = <0x0 0xfe3e0000 0x0 0x20000>;
423 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
424 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
425 <&cru SCLK_USBPHY1_480M_SRC>;
426 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
427 phys = <&u2phy1_host>;
429 power-domains = <&power RK3399_PD_PERIHP>;
433 usbdrd3_0: usb@fe800000 {
434 compatible = "rockchip,dwc3";
435 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
436 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
437 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
438 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
439 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
440 "aclk_usb3", "aclk_usb3_grf";
441 power-domains = <&power RK3399_PD_USB3>;
442 #address-cells = <2>;
446 usbdrd_dwc3_0: dwc3@fe800000 {
447 compatible = "snps,dwc3";
448 reg = <0x0 0xfe800000 0x0 0x100000>;
449 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
451 phys = <&u2phy0_otg>;
452 phy-names = "usb2-phy";
453 snps,dis_enblslpm_quirk;
454 snps,phyif_utmi_16_bits;
455 snps,dis_u2_freeclk_exists_quirk;
456 snps,dis_del_phy_power_chg_quirk;
457 snps,xhci_slow_suspend_quirk;
462 usbdrd3_1: usb@fe900000 {
463 compatible = "rockchip,dwc3";
464 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
465 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
466 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
467 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
468 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
469 "aclk_usb3", "aclk_usb3_grf";
470 power-domains = <&power RK3399_PD_USB3>;
471 #address-cells = <2>;
475 usbdrd_dwc3_1: dwc3@fe900000 {
476 compatible = "snps,dwc3";
477 reg = <0x0 0xfe900000 0x0 0x100000>;
478 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
480 phys = <&u2phy1_otg>;
481 phy-names = "usb2-phy";
482 snps,dis_enblslpm_quirk;
483 snps,phyif_utmi_16_bits;
484 snps,dis_u2_freeclk_exists_quirk;
485 snps,dis_del_phy_power_chg_quirk;
486 snps,xhci_slow_suspend_quirk;
491 gic: interrupt-controller@fee00000 {
492 compatible = "arm,gic-v3";
493 #interrupt-cells = <4>;
494 #address-cells = <2>;
497 interrupt-controller;
499 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
500 <0x0 0xfef00000 0 0xc0000>, /* GICR */
501 <0x0 0xfff00000 0 0x10000>, /* GICC */
502 <0x0 0xfff10000 0 0x10000>, /* GICH */
503 <0x0 0xfff20000 0 0x10000>; /* GICV */
504 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
505 its: interrupt-controller@fee20000 {
506 compatible = "arm,gic-v3-its";
508 reg = <0x0 0xfee20000 0x0 0x20000>;
512 part0: interrupt-partition-0 {
513 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
516 part1: interrupt-partition-1 {
517 affinity = <&cpu_b0 &cpu_b1>;
522 saradc: saradc@ff100000 {
523 compatible = "rockchip,rk3399-saradc";
524 reg = <0x0 0xff100000 0x0 0x100>;
525 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
526 #io-channel-cells = <1>;
527 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
528 clock-names = "saradc", "apb_pclk";
533 compatible = "rockchip,rk3399-i2c";
534 reg = <0x0 0xff3c0000 0x0 0x1000>;
535 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
536 clock-names = "i2c", "pclk";
537 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c0_xfer>;
540 #address-cells = <1>;
546 compatible = "rockchip,rk3399-i2c";
547 reg = <0x0 0xff110000 0x0 0x1000>;
548 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
549 clock-names = "i2c", "pclk";
550 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c1_xfer>;
553 #address-cells = <1>;
559 compatible = "rockchip,rk3399-i2c";
560 reg = <0x0 0xff120000 0x0 0x1000>;
561 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
562 clock-names = "i2c", "pclk";
563 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c2_xfer>;
566 #address-cells = <1>;
572 compatible = "rockchip,rk3399-i2c";
573 reg = <0x0 0xff130000 0x0 0x1000>;
574 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
575 clock-names = "i2c", "pclk";
576 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&i2c3_xfer>;
579 #address-cells = <1>;
585 compatible = "rockchip,rk3399-i2c";
586 reg = <0x0 0xff140000 0x0 0x1000>;
587 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
588 clock-names = "i2c", "pclk";
589 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&i2c5_xfer>;
592 #address-cells = <1>;
598 compatible = "rockchip,rk3399-i2c";
599 reg = <0x0 0xff150000 0x0 0x1000>;
600 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
601 clock-names = "i2c", "pclk";
602 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&i2c6_xfer>;
605 #address-cells = <1>;
611 compatible = "rockchip,rk3399-i2c";
612 reg = <0x0 0xff160000 0x0 0x1000>;
613 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
614 clock-names = "i2c", "pclk";
615 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&i2c7_xfer>;
618 #address-cells = <1>;
623 uart0: serial@ff180000 {
624 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
625 reg = <0x0 0xff180000 0x0 0x100>;
626 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
627 clock-names = "baudclk", "apb_pclk";
628 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
636 uart1: serial@ff190000 {
637 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
638 reg = <0x0 0xff190000 0x0 0x100>;
639 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
640 clock-names = "baudclk", "apb_pclk";
641 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&uart1_xfer>;
649 uart2: serial@ff1a0000 {
650 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
651 reg = <0x0 0xff1a0000 0x0 0x100>;
652 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
653 clock-names = "baudclk", "apb_pclk";
654 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&uart2c_xfer>;
662 uart3: serial@ff1b0000 {
663 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
664 reg = <0x0 0xff1b0000 0x0 0x100>;
665 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
666 clock-names = "baudclk", "apb_pclk";
667 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
676 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
677 reg = <0x0 0xff1c0000 0x0 0x1000>;
678 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
679 clock-names = "spiclk", "apb_pclk";
680 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
681 pinctrl-names = "default";
682 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
683 #address-cells = <1>;
689 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
690 reg = <0x0 0xff1d0000 0x0 0x1000>;
691 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
692 clock-names = "spiclk", "apb_pclk";
693 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
694 pinctrl-names = "default";
695 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
696 #address-cells = <1>;
702 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
703 reg = <0x0 0xff1e0000 0x0 0x1000>;
704 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
705 clock-names = "spiclk", "apb_pclk";
706 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
707 pinctrl-names = "default";
708 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
709 #address-cells = <1>;
715 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
716 reg = <0x0 0xff1f0000 0x0 0x1000>;
717 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
718 clock-names = "spiclk", "apb_pclk";
719 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
720 pinctrl-names = "default";
721 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
722 #address-cells = <1>;
728 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
729 reg = <0x0 0xff200000 0x0 0x1000>;
730 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
731 clock-names = "spiclk", "apb_pclk";
732 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
733 pinctrl-names = "default";
734 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
735 #address-cells = <1>;
741 soc_thermal: soc-thermal {
742 polling-delay-passive = <20>; /* milliseconds */
743 polling-delay = <1000>; /* milliseconds */
744 sustainable-power = <1000>; /* milliwatts */
746 thermal-sensors = <&tsadc 0>;
749 threshold: trip-point@0 {
750 temperature = <70000>; /* millicelsius */
751 hysteresis = <2000>; /* millicelsius */
754 target: trip-point@1 {
755 temperature = <85000>; /* millicelsius */
756 hysteresis = <2000>; /* millicelsius */
760 temperature = <95000>; /* millicelsius */
761 hysteresis = <2000>; /* millicelsius */
770 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
771 contribution = <4096>;
776 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
777 contribution = <1024>;
782 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
783 contribution = <4096>;
788 gpu_thermal: gpu-thermal {
789 polling-delay-passive = <100>; /* milliseconds */
790 polling-delay = <1000>; /* milliseconds */
792 thermal-sensors = <&tsadc 1>;
796 tsadc: tsadc@ff260000 {
797 compatible = "rockchip,rk3399-tsadc";
798 reg = <0x0 0xff260000 0x0 0x100>;
799 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
800 rockchip,grf = <&grf>;
801 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
802 clock-names = "tsadc", "apb_pclk";
803 assigned-clocks = <&cru SCLK_TSADC>;
804 assigned-clock-rates = <750000>;
805 resets = <&cru SRST_TSADC>;
806 reset-names = "tsadc-apb";
807 pinctrl-names = "init", "default", "sleep";
808 pinctrl-0 = <&otp_gpio>;
809 pinctrl-1 = <&otp_out>;
810 pinctrl-2 = <&otp_gpio>;
811 #thermal-sensor-cells = <1>;
812 rockchip,hw-tshut-temp = <95000>;
816 qos_emmc: qos@ffa58000 {
817 compatible = "syscon";
818 reg = <0x0 0xffa58000 0x0 0x20>;
821 qos_gmac: qos@ffa5c000 {
822 compatible = "syscon";
823 reg = <0x0 0xffa5c000 0x0 0x20>;
826 qos_pcie: qos@ffa60080 {
827 compatible = "syscon";
828 reg = <0x0 0xffa60080 0x0 0x20>;
831 qos_usb_host0: qos@ffa60100 {
832 compatible = "syscon";
833 reg = <0x0 0xffa60100 0x0 0x20>;
836 qos_usb_host1: qos@ffa60180 {
837 compatible = "syscon";
838 reg = <0x0 0xffa60180 0x0 0x20>;
841 qos_usb_otg0: qos@ffa70000 {
842 compatible = "syscon";
843 reg = <0x0 0xffa70000 0x0 0x20>;
846 qos_usb_otg1: qos@ffa70080 {
847 compatible = "syscon";
848 reg = <0x0 0xffa70080 0x0 0x20>;
851 qos_sd: qos@ffa74000 {
852 compatible = "syscon";
853 reg = <0x0 0xffa74000 0x0 0x20>;
856 qos_sdioaudio: qos@ffa76000 {
857 compatible = "syscon";
858 reg = <0x0 0xffa76000 0x0 0x20>;
861 qos_hdcp: qos@ffa90000 {
862 compatible = "syscon";
863 reg = <0x0 0xffa90000 0x0 0x20>;
866 qos_iep: qos@ffa98000 {
867 compatible = "syscon";
868 reg = <0x0 0xffa98000 0x0 0x20>;
871 qos_isp0_m0: qos@ffaa0000 {
872 compatible = "syscon";
873 reg = <0x0 0xffaa0000 0x0 0x20>;
876 qos_isp0_m1: qos@ffaa0080 {
877 compatible = "syscon";
878 reg = <0x0 0xffaa0080 0x0 0x20>;
881 qos_isp1_m0: qos@ffaa8000 {
882 compatible = "syscon";
883 reg = <0x0 0xffaa8000 0x0 0x20>;
886 qos_isp1_m1: qos@ffaa8080 {
887 compatible = "syscon";
888 reg = <0x0 0xffaa8080 0x0 0x20>;
891 qos_rga_r: qos@ffab0000 {
892 compatible = "syscon";
893 reg = <0x0 0xffab0000 0x0 0x20>;
896 qos_rga_w: qos@ffab0080 {
897 compatible = "syscon";
898 reg = <0x0 0xffab0080 0x0 0x20>;
901 qos_video_m0: qos@ffab8000 {
902 compatible = "syscon";
903 reg = <0x0 0xffab8000 0x0 0x20>;
906 qos_video_m1_r: qos@ffac0000 {
907 compatible = "syscon";
908 reg = <0x0 0xffac0000 0x0 0x20>;
911 qos_video_m1_w: qos@ffac0080 {
912 compatible = "syscon";
913 reg = <0x0 0xffac0080 0x0 0x20>;
916 qos_vop_big_r: qos@ffac8000 {
917 compatible = "syscon";
918 reg = <0x0 0xffac8000 0x0 0x20>;
921 qos_vop_big_w: qos@ffac8080 {
922 compatible = "syscon";
923 reg = <0x0 0xffac8080 0x0 0x20>;
926 qos_vop_little: qos@ffad0000 {
927 compatible = "syscon";
928 reg = <0x0 0xffad0000 0x0 0x20>;
931 qos_perihp: qos@ffad8080 {
932 compatible = "syscon";
933 reg = <0x0 0xffad8080 0x0 0x20>;
936 qos_gpu: qos@ffae0000 {
937 compatible = "syscon";
938 reg = <0x0 0xffae0000 0x0 0x20>;
941 pmu: power-management@ff310000 {
942 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
943 reg = <0x0 0xff310000 0x0 0x1000>;
946 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
947 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
948 * Some of the power domains are grouped together for every
950 * The detail contents as below.
952 power: power-controller {
953 compatible = "rockchip,rk3399-power-controller";
954 #power-domain-cells = <1>;
955 #address-cells = <1>;
958 /* These power domains are grouped by VD_CENTER */
959 pd_iep@RK3399_PD_IEP {
960 reg = <RK3399_PD_IEP>;
961 clocks = <&cru ACLK_IEP>,
965 pd_rga@RK3399_PD_RGA {
966 reg = <RK3399_PD_RGA>;
967 clocks = <&cru ACLK_RGA>,
969 pm_qos = <&qos_rga_r>,
972 pd_vcodec@RK3399_PD_VCODEC {
973 reg = <RK3399_PD_VCODEC>;
974 clocks = <&cru ACLK_VCODEC>,
976 pm_qos = <&qos_video_m0>;
978 pd_vdu@RK3399_PD_VDU {
979 reg = <RK3399_PD_VDU>;
980 clocks = <&cru ACLK_VDU>,
982 pm_qos = <&qos_video_m1_r>,
986 /* These power domains are grouped by VD_GPU */
987 pd_gpu@RK3399_PD_GPU {
988 reg = <RK3399_PD_GPU>;
989 clocks = <&cru ACLK_GPU>;
993 /* These power domains are grouped by VD_LOGIC */
994 pd_emmc@RK3399_PD_EMMC {
995 reg = <RK3399_PD_EMMC>;
996 clocks = <&cru ACLK_EMMC>;
997 pm_qos = <&qos_emmc>;
999 pd_gmac@RK3399_PD_GMAC {
1000 reg = <RK3399_PD_GMAC>;
1001 clocks = <&cru ACLK_GMAC>;
1002 pm_qos = <&qos_gmac>;
1004 pd_perihp@RK3399_PD_PERIHP {
1005 reg = <RK3399_PD_PERIHP>;
1006 #address-cells = <1>;
1008 clocks = <&cru ACLK_PERIHP>;
1009 pm_qos = <&qos_perihp>,
1014 pd_sd@RK3399_PD_SD {
1015 reg = <RK3399_PD_SD>;
1016 clocks = <&cru HCLK_SDMMC>,
1021 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1022 reg = <RK3399_PD_SDIOAUDIO>;
1023 clocks = <&cru HCLK_SDIO>;
1024 pm_qos = <&qos_sdioaudio>;
1026 pd_usb3@RK3399_PD_USB3 {
1027 reg = <RK3399_PD_USB3>;
1028 clocks = <&cru ACLK_USB3>;
1029 pm_qos = <&qos_usb_otg0>,
1032 pd_vio@RK3399_PD_VIO {
1033 reg = <RK3399_PD_VIO>;
1034 #address-cells = <1>;
1037 pd_hdcp@RK3399_PD_HDCP {
1038 reg = <RK3399_PD_HDCP>;
1039 clocks = <&cru ACLK_HDCP>,
1042 pm_qos = <&qos_hdcp>;
1044 pd_isp0@RK3399_PD_ISP0 {
1045 reg = <RK3399_PD_ISP0>;
1046 clocks = <&cru ACLK_ISP0>,
1048 pm_qos = <&qos_isp0_m0>,
1051 pd_isp1@RK3399_PD_ISP1 {
1052 reg = <RK3399_PD_ISP1>;
1053 clocks = <&cru ACLK_ISP1>,
1055 pm_qos = <&qos_isp1_m0>,
1058 pd_vo@RK3399_PD_VO {
1059 reg = <RK3399_PD_VO>;
1060 #address-cells = <1>;
1063 pd_vopb@RK3399_PD_VOPB {
1064 reg = <RK3399_PD_VOPB>;
1065 clocks = <&cru ACLK_VOP0>,
1067 pm_qos = <&qos_vop_big_r>,
1070 pd_vopl@RK3399_PD_VOPL {
1071 reg = <RK3399_PD_VOPL>;
1072 clocks = <&cru ACLK_VOP1>,
1074 pm_qos = <&qos_vop_little>;
1081 pmugrf: syscon@ff320000 {
1082 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1083 reg = <0x0 0xff320000 0x0 0x1000>;
1086 compatible = "syscon-reboot-mode";
1088 mode-bootloader = <BOOT_LOADER>;
1089 mode-charge = <BOOT_CHARGING>;
1090 mode-fastboot = <BOOT_FASTBOOT>;
1091 mode-loader = <BOOT_LOADER>;
1092 mode-normal = <BOOT_NORMAL>;
1093 mode-recovery = <BOOT_RECOVERY>;
1097 spi3: spi@ff350000 {
1098 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1099 reg = <0x0 0xff350000 0x0 0x1000>;
1100 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1101 clock-names = "spiclk", "apb_pclk";
1102 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1103 pinctrl-names = "default";
1104 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1105 #address-cells = <1>;
1107 status = "disabled";
1110 uart4: serial@ff370000 {
1111 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1112 reg = <0x0 0xff370000 0x0 0x100>;
1113 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1114 clock-names = "baudclk", "apb_pclk";
1115 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&uart4_xfer>;
1120 status = "disabled";
1123 i2c4: i2c@ff3d0000 {
1124 compatible = "rockchip,rk3399-i2c";
1125 reg = <0x0 0xff3d0000 0x0 0x1000>;
1126 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1127 clock-names = "i2c", "pclk";
1128 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&i2c4_xfer>;
1131 #address-cells = <1>;
1133 status = "disabled";
1136 i2c8: i2c@ff3e0000 {
1137 compatible = "rockchip,rk3399-i2c";
1138 reg = <0x0 0xff3e0000 0x0 0x1000>;
1139 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1140 clock-names = "i2c", "pclk";
1141 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1142 pinctrl-names = "default";
1143 pinctrl-0 = <&i2c8_xfer>;
1144 #address-cells = <1>;
1146 status = "disabled";
1149 pcie0: pcie@f8000000 {
1150 compatible = "rockchip,rk3399-pcie";
1151 #address-cells = <3>;
1153 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1154 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1155 clock-names = "aclk_pcie", "aclk_perf_pcie",
1156 "hclk_pcie", "clk_pciephy_ref";
1157 bus-range = <0x0 0x1>;
1158 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1159 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1160 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1161 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1162 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1163 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1164 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1165 < 0x0 0xfd000000 0x0 0x1000000 >;
1166 reg-name = "axi-base", "apb-base";
1167 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1168 <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1169 <&cru SRST_PCIE_PIPE>;
1170 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1171 "mgmt-sticky-rst", "pipe-rst";
1172 rockchip,grf = <&grf>;
1173 pcie-conf = <0xe220>;
1174 pcie-status = <0xe2a4>;
1175 pcie-laneoff = <0xe214>;
1176 power-domains = <&power RK3399_PD_PERIHP>;
1177 msi-parent = <&its>;
1178 #interrupt-cells = <1>;
1179 interrupt-map-mask = <0 0 0 7>;
1180 interrupt-map = <0 0 0 1 &pcie0 1>,
1184 status = "disabled";
1185 pcie_intc: interrupt-controller {
1186 interrupt-controller;
1187 #address-cells = <0>;
1188 #interrupt-cells = <1>;
1192 pwm0: pwm@ff420000 {
1193 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1194 reg = <0x0 0xff420000 0x0 0x10>;
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&pwm0_pin>;
1198 clocks = <&pmucru PCLK_RKPWM_PMU>;
1199 clock-names = "pwm";
1200 status = "disabled";
1203 pwm1: pwm@ff420010 {
1204 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1205 reg = <0x0 0xff420010 0x0 0x10>;
1207 pinctrl-names = "default";
1208 pinctrl-0 = <&pwm1_pin>;
1209 clocks = <&pmucru PCLK_RKPWM_PMU>;
1210 clock-names = "pwm";
1211 status = "disabled";
1214 pwm2: pwm@ff420020 {
1215 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1216 reg = <0x0 0xff420020 0x0 0x10>;
1218 pinctrl-names = "default";
1219 pinctrl-0 = <&pwm2_pin>;
1220 clocks = <&pmucru PCLK_RKPWM_PMU>;
1221 clock-names = "pwm";
1222 status = "disabled";
1225 pwm3: pwm@ff420030 {
1226 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1227 reg = <0x0 0xff420030 0x0 0x10>;
1229 pinctrl-names = "default";
1230 pinctrl-0 = <&pwm3a_pin>;
1231 clocks = <&pmucru PCLK_RKPWM_PMU>;
1232 clock-names = "pwm";
1233 status = "disabled";
1237 compatible = "rockchip,rk3399-rga";
1238 reg = <0x0 0xff680000 0x0 0x10000>;
1239 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1240 interrupt-names = "rga";
1241 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1242 clock-names = "aclk", "hclk", "sclk";
1243 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1244 reset-names = "core", "axi", "ahb";
1245 power-domains = <&power RK3399_PD_RGA>;
1246 status = "disabled";
1249 pmucru: pmu-clock-controller@ff750000 {
1250 compatible = "rockchip,rk3399-pmucru";
1251 reg = <0x0 0xff750000 0x0 0x1000>;
1254 assigned-clocks = <&pmucru PLL_PPLL>;
1255 assigned-clock-rates = <676000000>;
1258 cru: clock-controller@ff760000 {
1259 compatible = "rockchip,rk3399-cru";
1260 reg = <0x0 0xff760000 0x0 0x1000>;
1264 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1265 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1266 <&cru ARMCLKL>, <&cru ARMCLKB>,
1267 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1269 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1271 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1272 <&cru PCLK_PERILP0>,
1273 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1274 assigned-clock-rates =
1275 <400000000>, <200000000>,
1276 <400000000>, <200000000>,
1277 <816000000>, <816000000>,
1278 <594000000>, <800000000>,
1280 <150000000>, <75000000>,
1282 <100000000>, <100000000>,
1284 <100000000>, <50000000>;
1287 grf: syscon@ff770000 {
1288 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1289 reg = <0x0 0xff770000 0x0 0x10000>;
1290 #address-cells = <1>;
1293 u2phy0: usb2-phy@e450 {
1294 compatible = "rockchip,rk3399-usb2phy";
1295 reg = <0xe450 0x10>;
1296 clocks = <&cru SCLK_USB2PHY0_REF>;
1297 clock-names = "phyclk";
1299 clock-output-names = "clk_usbphy0_480m";
1300 status = "disabled";
1302 u2phy0_otg: otg-port {
1304 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1305 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1306 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1307 interrupt-names = "otg-bvalid", "otg-id",
1309 status = "disabled";
1312 u2phy0_host: host-port {
1314 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1315 interrupt-names = "linestate";
1316 status = "disabled";
1320 u2phy1: usb2-phy@e460 {
1321 compatible = "rockchip,rk3399-usb2phy";
1322 reg = <0xe460 0x10>;
1323 clocks = <&cru SCLK_USB2PHY1_REF>;
1324 clock-names = "phyclk";
1326 clock-output-names = "clk_usbphy1_480m";
1327 status = "disabled";
1329 u2phy1_otg: otg-port {
1331 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1334 interrupt-names = "otg-bvalid", "otg-id",
1336 status = "disabled";
1339 u2phy1_host: host-port {
1341 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1342 interrupt-names = "linestate";
1343 status = "disabled";
1348 tcphy0: phy@ff7c0000 {
1349 compatible = "rockchip,rk3399-typec-phy";
1350 reg = <0x0 0xff7c0000 0x0 0x40000>;
1351 rockchip,grf = <&grf>;
1353 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1354 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1355 clock-names = "tcpdcore", "tcpdphy-ref";
1356 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1357 assigned-clock-rates = <50000000>;
1358 resets = <&cru SRST_UPHY0>,
1359 <&cru SRST_UPHY0_PIPE_L00>,
1360 <&cru SRST_P_UPHY0_TCPHY>;
1361 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1362 rockchip,typec-conn-dir = <0xe580 0 16>;
1363 rockchip,usb3tousb2-en = <0xe580 3 19>;
1364 rockchip,external-psm = <0xe588 14 30>;
1365 rockchip,pipe-status = <0xe5c0 0 0>;
1366 rockchip,uphy-dp-sel = <0x6268 19 19>;
1367 status = "disabled";
1370 tcphy1: phy@ff800000 {
1371 compatible = "rockchip,rk3399-typec-phy";
1372 reg = <0x0 0xff800000 0x0 0x40000>;
1373 rockchip,grf = <&grf>;
1375 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1376 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1377 clock-names = "tcpdcore", "tcpdphy-ref";
1378 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1379 assigned-clock-rates = <50000000>;
1380 resets = <&cru SRST_UPHY1>,
1381 <&cru SRST_UPHY1_PIPE_L00>,
1382 <&cru SRST_P_UPHY1_TCPHY>;
1383 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1384 rockchip,typec-conn-dir = <0xe58c 0 16>;
1385 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1386 rockchip,external-psm = <0xe594 14 30>;
1387 rockchip,pipe-status = <0xe5c0 16 16>;
1388 rockchip,uphy-dp-sel = <0x6268 3 19>;
1389 status = "disabled";
1393 compatible = "snps,dw-wdt";
1394 reg = <0x0 0xff840000 0x0 0x100>;
1395 clocks = <&cru PCLK_WDT>;
1396 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1399 rktimer: rktimer@ff850000 {
1400 compatible = "rockchip,rk3399-timer";
1401 reg = <0x0 0xff850000 0x0 0x1000>;
1402 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1403 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1404 clock-names = "pclk", "timer";
1407 spdif: spdif@ff870000 {
1408 compatible = "rockchip,rk3399-spdif";
1409 reg = <0x0 0xff870000 0x0 0x1000>;
1410 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1411 dmas = <&dmac_bus 7>;
1413 clock-names = "mclk", "hclk";
1414 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&spdif_bus>;
1417 status = "disabled";
1420 i2s0: i2s@ff880000 {
1421 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1422 reg = <0x0 0xff880000 0x0 0x1000>;
1423 rockchip,grf = <&grf>;
1424 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1425 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1426 dma-names = "tx", "rx";
1427 clock-names = "i2s_clk", "i2s_hclk";
1428 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1429 pinctrl-names = "default";
1430 pinctrl-0 = <&i2s0_8ch_bus>;
1431 status = "disabled";
1434 i2s1: i2s@ff890000 {
1435 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1436 reg = <0x0 0xff890000 0x0 0x1000>;
1437 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1438 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1439 dma-names = "tx", "rx";
1440 clock-names = "i2s_clk", "i2s_hclk";
1441 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1442 pinctrl-names = "default";
1443 pinctrl-0 = <&i2s1_2ch_bus>;
1444 status = "disabled";
1447 i2s2: i2s@ff8a0000 {
1448 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1449 reg = <0x0 0xff8a0000 0x0 0x1000>;
1450 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1451 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1452 dma-names = "tx", "rx";
1453 clock-names = "i2s_clk", "i2s_hclk";
1454 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1455 status = "disabled";
1459 compatible = "arm,malit860",
1464 reg = <0x0 0xff9a0000 0x0 0x10000>;
1466 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1467 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1468 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1469 interrupt-names = "GPU", "JOB", "MMU";
1471 clocks = <&cru ACLK_GPU>;
1472 clock-names = "clk_mali";
1473 #cooling-cells = <2>; /* min followed by max */
1474 operating-points-v2 = <&gpu_opp_table>;
1475 power-domains = <&power RK3399_PD_GPU>;
1476 power-off-delay-ms = <200>;
1477 status = "disabled";
1479 gpu_power_model: power_model {
1480 compatible = "arm,mali-simple-power-model";
1483 static-power = <300>;
1484 dynamic-power = <396>;
1485 ts = <32000 4700 (-80) 2>;
1486 thermal-zone = "gpu-thermal";
1490 gpu_opp_table: gpu_opp_table {
1491 compatible = "operating-points-v2";
1495 opp-hz = /bits/ 64 <200000000>;
1496 opp-microvolt = <900000>;
1499 opp-hz = /bits/ 64 <300000000>;
1500 opp-microvolt = <900000>;
1503 opp-hz = /bits/ 64 <400000000>;
1504 opp-microvolt = <900000>;
1509 vopl: vop@ff8f0000 {
1510 compatible = "rockchip,rk3399-vop-lit";
1511 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1512 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1513 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1514 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1515 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1516 reset-names = "axi", "ahb", "dclk";
1517 power-domains = <&power RK3399_PD_VOPL>;
1518 iommus = <&vopl_mmu>;
1519 status = "disabled";
1522 #address-cells = <1>;
1525 vopl_out_mipi: endpoint@0 {
1527 remote-endpoint = <&mipi_in_vopl>;
1530 vopl_out_edp: endpoint@1 {
1532 remote-endpoint = <&edp_in_vopl>;
1535 vopl_out_hdmi: endpoint@2 {
1537 remote-endpoint = <&hdmi_in_vopl>;
1542 vop1_pwm: voppwm@ff8f01a0 {
1543 compatible = "rockchip,vop-pwm";
1544 reg = <0x0 0xff8f01a0 0x0 0x10>;
1546 pinctrl-names = "default";
1547 pinctrl-0 = <&vop1_pwm_pin>;
1548 clocks = <&cru SCLK_VOP1_PWM>;
1549 clock-names = "pwm";
1550 status = "disabled";
1553 vopl_mmu: iommu@ff8f3f00 {
1554 compatible = "rockchip,iommu";
1555 reg = <0x0 0xff8f3f00 0x0 0x100>;
1556 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1557 interrupt-names = "vopl_mmu";
1559 status = "disabled";
1562 vopb: vop@ff900000 {
1563 compatible = "rockchip,rk3399-vop-big";
1564 reg = <0x0 0xff900000 0x0 0x3efc>;
1565 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1566 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1567 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1568 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1569 reset-names = "axi", "ahb", "dclk";
1570 power-domains = <&power RK3399_PD_VOPB>;
1571 iommus = <&vopb_mmu>;
1572 status = "disabled";
1575 #address-cells = <1>;
1578 vopb_out_edp: endpoint@0 {
1580 remote-endpoint = <&edp_in_vopb>;
1583 vopb_out_mipi: endpoint@1 {
1585 remote-endpoint = <&mipi_in_vopb>;
1588 vopb_out_hdmi: endpoint@2 {
1590 remote-endpoint = <&hdmi_in_vopb>;
1595 vop0_pwm: voppwm@ff9001a0 {
1596 compatible = "rockchip,vop-pwm";
1597 reg = <0x0 0xff9001a0 0x0 0x10>;
1599 pinctrl-names = "default";
1600 pinctrl-0 = <&vop0_pwm_pin>;
1601 clocks = <&cru SCLK_VOP0_PWM>;
1602 clock-names = "pwm";
1603 status = "disabled";
1606 vopb_mmu: iommu@ff903f00 {
1607 compatible = "rockchip,iommu";
1608 reg = <0x0 0xff903f00 0x0 0x100>;
1609 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1610 interrupt-names = "vopb_mmu";
1612 status = "disabled";
1615 hdmi: hdmi@ff940000 {
1616 compatible = "rockchip,rk3399-dw-hdmi";
1617 reg = <0x0 0xff940000 0x0 0x20000>;
1619 rockchip,grf = <&grf>;
1620 power-domains = <&power RK3399_PD_HDCP>;
1621 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1622 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1623 clock-names = "iahb", "isfr", "vpll", "grf";
1624 status = "disabled";
1628 #address-cells = <1>;
1630 hdmi_in_vopb: endpoint@0 {
1632 remote-endpoint = <&vopb_out_hdmi>;
1634 hdmi_in_vopl: endpoint@1 {
1636 remote-endpoint = <&vopl_out_hdmi>;
1642 mipi_dsi: mipi@ff960000 {
1643 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1644 reg = <0x0 0xff960000 0x0 0x8000>;
1645 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1646 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1647 <&cru SCLK_DPHY_TX0_CFG>;
1648 clock-names = "ref", "pclk", "phy_cfg";
1649 power-domains = <&power RK3399_PD_VIO>;
1650 rockchip,grf = <&grf>;
1651 #address-cells = <1>;
1653 status = "disabled";
1656 #address-cells = <1>;
1661 #address-cells = <1>;
1664 mipi_in_vopb: endpoint@0 {
1666 remote-endpoint = <&vopb_out_mipi>;
1668 mipi_in_vopl: endpoint@1 {
1670 remote-endpoint = <&vopl_out_mipi>;
1677 compatible = "rockchip,rk3399-edp";
1678 reg = <0x0 0xff970000 0x0 0x8000>;
1679 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1680 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1681 clock-names = "dp", "pclk";
1682 resets = <&cru SRST_P_EDP_CTRL>;
1684 rockchip,grf = <&grf>;
1685 status = "disabled";
1686 pinctrl-names = "default";
1687 pinctrl-0 = <&edp_hpd>;
1690 #address-cells = <1>;
1695 #address-cells = <1>;
1698 edp_in_vopb: endpoint@0 {
1700 remote-endpoint = <&vopb_out_edp>;
1703 edp_in_vopl: endpoint@1 {
1705 remote-endpoint = <&vopl_out_edp>;
1711 display_subsystem: display-subsystem {
1712 compatible = "rockchip,display-subsystem";
1713 ports = <&vopl_out>, <&vopb_out>;
1714 status = "disabled";
1718 compatible = "rockchip,rk3399-pinctrl";
1719 rockchip,grf = <&grf>;
1720 rockchip,pmu = <&pmugrf>;
1721 #address-cells = <0x2>;
1722 #size-cells = <0x2>;
1725 gpio0: gpio0@ff720000 {
1726 compatible = "rockchip,gpio-bank";
1727 reg = <0x0 0xff720000 0x0 0x100>;
1728 clocks = <&pmucru PCLK_GPIO0_PMU>;
1729 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1732 #gpio-cells = <0x2>;
1734 interrupt-controller;
1735 #interrupt-cells = <0x2>;
1738 gpio1: gpio1@ff730000 {
1739 compatible = "rockchip,gpio-bank";
1740 reg = <0x0 0xff730000 0x0 0x100>;
1741 clocks = <&pmucru PCLK_GPIO1_PMU>;
1742 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1745 #gpio-cells = <0x2>;
1747 interrupt-controller;
1748 #interrupt-cells = <0x2>;
1751 gpio2: gpio2@ff780000 {
1752 compatible = "rockchip,gpio-bank";
1753 reg = <0x0 0xff780000 0x0 0x100>;
1754 clocks = <&cru PCLK_GPIO2>;
1755 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1758 #gpio-cells = <0x2>;
1760 interrupt-controller;
1761 #interrupt-cells = <0x2>;
1764 gpio3: gpio3@ff788000 {
1765 compatible = "rockchip,gpio-bank";
1766 reg = <0x0 0xff788000 0x0 0x100>;
1767 clocks = <&cru PCLK_GPIO3>;
1768 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1771 #gpio-cells = <0x2>;
1773 interrupt-controller;
1774 #interrupt-cells = <0x2>;
1777 gpio4: gpio4@ff790000 {
1778 compatible = "rockchip,gpio-bank";
1779 reg = <0x0 0xff790000 0x0 0x100>;
1780 clocks = <&cru PCLK_GPIO4>;
1781 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1784 #gpio-cells = <0x2>;
1786 interrupt-controller;
1787 #interrupt-cells = <0x2>;
1790 pcfg_pull_up: pcfg-pull-up {
1794 pcfg_pull_down: pcfg-pull-down {
1798 pcfg_pull_none: pcfg-pull-none {
1802 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1804 drive-strength = <20>;
1807 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1809 drive-strength = <20>;
1812 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1814 drive-strength = <18>;
1817 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1819 drive-strength = <12>;
1822 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1824 drive-strength = <8>;
1827 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1829 drive-strength = <4>;
1832 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1834 drive-strength = <2>;
1837 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1839 drive-strength = <12>;
1842 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1844 drive-strength = <13>;
1848 emmc_pwr: emmc-pwr {
1850 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1855 rgmii_pins: rgmii-pins {
1858 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1860 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1862 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1864 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1866 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1868 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1870 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1872 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1874 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1876 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1878 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1880 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1882 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1884 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1886 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1889 rmii_pins: rmii-pins {
1892 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1894 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1896 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1898 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1900 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1902 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1904 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1906 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1908 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1910 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1915 i2c0_xfer: i2c0-xfer {
1917 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1918 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1923 i2c1_xfer: i2c1-xfer {
1925 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1926 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1931 i2c2_xfer: i2c2-xfer {
1933 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1934 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1939 i2c3_xfer: i2c3-xfer {
1941 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1942 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1945 i2c3_gpio: i2c3_gpio {
1947 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1948 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1954 i2c4_xfer: i2c4-xfer {
1956 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1957 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1962 i2c5_xfer: i2c5-xfer {
1964 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1965 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1970 i2c6_xfer: i2c6-xfer {
1972 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1973 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1978 i2c7_xfer: i2c7-xfer {
1980 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1981 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1986 i2c8_xfer: i2c8-xfer {
1988 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1989 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1994 i2s0_8ch_bus: i2s0-8ch-bus {
1996 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1997 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1998 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1999 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2000 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2001 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2002 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2003 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2004 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2009 i2s1_2ch_bus: i2s1-2ch-bus {
2011 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2012 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2013 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2014 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2015 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2020 sdio0_bus1: sdio0-bus1 {
2022 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2025 sdio0_bus4: sdio0-bus4 {
2027 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2028 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2029 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2030 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2033 sdio0_cmd: sdio0-cmd {
2035 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2038 sdio0_clk: sdio0-clk {
2040 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2043 sdio0_cd: sdio0-cd {
2045 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2048 sdio0_pwr: sdio0-pwr {
2050 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2053 sdio0_bkpwr: sdio0-bkpwr {
2055 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2058 sdio0_wp: sdio0-wp {
2060 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2063 sdio0_int: sdio0-int {
2065 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2070 sdmmc_bus1: sdmmc-bus1 {
2072 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2075 sdmmc_bus4: sdmmc-bus4 {
2077 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2078 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2079 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2080 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2083 sdmmc_clk: sdmmc-clk {
2085 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2088 sdmmc_cmd: sdmmc-cmd {
2090 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2093 sdmmc_cd: sdmcc-cd {
2095 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2098 sdmmc_wp: sdmmc-wp {
2100 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2105 spdif_bus: spdif-bus {
2107 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2110 spdif_bus_1: spdif-bus-1 {
2112 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2117 spi0_clk: spi0-clk {
2119 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2121 spi0_cs0: spi0-cs0 {
2123 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2125 spi0_cs1: spi0-cs1 {
2127 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2131 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2135 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2140 spi1_clk: spi1-clk {
2142 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2144 spi1_cs0: spi1-cs0 {
2146 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2150 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2154 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2159 spi2_clk: spi2-clk {
2161 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2163 spi2_cs0: spi2-cs0 {
2165 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2169 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2173 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2178 spi3_clk: spi3-clk {
2180 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2182 spi3_cs0: spi3-cs0 {
2184 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2188 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2192 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2197 spi4_clk: spi4-clk {
2199 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2201 spi4_cs0: spi4-cs0 {
2203 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2207 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2211 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2216 spi5_clk: spi5-clk {
2218 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2220 spi5_cs0: spi5-cs0 {
2222 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2226 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2230 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2235 otp_gpio: otp-gpio {
2236 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2240 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2245 uart0_xfer: uart0-xfer {
2247 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2248 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2251 uart0_cts: uart0-cts {
2253 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2256 uart0_rts: uart0-rts {
2258 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2263 uart1_xfer: uart1-xfer {
2265 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2266 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2271 uart2a_xfer: uart2a-xfer {
2273 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2274 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2279 uart2b_xfer: uart2b-xfer {
2281 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2282 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2287 uart2c_xfer: uart2c-xfer {
2289 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2290 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2295 uart3_xfer: uart3-xfer {
2297 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2298 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2301 uart3_cts: uart3-cts {
2303 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2306 uart3_rts: uart3-rts {
2308 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2313 uart4_xfer: uart4-xfer {
2315 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2316 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2321 uarthdcp_xfer: uarthdcp-xfer {
2323 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2324 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2329 pwm0_pin: pwm0-pin {
2331 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2334 vop0_pwm_pin: vop0-pwm-pin {
2336 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2341 pwm1_pin: pwm1-pin {
2343 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2346 vop1_pwm_pin: vop1-pwm-pin {
2348 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2353 pwm2_pin: pwm2-pin {
2355 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2360 pwm3a_pin: pwm3a-pin {
2362 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2367 pwm3b_pin: pwm3b-pin {
2369 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2376 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2381 hdmi_i2c_xfer: hdmi-i2c-xfer {
2383 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2384 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2387 hdmi_cec: hdmi-cec {
2389 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2394 pcie_clkreqn: pci-clkreqn {
2396 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2399 pcie_clkreqnb: pci-clkreqnb {
2401 <4 24 RK_FUNC_1 &pcfg_pull_none>;