2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #ifndef __ASM_ASSEMBLER_H
24 #define __ASM_ASSEMBLER_H
26 #include <asm/asm-offsets.h>
27 #include <asm/pgtable-hwdef.h>
28 #include <asm/ptrace.h>
29 #include <asm/thread_info.h>
32 * Stack pushing/popping (register pairs only). Equivalent to store decrement
33 * before, load increment after.
35 .macro push, xreg1, xreg2
36 stp \xreg1, \xreg2, [sp, #-16]!
39 .macro pop, xreg1, xreg2
40 ldp \xreg1, \xreg2, [sp], #16
44 * Enable and disable interrupts.
55 * Enable and disable debug exceptions.
65 .macro disable_step_tsk, flgs, tmp
66 tbz \flgs, #TIF_SINGLESTEP, 9990f
70 isb // Synchronise with enable_dbg
74 .macro enable_step_tsk, flgs, tmp
75 tbz \flgs, #TIF_SINGLESTEP, 9990f
84 * Enable both debug exceptions and interrupts. This is likely to be
85 * faster than two daifclr operations, since writes to this register
86 * are self-synchronising.
88 .macro enable_dbg_and_irq
93 * SMP data memory barrier
100 * Emit an entry into the exception table
102 .macro _asm_extable, from, to
103 .pushsection __ex_table, "a"
105 .long (\from - .), (\to - .)
109 #define USER(l, x...) \
111 _asm_extable 9999b, l
116 lr .req x30 // link register
127 * Select code when configured for BE.
129 #ifdef CONFIG_CPU_BIG_ENDIAN
130 #define CPU_BE(code...) code
132 #define CPU_BE(code...)
136 * Select code when configured for LE.
138 #ifdef CONFIG_CPU_BIG_ENDIAN
139 #define CPU_LE(code...)
141 #define CPU_LE(code...) code
145 * Define a macro that constructs a 64-bit value by concatenating two
146 * 32-bit registers. Note that on big endian systems the order of the
147 * registers is swapped.
149 #ifndef CONFIG_CPU_BIG_ENDIAN
150 .macro regs_to_64, rd, lbits, hbits
152 .macro regs_to_64, rd, hbits, lbits
154 orr \rd, \lbits, \hbits, lsl #32
158 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
159 * <symbol> is within the range +/- 4 GB of the PC.
162 * @dst: destination register (64 bit wide)
163 * @sym: name of the symbol
164 * @tmp: optional scratch register to be used if <dst> == sp, which
165 * is not allowed in an adrp instruction
167 .macro adr_l, dst, sym, tmp=
170 add \dst, \dst, :lo12:\sym
173 add \dst, \tmp, :lo12:\sym
178 * @dst: destination register (32 or 64 bit wide)
179 * @sym: name of the symbol
180 * @tmp: optional 64-bit scratch register to be used if <dst> is a
181 * 32-bit wide register, in which case it cannot be used to hold
184 .macro ldr_l, dst, sym, tmp=
187 ldr \dst, [\dst, :lo12:\sym]
190 ldr \dst, [\tmp, :lo12:\sym]
195 * @src: source register (32 or 64 bit wide)
196 * @sym: name of the symbol
197 * @tmp: mandatory 64-bit scratch register to calculate the address
198 * while <src> needs to be preserved.
200 .macro str_l, src, sym, tmp
202 str \src, [\tmp, :lo12:\sym]
206 * @sym: The name of the per-cpu variable
207 * @reg: Result of per_cpu(sym, smp_processor_id())
208 * @tmp: scratch register
210 .macro this_cpu_ptr, sym, reg, tmp
217 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
219 .macro vma_vm_mm, rd, rn
220 ldr \rd, [\rn, #VMA_VM_MM]
224 * mmid - get context id from mm pointer (mm->context.id)
227 ldr \rd, [\rn, #MM_CONTEXT_ID]
231 * dcache_line_size - get the minimum D-cache line size from the CTR register.
233 .macro dcache_line_size, reg, tmp
234 mrs \tmp, ctr_el0 // read CTR
235 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
236 mov \reg, #4 // bytes per word
237 lsl \reg, \reg, \tmp // actual cache line size
241 * icache_line_size - get the minimum I-cache line size from the CTR register.
243 .macro icache_line_size, reg, tmp
244 mrs \tmp, ctr_el0 // read CTR
245 and \tmp, \tmp, #0xf // cache line size encoding
246 mov \reg, #4 // bytes per word
247 lsl \reg, \reg, \tmp // actual cache line size
251 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
253 .macro tcr_set_idmap_t0sz, valreg, tmpreg
254 #ifndef CONFIG_ARM64_VA_BITS_48
255 ldr_l \tmpreg, idmap_t0sz
256 bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
261 * Macro to perform a data cache maintenance for the interval
262 * [kaddr, kaddr + size)
264 * op: operation passed to dc instruction
265 * domain: domain used in dsb instruciton
266 * kaddr: starting virtual address of the region
267 * size: size of the region
268 * Corrupts: kaddr, size, tmp1, tmp2
270 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
271 dcache_line_size \tmp1, \tmp2
272 add \size, \kaddr, \size
274 bic \kaddr, \kaddr, \tmp2
276 add \kaddr, \kaddr, \tmp1
283 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
285 .macro reset_pmuserenr_el0, tmpreg
286 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
287 sbfx \tmpreg, \tmpreg, #8, #4
288 cmp \tmpreg, #1 // Skip if no PMU present
290 msr pmuserenr_el0, xzr // Disable PMU access from EL0
295 * Annotate a function as position independent, i.e., safe to be called before
296 * the kernel virtual mapping is activated.
298 #define ENDPIPROC(x) \
300 .type __pi_##x, %function; \
302 .size __pi_##x, . - x; \
306 * Emit a 64-bit absolute little endian symbol reference in a way that
307 * ensures that it will be resolved at build time, even when building a
308 * PIE binary. This requires cooperation from the linker script, which
309 * must emit the lo32/hi32 halves individually.
317 * mov_q - move an immediate constant into a 64-bit register using
318 * between 2 and 4 movz/movk instructions (depending on the
319 * magnitude and sign of the operand)
321 .macro mov_q, reg, val
322 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
323 movz \reg, :abs_g1_s:\val
325 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
326 movz \reg, :abs_g2_s:\val
328 movz \reg, :abs_g3:\val
329 movk \reg, :abs_g2_nc:\val
331 movk \reg, :abs_g1_nc:\val
333 movk \reg, :abs_g0_nc:\val
336 #endif /* __ASM_ASSEMBLER_H */