2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #ifndef __ASM_ASSEMBLER_H
24 #define __ASM_ASSEMBLER_H
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
29 #include <asm/pgtable-hwdef.h>
30 #include <asm/ptrace.h>
31 #include <asm/thread_info.h>
34 * Stack pushing/popping (register pairs only). Equivalent to store decrement
35 * before, load increment after.
37 .macro push, xreg1, xreg2
38 stp \xreg1, \xreg2, [sp, #-16]!
41 .macro pop, xreg1, xreg2
42 ldp \xreg1, \xreg2, [sp], #16
46 * Enable and disable interrupts.
56 .macro save_and_disable_irq, flags
61 .macro restore_irq, flags
66 * Enable and disable debug exceptions.
76 .macro disable_step_tsk, flgs, tmp
77 tbz \flgs, #TIF_SINGLESTEP, 9990f
81 isb // Synchronise with enable_dbg
85 .macro enable_step_tsk, flgs, tmp
86 tbz \flgs, #TIF_SINGLESTEP, 9990f
95 * Enable both debug exceptions and interrupts. This is likely to be
96 * faster than two daifclr operations, since writes to this register
97 * are self-synchronising.
99 .macro enable_dbg_and_irq
100 msr daifclr, #(8 | 2)
104 * SMP data memory barrier
120 * Emit an entry into the exception table
122 .macro _asm_extable, from, to
123 .pushsection __ex_table, "a"
125 .long (\from - .), (\to - .)
129 #define USER(l, x...) \
131 _asm_extable 9999b, l
136 lr .req x30 // link register
147 * Select code when configured for BE.
149 #ifdef CONFIG_CPU_BIG_ENDIAN
150 #define CPU_BE(code...) code
152 #define CPU_BE(code...)
156 * Select code when configured for LE.
158 #ifdef CONFIG_CPU_BIG_ENDIAN
159 #define CPU_LE(code...)
161 #define CPU_LE(code...) code
165 * Define a macro that constructs a 64-bit value by concatenating two
166 * 32-bit registers. Note that on big endian systems the order of the
167 * registers is swapped.
169 #ifndef CONFIG_CPU_BIG_ENDIAN
170 .macro regs_to_64, rd, lbits, hbits
172 .macro regs_to_64, rd, hbits, lbits
174 orr \rd, \lbits, \hbits, lsl #32
178 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
179 * <symbol> is within the range +/- 4 GB of the PC.
182 * @dst: destination register (64 bit wide)
183 * @sym: name of the symbol
184 * @tmp: optional scratch register to be used if <dst> == sp, which
185 * is not allowed in an adrp instruction
187 .macro adr_l, dst, sym, tmp=
190 add \dst, \dst, :lo12:\sym
193 add \dst, \tmp, :lo12:\sym
198 * @dst: destination register (32 or 64 bit wide)
199 * @sym: name of the symbol
200 * @tmp: optional 64-bit scratch register to be used if <dst> is a
201 * 32-bit wide register, in which case it cannot be used to hold
204 .macro ldr_l, dst, sym, tmp=
207 ldr \dst, [\dst, :lo12:\sym]
210 ldr \dst, [\tmp, :lo12:\sym]
215 * @src: source register (32 or 64 bit wide)
216 * @sym: name of the symbol
217 * @tmp: mandatory 64-bit scratch register to calculate the address
218 * while <src> needs to be preserved.
220 .macro str_l, src, sym, tmp
222 str \src, [\tmp, :lo12:\sym]
226 * @sym: The name of the per-cpu variable
227 * @reg: Result of per_cpu(sym, smp_processor_id())
228 * @tmp: scratch register
230 .macro this_cpu_ptr, sym, reg, tmp
237 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
239 .macro vma_vm_mm, rd, rn
240 ldr \rd, [\rn, #VMA_VM_MM]
244 * mmid - get context id from mm pointer (mm->context.id)
247 ldr \rd, [\rn, #MM_CONTEXT_ID]
251 * dcache_line_size - get the minimum D-cache line size from the CTR register.
253 .macro dcache_line_size, reg, tmp
254 mrs \tmp, ctr_el0 // read CTR
255 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
256 mov \reg, #4 // bytes per word
257 lsl \reg, \reg, \tmp // actual cache line size
261 * icache_line_size - get the minimum I-cache line size from the CTR register.
263 .macro icache_line_size, reg, tmp
264 mrs \tmp, ctr_el0 // read CTR
265 and \tmp, \tmp, #0xf // cache line size encoding
266 mov \reg, #4 // bytes per word
267 lsl \reg, \reg, \tmp // actual cache line size
271 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
273 .macro tcr_set_idmap_t0sz, valreg, tmpreg
274 #ifndef CONFIG_ARM64_VA_BITS_48
275 ldr_l \tmpreg, idmap_t0sz
276 bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
281 * Macro to perform a data cache maintenance for the interval
282 * [kaddr, kaddr + size)
284 * op: operation passed to dc instruction
285 * domain: domain used in dsb instruciton
286 * kaddr: starting virtual address of the region
287 * size: size of the region
288 * Corrupts: kaddr, size, tmp1, tmp2
290 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
291 dcache_line_size \tmp1, \tmp2
292 add \size, \kaddr, \size
294 bic \kaddr, \kaddr, \tmp2
296 .if (\op == cvau || \op == cvac)
297 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
305 add \kaddr, \kaddr, \tmp1
312 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
314 .macro reset_pmuserenr_el0, tmpreg
315 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
316 sbfx \tmpreg, \tmpreg, #8, #4
317 cmp \tmpreg, #1 // Skip if no PMU present
319 msr pmuserenr_el0, xzr // Disable PMU access from EL0
324 * copy_page - copy src to dest using temp registers t1-t8
326 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
327 9998: ldp \t1, \t2, [\src]
328 ldp \t3, \t4, [\src, #16]
329 ldp \t5, \t6, [\src, #32]
330 ldp \t7, \t8, [\src, #48]
332 stnp \t1, \t2, [\dest]
333 stnp \t3, \t4, [\dest, #16]
334 stnp \t5, \t6, [\dest, #32]
335 stnp \t7, \t8, [\dest, #48]
336 add \dest, \dest, #64
337 tst \src, #(PAGE_SIZE - 1)
342 * Annotate a function as position independent, i.e., safe to be called before
343 * the kernel virtual mapping is activated.
345 #define ENDPIPROC(x) \
347 .type __pi_##x, %function; \
349 .size __pi_##x, . - x; \
353 * Emit a 64-bit absolute little endian symbol reference in a way that
354 * ensures that it will be resolved at build time, even when building a
355 * PIE binary. This requires cooperation from the linker script, which
356 * must emit the lo32/hi32 halves individually.
364 * mov_q - move an immediate constant into a 64-bit register using
365 * between 2 and 4 movz/movk instructions (depending on the
366 * magnitude and sign of the operand)
368 .macro mov_q, reg, val
369 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
370 movz \reg, :abs_g1_s:\val
372 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
373 movz \reg, :abs_g2_s:\val
375 movz \reg, :abs_g3:\val
376 movk \reg, :abs_g2_nc:\val
378 movk \reg, :abs_g1_nc:\val
380 movk \reg, :abs_g0_nc:\val
384 * Return the current thread_info.
386 .macro get_thread_info, rd
391 * Errata workaround post TTBR0_EL1 update.
393 .macro post_ttbr0_update_workaround
394 #ifdef CONFIG_CAVIUM_ERRATUM_27456
395 alternative_if ARM64_WORKAROUND_CAVIUM_27456
399 alternative_else_nop_endif
403 #endif /* __ASM_ASSEMBLER_H */