2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/types.h>
22 /* A64 instructions are always 32 bits. */
23 #define AARCH64_INSN_SIZE 4
28 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
29 * Section C3.1 "A64 instruction index by encoding":
30 * AArch64 main encoding table
32 * 28 27 26 25 Encoding Group
34 * 1 0 0 - Data processing, immediate
35 * 1 0 1 - Branch, exception generation and system instructions
36 * - 1 - 0 Loads and stores
37 * - 1 0 1 Data processing - register
38 * 0 1 1 1 Data processing - SIMD and floating point
39 * 1 1 1 1 Data processing - SIMD and floating point
40 * "-" means "don't care"
42 enum aarch64_insn_encoding_class {
43 AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
44 AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
45 AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
46 AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
47 AARCH64_INSN_CLS_LDST, /* Loads and stores */
48 AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
49 * system instructions */
52 enum aarch64_insn_hint_op {
53 AARCH64_INSN_HINT_NOP = 0x0 << 5,
54 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
55 AARCH64_INSN_HINT_WFE = 0x2 << 5,
56 AARCH64_INSN_HINT_WFI = 0x3 << 5,
57 AARCH64_INSN_HINT_SEV = 0x4 << 5,
58 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
61 enum aarch64_insn_imm_type {
72 enum aarch64_insn_branch_type {
73 AARCH64_INSN_BRANCH_NOLINK,
74 AARCH64_INSN_BRANCH_LINK,
77 #define __AARCH64_INSN_FUNCS(abbr, mask, val) \
78 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
79 { return (code & (mask)) == (val); } \
80 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
83 __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
84 __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
85 __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
86 __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
87 __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
88 __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
89 __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
91 #undef __AARCH64_INSN_FUNCS
93 bool aarch64_insn_is_nop(u32 insn);
95 int aarch64_insn_read(void *addr, u32 *insnp);
96 int aarch64_insn_write(void *addr, u32 insn);
97 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
98 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
100 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
101 enum aarch64_insn_branch_type type);
102 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
103 u32 aarch64_insn_gen_nop(void);
105 bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
107 int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
108 int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
109 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
111 #endif /* __ASSEMBLY__ */
113 #endif /* __ASM_INSN_H */