2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * Derived from arch/arm/include/asm/kvm_host.h:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __ARM64_KVM_HOST_H__
23 #define __ARM64_KVM_HOST_H__
25 #include <linux/types.h>
26 #include <linux/kvm_types.h>
28 #include <asm/kvm_mmio.h>
30 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
32 #define KVM_USER_MEM_SLOTS 32
33 #define KVM_PRIVATE_MEM_SLOTS 4
34 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
35 #define KVM_HALT_POLL_NS_DEFAULT 500000
37 #include <kvm/arm_vgic.h>
38 #include <kvm/arm_arch_timer.h>
40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
42 #define KVM_VCPU_MAX_FEATURES 3
44 int __attribute_const__ kvm_target_cpu(void);
45 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
46 int kvm_arch_dev_ioctl_check_extension(long ext);
47 phys_addr_t kvm_hyp_reset_entry(void);
50 /* The VMID generation used for the virt. memory system */
54 /* 1-level 2nd stage table and lock */
58 /* VTTBR value associated with above pgd and vmid */
61 /* The maximum number of vCPUs depends on the used GIC model */
64 /* Interrupt controller */
65 struct vgic_dist vgic;
68 struct arch_timer_kvm timer;
71 #define KVM_NR_MEM_OBJS 40
74 * We don't want allocation failures within the mmu code, so we preallocate
75 * enough memory for a single page fault in a cache.
77 struct kvm_mmu_memory_cache {
79 void *objects[KVM_NR_MEM_OBJS];
82 struct kvm_vcpu_fault_info {
83 u32 esr_el2; /* Hyp Syndrom Register */
84 u64 far_el2; /* Hyp Fault Address Register */
85 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
89 * 0 is reserved as an invalid value.
90 * Order should be kept in sync with the save/restore code.
94 MPIDR_EL1, /* MultiProcessor Affinity Register */
95 CSSELR_EL1, /* Cache Size Selection Register */
96 SCTLR_EL1, /* System Control Register */
97 ACTLR_EL1, /* Auxiliary Control Register */
98 CPACR_EL1, /* Coprocessor Access Control */
99 TTBR0_EL1, /* Translation Table Base Register 0 */
100 TTBR1_EL1, /* Translation Table Base Register 1 */
101 TCR_EL1, /* Translation Control Register */
102 ESR_EL1, /* Exception Syndrome Register */
103 AFSR0_EL1, /* Auxilary Fault Status Register 0 */
104 AFSR1_EL1, /* Auxilary Fault Status Register 1 */
105 FAR_EL1, /* Fault Address Register */
106 MAIR_EL1, /* Memory Attribute Indirection Register */
107 VBAR_EL1, /* Vector Base Address Register */
108 CONTEXTIDR_EL1, /* Context ID Register */
109 TPIDR_EL0, /* Thread ID, User R/W */
110 TPIDRRO_EL0, /* Thread ID, User R/O */
111 TPIDR_EL1, /* Thread ID, Privileged */
112 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
113 CNTKCTL_EL1, /* Timer Control Register (EL1) */
114 PAR_EL1, /* Physical Address Register */
115 MDSCR_EL1, /* Monitor Debug System Control Register */
116 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
118 /* 32bit specific registers. Keep them at the end of the range */
119 DACR32_EL2, /* Domain Access Control Register */
120 IFSR32_EL2, /* Instruction Fault Status Register */
121 FPEXC32_EL2, /* Floating-Point Exception Control Register */
122 DBGVCR32_EL2, /* Debug Vector Catch Register */
124 NR_SYS_REGS /* Nothing after this line! */
128 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
129 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
130 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
131 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
132 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
133 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
134 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
135 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
136 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
137 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
138 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
139 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
140 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
141 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
142 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
143 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
144 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
145 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
146 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
147 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
148 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
149 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
150 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
151 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
152 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
153 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
154 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
155 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
156 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
158 #define cp14_DBGDSCRext (MDSCR_EL1 * 2)
159 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
160 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
161 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
162 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
163 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
164 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
166 #define NR_COPRO_REGS (NR_SYS_REGS * 2)
168 struct kvm_cpu_context {
169 struct kvm_regs gp_regs;
171 u64 sys_regs[NR_SYS_REGS];
172 u32 copro[NR_COPRO_REGS];
176 typedef struct kvm_cpu_context kvm_cpu_context_t;
178 struct kvm_vcpu_arch {
179 struct kvm_cpu_context ctxt;
181 /* HYP configuration */
185 /* Exception Information */
186 struct kvm_vcpu_fault_info fault;
188 /* Guest debug state */
192 * We maintain more than a single set of debug registers to support
193 * debugging the guest from the host and to maintain separate host and
194 * guest state during world switches. vcpu_debug_state are the debug
195 * registers of the vcpu as the guest sees them. host_debug_state are
196 * the host registers which are saved and restored during
197 * world switches. external_debug_state contains the debug
198 * values we want to debug the guest. This is set via the
199 * KVM_SET_GUEST_DEBUG ioctl.
201 * debug_ptr points to the set of debug registers that should be loaded
202 * onto the hardware when running the guest.
204 struct kvm_guest_debug_arch *debug_ptr;
205 struct kvm_guest_debug_arch vcpu_debug_state;
206 struct kvm_guest_debug_arch external_debug_state;
208 /* Pointer to host CPU context */
209 kvm_cpu_context_t *host_cpu_context;
210 struct kvm_guest_debug_arch host_debug_state;
213 struct vgic_cpu vgic_cpu;
214 struct arch_timer_cpu timer_cpu;
217 * Anything that is not used directly from assembly code goes
222 * Guest registers we preserve during guest debugging.
224 * These shadow registers are updated by the kvm_handle_sys_reg
225 * trap handler if the guest accesses or updates them while we
226 * are using guest debug.
230 } guest_debug_preserved;
232 /* vcpu power-off state */
235 /* Don't run the guest (internal implementation need) */
238 /* IO related fields */
239 struct kvm_decode mmio_decode;
241 /* Interrupt related fields */
242 u64 irq_lines; /* IRQ and FIQ levels */
244 /* Cache some mmu pages needed inside spinlock regions */
245 struct kvm_mmu_memory_cache mmu_page_cache;
247 /* Target CPU and feature flags */
249 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
251 /* Detect first run of a vcpu */
255 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
256 #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
258 * CP14 and CP15 live in the same array, as they are backed by the
259 * same system registers.
261 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
262 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
264 #ifdef CONFIG_CPU_BIG_ENDIAN
265 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r))
266 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1)
268 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1)
269 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r))
273 u32 remote_tlb_flush;
276 struct kvm_vcpu_stat {
277 u32 halt_successful_poll;
278 u32 halt_attempted_poll;
282 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
283 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
284 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
285 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
286 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
288 #define KVM_ARCH_WANT_MMU_NOTIFIER
289 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
290 int kvm_unmap_hva_range(struct kvm *kvm,
291 unsigned long start, unsigned long end);
292 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
293 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
294 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
296 /* We do not have shadow page tables, hence the empty hooks */
297 static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
298 unsigned long address)
302 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
303 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
305 u64 __kvm_call_hyp(void *hypfn, ...);
306 void force_vm_exit(const cpumask_t *mask);
307 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
309 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
310 int exception_index);
312 int kvm_perf_init(void);
313 int kvm_perf_teardown(void);
315 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
317 static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
319 unsigned long hyp_stack_ptr,
320 unsigned long vector_ptr)
323 * Call initialization code, and switch to the full blown
326 __kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr,
327 hyp_stack_ptr, vector_ptr);
330 static inline void __cpu_init_stage2(void)
334 static inline void __cpu_reset_hyp_mode(phys_addr_t boot_pgd_ptr,
335 phys_addr_t phys_idmap_start)
338 * Call reset code, and switch back to stub hyp vectors.
339 * Uses __kvm_call_hyp() to avoid kaslr's kvm_ksym_ref() translation.
341 __kvm_call_hyp((void *)kvm_hyp_reset_entry(),
342 boot_pgd_ptr, phys_idmap_start);
345 static inline void kvm_arch_hardware_unsetup(void) {}
346 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
347 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
348 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
350 void kvm_arm_init_debug(void);
351 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
352 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
353 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
355 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
357 #endif /* __ARM64_KVM_HOST_H__ */