2 * Copyright (C) 2012 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __ASM_PGTABLE_HWDEF_H
17 #define __ASM_PGTABLE_HWDEF_H
19 #ifdef CONFIG_ARM64_64K_PAGES
20 #include <asm/pgtable-2level-hwdef.h>
22 #include <asm/pgtable-3level-hwdef.h>
26 * Hardware page table definitions.
28 * Level 2 descriptor (PMD).
30 #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
31 #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
32 #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
33 #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
38 #define PMD_SECT_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
39 #define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
40 #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
41 #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
42 #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
43 #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54)
46 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
48 #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2)
49 #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2)
52 * Level 3 descriptor (PTE).
54 #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
55 #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
56 #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
57 #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
58 #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
59 #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
60 #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
61 #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */
62 #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */
63 #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */
66 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
68 #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
69 #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
72 * 2nd stage PTE definitions
74 #define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */
75 #define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
78 * Memory Attribute override for Stage-2 (MemAttr[3:0])
80 #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2)
81 #define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2)
84 * EL2/HYP PTE/PMD definitions
86 #define PMD_HYP PMD_SECT_USER
87 #define PTE_HYP PTE_USER
90 * 40-bit physical address supported.
92 #define PHYS_MASK_SHIFT (40)
93 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
98 #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0))
99 #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24))
100 #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24))
101 #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24))
102 #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24))
103 #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24))
104 #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26))
105 #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26))
106 #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26))
107 #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26))
108 #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26))
109 #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))
110 #define TCR_TG0_64K (UL(1) << 14)
111 #define TCR_TG1_64K (UL(1) << 30)
112 #define TCR_IPS_40BIT (UL(2) << 32)
113 #define TCR_ASID16 (UL(1) << 36)