2 * Based on arch/arm/kernel/asm-offsets.c
4 * Copyright (C) 1995-2003 Russell King
5 * 2001-2002 Keith Owens
6 * Copyright (C) 2012 ARM Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/sched.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/kvm_host.h>
25 #include <asm/thread_info.h>
26 #include <asm/memory.h>
27 #include <asm/smp_plat.h>
28 #include <asm/suspend.h>
29 #include <asm/vdso_datapage.h>
30 #include <linux/kbuild.h>
34 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
36 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
37 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
38 DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit));
39 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
40 DEFINE(TI_TTBR0, offsetof(struct thread_info, ttbr0));
42 DEFINE(TI_TASK, offsetof(struct thread_info, task));
43 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
45 DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context));
47 DEFINE(S_X0, offsetof(struct pt_regs, regs[0]));
48 DEFINE(S_X1, offsetof(struct pt_regs, regs[1]));
49 DEFINE(S_X2, offsetof(struct pt_regs, regs[2]));
50 DEFINE(S_X3, offsetof(struct pt_regs, regs[3]));
51 DEFINE(S_X4, offsetof(struct pt_regs, regs[4]));
52 DEFINE(S_X5, offsetof(struct pt_regs, regs[5]));
53 DEFINE(S_X6, offsetof(struct pt_regs, regs[6]));
54 DEFINE(S_X7, offsetof(struct pt_regs, regs[7]));
55 DEFINE(S_X8, offsetof(struct pt_regs, regs[8]));
56 DEFINE(S_X10, offsetof(struct pt_regs, regs[10]));
57 DEFINE(S_X12, offsetof(struct pt_regs, regs[12]));
58 DEFINE(S_X14, offsetof(struct pt_regs, regs[14]));
59 DEFINE(S_X16, offsetof(struct pt_regs, regs[16]));
60 DEFINE(S_X18, offsetof(struct pt_regs, regs[18]));
61 DEFINE(S_X20, offsetof(struct pt_regs, regs[20]));
62 DEFINE(S_X22, offsetof(struct pt_regs, regs[22]));
63 DEFINE(S_X24, offsetof(struct pt_regs, regs[24]));
64 DEFINE(S_X26, offsetof(struct pt_regs, regs[26]));
65 DEFINE(S_X28, offsetof(struct pt_regs, regs[28]));
66 DEFINE(S_LR, offsetof(struct pt_regs, regs[30]));
67 DEFINE(S_SP, offsetof(struct pt_regs, sp));
69 DEFINE(S_COMPAT_SP, offsetof(struct pt_regs, compat_sp));
71 DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate));
72 DEFINE(S_PC, offsetof(struct pt_regs, pc));
73 DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0));
74 DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno));
75 DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit));
76 DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
78 DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
80 DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
81 DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
83 DEFINE(VM_EXEC, VM_EXEC);
85 DEFINE(PAGE_SZ, PAGE_SIZE);
87 DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
88 DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
89 DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
91 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
92 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
93 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
94 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
95 DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE);
96 DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC);
97 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
99 DEFINE(VDSO_CS_CYCLE_LAST, offsetof(struct vdso_data, cs_cycle_last));
100 DEFINE(VDSO_XTIME_CLK_SEC, offsetof(struct vdso_data, xtime_clock_sec));
101 DEFINE(VDSO_XTIME_CLK_NSEC, offsetof(struct vdso_data, xtime_clock_nsec));
102 DEFINE(VDSO_XTIME_CRS_SEC, offsetof(struct vdso_data, xtime_coarse_sec));
103 DEFINE(VDSO_XTIME_CRS_NSEC, offsetof(struct vdso_data, xtime_coarse_nsec));
104 DEFINE(VDSO_WTM_CLK_SEC, offsetof(struct vdso_data, wtm_clock_sec));
105 DEFINE(VDSO_WTM_CLK_NSEC, offsetof(struct vdso_data, wtm_clock_nsec));
106 DEFINE(VDSO_TB_SEQ_COUNT, offsetof(struct vdso_data, tb_seq_count));
107 DEFINE(VDSO_CS_MULT, offsetof(struct vdso_data, cs_mult));
108 DEFINE(VDSO_CS_SHIFT, offsetof(struct vdso_data, cs_shift));
109 DEFINE(VDSO_TZ_MINWEST, offsetof(struct vdso_data, tz_minuteswest));
110 DEFINE(VDSO_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime));
111 DEFINE(VDSO_USE_SYSCALL, offsetof(struct vdso_data, use_syscall));
113 DEFINE(TVAL_TV_SEC, offsetof(struct timeval, tv_sec));
114 DEFINE(TVAL_TV_USEC, offsetof(struct timeval, tv_usec));
115 DEFINE(TSPEC_TV_SEC, offsetof(struct timespec, tv_sec));
116 DEFINE(TSPEC_TV_NSEC, offsetof(struct timespec, tv_nsec));
118 DEFINE(TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
119 DEFINE(TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
121 #ifdef CONFIG_KVM_ARM_HOST
122 DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt));
123 DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs));
124 DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs));
125 DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs));
126 DEFINE(CPU_SP_EL1, offsetof(struct kvm_regs, sp_el1));
127 DEFINE(CPU_ELR_EL1, offsetof(struct kvm_regs, elr_el1));
128 DEFINE(CPU_SPSR, offsetof(struct kvm_regs, spsr));
129 DEFINE(CPU_SYSREGS, offsetof(struct kvm_cpu_context, sys_regs));
130 DEFINE(VCPU_ESR_EL2, offsetof(struct kvm_vcpu, arch.fault.esr_el2));
131 DEFINE(VCPU_FAR_EL2, offsetof(struct kvm_vcpu, arch.fault.far_el2));
132 DEFINE(VCPU_HPFAR_EL2, offsetof(struct kvm_vcpu, arch.fault.hpfar_el2));
133 DEFINE(VCPU_DEBUG_FLAGS, offsetof(struct kvm_vcpu, arch.debug_flags));
134 DEFINE(VCPU_DEBUG_PTR, offsetof(struct kvm_vcpu, arch.debug_ptr));
135 DEFINE(DEBUG_BCR, offsetof(struct kvm_guest_debug_arch, dbg_bcr));
136 DEFINE(DEBUG_BVR, offsetof(struct kvm_guest_debug_arch, dbg_bvr));
137 DEFINE(DEBUG_WCR, offsetof(struct kvm_guest_debug_arch, dbg_wcr));
138 DEFINE(DEBUG_WVR, offsetof(struct kvm_guest_debug_arch, dbg_wvr));
139 DEFINE(VCPU_HCR_EL2, offsetof(struct kvm_vcpu, arch.hcr_el2));
140 DEFINE(VCPU_MDCR_EL2, offsetof(struct kvm_vcpu, arch.mdcr_el2));
141 DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines));
142 DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context));
143 DEFINE(VCPU_HOST_DEBUG_STATE, offsetof(struct kvm_vcpu, arch.host_debug_state));
144 DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
145 DEFINE(VCPU_TIMER_CNTV_CVAL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
146 DEFINE(KVM_TIMER_CNTVOFF, offsetof(struct kvm, arch.timer.cntvoff));
147 DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled));
148 DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
149 DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu));
150 DEFINE(VGIC_V2_CPU_HCR, offsetof(struct vgic_cpu, vgic_v2.vgic_hcr));
151 DEFINE(VGIC_V2_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v2.vgic_vmcr));
152 DEFINE(VGIC_V2_CPU_MISR, offsetof(struct vgic_cpu, vgic_v2.vgic_misr));
153 DEFINE(VGIC_V2_CPU_EISR, offsetof(struct vgic_cpu, vgic_v2.vgic_eisr));
154 DEFINE(VGIC_V2_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr));
155 DEFINE(VGIC_V2_CPU_APR, offsetof(struct vgic_cpu, vgic_v2.vgic_apr));
156 DEFINE(VGIC_V2_CPU_LR, offsetof(struct vgic_cpu, vgic_v2.vgic_lr));
157 DEFINE(VGIC_V3_CPU_SRE, offsetof(struct vgic_cpu, vgic_v3.vgic_sre));
158 DEFINE(VGIC_V3_CPU_HCR, offsetof(struct vgic_cpu, vgic_v3.vgic_hcr));
159 DEFINE(VGIC_V3_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v3.vgic_vmcr));
160 DEFINE(VGIC_V3_CPU_MISR, offsetof(struct vgic_cpu, vgic_v3.vgic_misr));
161 DEFINE(VGIC_V3_CPU_EISR, offsetof(struct vgic_cpu, vgic_v3.vgic_eisr));
162 DEFINE(VGIC_V3_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v3.vgic_elrsr));
163 DEFINE(VGIC_V3_CPU_AP0R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap0r));
164 DEFINE(VGIC_V3_CPU_AP1R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap1r));
165 DEFINE(VGIC_V3_CPU_LR, offsetof(struct vgic_cpu, vgic_v3.vgic_lr));
166 DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr));
167 DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr));
168 DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base));
171 DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx));
172 DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp));
173 DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask));
174 DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff));
175 DEFINE(SLEEP_SAVE_SP_SZ, sizeof(struct sleep_save_sp));
176 DEFINE(SLEEP_SAVE_SP_PHYS, offsetof(struct sleep_save_sp, save_ptr_stash_phys));
177 DEFINE(SLEEP_SAVE_SP_VIRT, offsetof(struct sleep_save_sp, save_ptr_stash));