arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/sort.h>
  23 #include <linux/types.h>
  24 #include <asm/cpu.h>
  25 #include <asm/cpufeature.h>
  26 #include <asm/cpu_ops.h>
  27 #include <asm/processor.h>
  28 #include <asm/sysreg.h>
  29 #include <asm/virt.h>
  30
  31 unsigned long elf_hwcap __read_mostly;
  32 EXPORT_SYMBOL_GPL(elf_hwcap);
  33
  34 #ifdef CONFIG_COMPAT
  35 #define COMPAT_ELF_HWCAP_DEFAULT        \
  36                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  37                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  38                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  39                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  40                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  41                                  COMPAT_HWCAP_LPAE)
  42 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  43 unsigned int compat_elf_hwcap2 __read_mostly;
  44 #endif
  45
  46 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  47
  48 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  49         {                                               \
  50                 .sign = SIGNED,                         \
  51                 .strict = STRICT,                       \
  52                 .type = TYPE,                           \
  53                 .shift = SHIFT,                         \
  54                 .width = WIDTH,                         \
  55                 .safe_val = SAFE_VAL,                   \
  56         }
  57
  58 /* Define a feature with signed values */
  59 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  60         __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  61
  62 /* Define a feature with unsigned value */
  63 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  64         __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  65
  66 #define ARM64_FTR_END                                   \
  67         {                                               \
  68                 .width = 0,                             \
  69         }
  70
  71 /* meta feature for alternatives */
  72 static bool __maybe_unused
  73 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
  74
  75 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  76         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  77         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  78         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
  79         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  80         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  81         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  82         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  83         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  84         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
  85         ARM64_FTR_END,
  86 };
  87
  88 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  89         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  90         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
  91         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  92         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  93         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  94         /* Linux doesn't care about the EL3 */
  95         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
  96         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
  97         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
  98         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
  99         ARM64_FTR_END,
 100 };
 101
 102 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 103         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 104         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 105         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 106         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 107         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 108         /* Linux shouldn't care about secure memory */
 109         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 110         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 111         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 112         /*
 113          * Differing PARange is fine as long as all peripherals and memory are mapped
 114          * within the minimum PARange of all CPUs
 115          */
 116         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 117         ARM64_FTR_END,
 118 };
 119
 120 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 121         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 122         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 128         ARM64_FTR_END,
 129 };
 130
 131 static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 132         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 133         ARM64_FTR_END,
 134 };
 135
 136 static struct arm64_ftr_bits ftr_ctr[] = {
 137         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),      /* RAO */
 138         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
 139         U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),        /* CWG */
 140         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
 141         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
 142         /*
 143          * Linux can handle differing I-cache policies. Userspace JITs will
 144          * make use of *minLine
 145          */
 146         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),   /* L1Ip */
 147         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),        /* RAZ */
 148         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),  /* IminLine */
 149         ARM64_FTR_END,
 150 };
 151
 152 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
 153         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),        /* InnerShr */
 154         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
 155         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),        /* AuxReg */
 156         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),        /* TCM */
 157         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* ShareLvl */
 158         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
 159         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
 160         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
 161         ARM64_FTR_END,
 162 };
 163
 164 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 165         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 166         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 167         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 168         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 169         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 170         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 171         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 172         ARM64_FTR_END,
 173 };
 174
 175 static struct arm64_ftr_bits ftr_mvfr2[] = {
 176         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 177         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* FPMisc */
 178         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* SIMDMisc */
 179         ARM64_FTR_END,
 180 };
 181
 182 static struct arm64_ftr_bits ftr_dczid[] = {
 183         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0),        /* RAZ */
 184         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1),         /* DZP */
 185         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* BS */
 186         ARM64_FTR_END,
 187 };
 188
 189
 190 static struct arm64_ftr_bits ftr_id_isar5[] = {
 191         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 192         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0),        /* RAZ */
 193         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 194         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 196         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 197         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 198         ARM64_FTR_END,
 199 };
 200
 201 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
 202         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 203         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* ac2 */
 204         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* RAZ */
 205         ARM64_FTR_END,
 206 };
 207
 208 static struct arm64_ftr_bits ftr_id_pfr0[] = {
 209         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0),       /* RAZ */
 210         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* State3 */
 211         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),         /* State2 */
 212         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* State1 */
 213         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* State0 */
 214         ARM64_FTR_END,
 215 };
 216
 217 /*
 218  * Common ftr bits for a 32bit register with all hidden, strict
 219  * attributes, with 4bit feature fields and a default safe value of
 220  * 0. Covers the following 32bit registers:
 221  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 222  */
 223 static struct arm64_ftr_bits ftr_generic_32bits[] = {
 224         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 225         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 226         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 227         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 228         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 229         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 230         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 231         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 232         ARM64_FTR_END,
 233 };
 234
 235 static struct arm64_ftr_bits ftr_generic[] = {
 236         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 237         ARM64_FTR_END,
 238 };
 239
 240 static struct arm64_ftr_bits ftr_generic32[] = {
 241         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
 242         ARM64_FTR_END,
 243 };
 244
 245 static struct arm64_ftr_bits ftr_aa64raz[] = {
 246         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 247         ARM64_FTR_END,
 248 };
 249
 250 #define ARM64_FTR_REG(id, table)                \
 251         {                                       \
 252                 .sys_id = id,                   \
 253                 .name = #id,                    \
 254                 .ftr_bits = &((table)[0]),      \
 255         }
 256
 257 static struct arm64_ftr_reg arm64_ftr_regs[] = {
 258
 259         /* Op1 = 0, CRn = 0, CRm = 1 */
 260         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 261         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 262         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
 263         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 264         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 265         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 266         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 267
 268         /* Op1 = 0, CRn = 0, CRm = 2 */
 269         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 270         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 271         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 272         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 273         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 274         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 275         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 276
 277         /* Op1 = 0, CRn = 0, CRm = 3 */
 278         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 279         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 280         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 281
 282         /* Op1 = 0, CRn = 0, CRm = 4 */
 283         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 284         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
 285
 286         /* Op1 = 0, CRn = 0, CRm = 5 */
 287         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 288         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
 289
 290         /* Op1 = 0, CRn = 0, CRm = 6 */
 291         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 292         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
 293
 294         /* Op1 = 0, CRn = 0, CRm = 7 */
 295         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 296         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 297         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 298
 299         /* Op1 = 3, CRn = 0, CRm = 0 */
 300         ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
 301         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 302
 303         /* Op1 = 3, CRn = 14, CRm = 0 */
 304         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
 305 };
 306
 307 static int search_cmp_ftr_reg(const void *id, const void *regp)
 308 {
 309         return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
 310 }
 311
 312 /*
 313  * get_arm64_ftr_reg - Lookup a feature register entry using its
 314  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 315  * ascending order of sys_id , we use binary search to find a matching
 316  * entry.
 317  *
 318  * returns - Upon success,  matching ftr_reg entry for id.
 319  *         - NULL on failure. It is upto the caller to decide
 320  *           the impact of a failure.
 321  */
 322 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 323 {
 324         return bsearch((const void *)(unsigned long)sys_id,
 325                         arm64_ftr_regs,
 326                         ARRAY_SIZE(arm64_ftr_regs),
 327                         sizeof(arm64_ftr_regs[0]),
 328                         search_cmp_ftr_reg);
 329 }
 330
 331 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
 332 {
 333         u64 mask = arm64_ftr_mask(ftrp);
 334
 335         reg &= ~mask;
 336         reg |= (ftr_val << ftrp->shift) & mask;
 337         return reg;
 338 }
 339
 340 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
 341 {
 342         s64 ret = 0;
 343
 344         switch (ftrp->type) {
 345         case FTR_EXACT:
 346                 ret = ftrp->safe_val;
 347                 break;
 348         case FTR_LOWER_SAFE:
 349                 ret = new < cur ? new : cur;
 350                 break;
 351         case FTR_HIGHER_SAFE:
 352                 ret = new > cur ? new : cur;
 353                 break;
 354         default:
 355                 BUG();
 356         }
 357
 358         return ret;
 359 }
 360
 361 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
 362 {
 363         return ((const struct arm64_ftr_reg *)a)->sys_id -
 364                  ((const struct arm64_ftr_reg *)b)->sys_id;
 365 }
 366
 367 static void __init swap_ftr_regs(void *a, void *b, int size)
 368 {
 369         struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
 370         *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
 371         *(struct arm64_ftr_reg *)b = tmp;
 372 }
 373
 374 static void __init sort_ftr_regs(void)
 375 {
 376         /* Keep the array sorted so that we can do the binary search */
 377         sort(arm64_ftr_regs,
 378                 ARRAY_SIZE(arm64_ftr_regs),
 379                 sizeof(arm64_ftr_regs[0]),
 380                 sort_cmp_ftr_regs,
 381                 swap_ftr_regs);
 382 }
 383
 384 /*
 385  * Initialise the CPU feature register from Boot CPU values.
 386  * Also initiliases the strict_mask for the register.
 387  */
 388 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 389 {
 390         u64 val = 0;
 391         u64 strict_mask = ~0x0ULL;
 392         struct arm64_ftr_bits *ftrp;
 393         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 394
 395         BUG_ON(!reg);
 396
 397         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 398                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 399
 400                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 401                 if (!ftrp->strict)
 402                         strict_mask &= ~arm64_ftr_mask(ftrp);
 403         }
 404         reg->sys_val = val;
 405         reg->strict_mask = strict_mask;
 406 }
 407
 408 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 409 {
 410         /* Before we start using the tables, make sure it is sorted */
 411         sort_ftr_regs();
 412
 413         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 414         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 415         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 416         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 417         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 418         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 419         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 420         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 421         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 422         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 423         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 424         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 425         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 426         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 427         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 428         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 429         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 430         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 431         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 432         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 433         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 434         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 435         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 436         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 437         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 438         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 439         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 440         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 441 }
 442
 443 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 444 {
 445         struct arm64_ftr_bits *ftrp;
 446
 447         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 448                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 449                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 450
 451                 if (ftr_cur == ftr_new)
 452                         continue;
 453                 /* Find a safe value */
 454                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 455                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 456         }
 457
 458 }
 459
 460 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 461 {
 462         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 463
 464         BUG_ON(!regp);
 465         update_cpu_ftr_reg(regp, val);
 466         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 467                 return 0;
 468         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 469                         regp->name, boot, cpu, val);
 470         return 1;
 471 }
 472
 473 /*
 474  * Update system wide CPU feature registers with the values from a
 475  * non-boot CPU. Also performs SANITY checks to make sure that there
 476  * aren't any insane variations from that of the boot CPU.
 477  */
 478 void update_cpu_features(int cpu,
 479                          struct cpuinfo_arm64 *info,
 480                          struct cpuinfo_arm64 *boot)
 481 {
 482         int taint = 0;
 483
 484         /*
 485          * The kernel can handle differing I-cache policies, but otherwise
 486          * caches should look identical. Userspace JITs will make use of
 487          * *minLine.
 488          */
 489         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 490                                       info->reg_ctr, boot->reg_ctr);
 491
 492         /*
 493          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 494          * could result in too much or too little memory being zeroed if a
 495          * process is preempted and migrated between CPUs.
 496          */
 497         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 498                                       info->reg_dczid, boot->reg_dczid);
 499
 500         /* If different, timekeeping will be broken (especially with KVM) */
 501         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 502                                       info->reg_cntfrq, boot->reg_cntfrq);
 503
 504         /*
 505          * The kernel uses self-hosted debug features and expects CPUs to
 506          * support identical debug features. We presently need CTX_CMPs, WRPs,
 507          * and BRPs to be identical.
 508          * ID_AA64DFR1 is currently RES0.
 509          */
 510         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 511                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 512         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 513                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 514         /*
 515          * Even in big.LITTLE, processors should be identical instruction-set
 516          * wise.
 517          */
 518         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 519                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 520         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 521                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 522
 523         /*
 524          * Differing PARange support is fine as long as all peripherals and
 525          * memory are mapped within the minimum PARange of all CPUs.
 526          * Linux should not care about secure memory.
 527          */
 528         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 529                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 530         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 531                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 532         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 533                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 534
 535         /*
 536          * EL3 is not our concern.
 537          * ID_AA64PFR1 is currently RES0.
 538          */
 539         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 540                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 541         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 542                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 543
 544         /*
 545          * If we have AArch32, we care about 32-bit features for compat. These
 546          * registers should be RES0 otherwise.
 547          */
 548         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 549                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 550         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 551                                         info->reg_id_isar0, boot->reg_id_isar0);
 552         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 553                                         info->reg_id_isar1, boot->reg_id_isar1);
 554         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 555                                         info->reg_id_isar2, boot->reg_id_isar2);
 556         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 557                                         info->reg_id_isar3, boot->reg_id_isar3);
 558         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 559                                         info->reg_id_isar4, boot->reg_id_isar4);
 560         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 561                                         info->reg_id_isar5, boot->reg_id_isar5);
 562
 563         /*
 564          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 565          * ACTLR formats could differ across CPUs and therefore would have to
 566          * be trapped for virtualization anyway.
 567          */
 568         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 569                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 570         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 571                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 572         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 573                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 574         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 575                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 576         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 577                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 578         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 579                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 580         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 581                                         info->reg_mvfr0, boot->reg_mvfr0);
 582         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 583                                         info->reg_mvfr1, boot->reg_mvfr1);
 584         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 585                                         info->reg_mvfr2, boot->reg_mvfr2);
 586
 587         /*
 588          * Mismatched CPU features are a recipe for disaster. Don't even
 589          * pretend to support them.
 590          */
 591         WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
 592                         "Unsupported CPU feature variation.\n");
 593 }
 594
 595 u64 read_system_reg(u32 id)
 596 {
 597         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 598
 599         /* We shouldn't get a request for an unsupported register */
 600         BUG_ON(!regp);
 601         return regp->sys_val;
 602 }
 603
 604 #include <linux/irqchip/arm-gic-v3.h>
 605
 606 static bool
 607 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 608 {
 609         int val = cpuid_feature_extract_field(reg, entry->field_pos);
 610
 611         return val >= entry->min_field_value;
 612 }
 613
 614 static bool
 615 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
 616 {
 617         u64 val;
 618
 619         val = read_system_reg(entry->sys_reg);
 620         return feature_matches(val, entry);
 621 }
 622
 623 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
 624 {
 625         bool has_sre;
 626
 627         if (!has_cpuid_feature(entry))
 628                 return false;
 629
 630         has_sre = gic_enable_sre();
 631         if (!has_sre)
 632                 pr_warn_once("%s present but disabled by higher exception level\n",
 633                              entry->desc);
 634
 635         return has_sre;
 636 }
 637
 638 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
 639 {
 640         u32 midr = read_cpuid_id();
 641         u32 rv_min, rv_max;
 642
 643         /* Cavium ThunderX pass 1.x and 2.x */
 644         rv_min = 0;
 645         rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
 646
 647         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
 648 }
 649
 650 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
 651 {
 652         return is_kernel_in_hyp_mode();
 653 }
 654
 655 static const struct arm64_cpu_capabilities arm64_features[] = {
 656         {
 657                 .desc = "GIC system register CPU interface",
 658                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 659                 .matches = has_useable_gicv3_cpuif,
 660                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 661                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 662                 .min_field_value = 1,
 663         },
 664 #ifdef CONFIG_ARM64_PAN
 665         {
 666                 .desc = "Privileged Access Never",
 667                 .capability = ARM64_HAS_PAN,
 668                 .matches = has_cpuid_feature,
 669                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 670                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 671                 .min_field_value = 1,
 672                 .enable = cpu_enable_pan,
 673         },
 674 #endif /* CONFIG_ARM64_PAN */
 675 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 676         {
 677                 .desc = "LSE atomic instructions",
 678                 .capability = ARM64_HAS_LSE_ATOMICS,
 679                 .matches = has_cpuid_feature,
 680                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 681                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 682                 .min_field_value = 2,
 683         },
 684 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 685         {
 686                 .desc = "Software prefetching using PRFM",
 687                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 688                 .matches = has_no_hw_prefetch,
 689         },
 690 #ifdef CONFIG_ARM64_UAO
 691         {
 692                 .desc = "User Access Override",
 693                 .capability = ARM64_HAS_UAO,
 694                 .matches = has_cpuid_feature,
 695                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
 696                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
 697                 .min_field_value = 1,
 698                 .enable = cpu_enable_uao,
 699         },
 700 #endif /* CONFIG_ARM64_UAO */
 701 #ifdef CONFIG_ARM64_PAN
 702         {
 703                 .capability = ARM64_ALT_PAN_NOT_UAO,
 704                 .matches = cpufeature_pan_not_uao,
 705         },
 706 #endif /* CONFIG_ARM64_PAN */
 707         {
 708                 .desc = "Virtualization Host Extensions",
 709                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
 710                 .matches = runs_at_el2,
 711         },
 712         {},
 713 };
 714
 715 #define HWCAP_CAP(reg, field, min_value, type, cap)             \
 716         {                                                       \
 717                 .desc = #cap,                                   \
 718                 .matches = has_cpuid_feature,                   \
 719                 .sys_reg = reg,                                 \
 720                 .field_pos = field,                             \
 721                 .min_field_value = min_value,                   \
 722                 .hwcap_type = type,                             \
 723                 .hwcap = cap,                                   \
 724         }
 725
 726 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
 727         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
 728         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
 729         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
 730         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
 731         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
 732         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
 733         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
 734         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
 735 #ifdef CONFIG_COMPAT
 736         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 737         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 738         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 739         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 740         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 741 #endif
 742         {},
 743 };
 744
 745 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
 746 {
 747         switch (cap->hwcap_type) {
 748         case CAP_HWCAP:
 749                 elf_hwcap |= cap->hwcap;
 750                 break;
 751 #ifdef CONFIG_COMPAT
 752         case CAP_COMPAT_HWCAP:
 753                 compat_elf_hwcap |= (u32)cap->hwcap;
 754                 break;
 755         case CAP_COMPAT_HWCAP2:
 756                 compat_elf_hwcap2 |= (u32)cap->hwcap;
 757                 break;
 758 #endif
 759         default:
 760                 WARN_ON(1);
 761                 break;
 762         }
 763 }
 764
 765 /* Check if we have a particular HWCAP enabled */
 766 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
 767 {
 768         bool rc;
 769
 770         switch (cap->hwcap_type) {
 771         case CAP_HWCAP:
 772                 rc = (elf_hwcap & cap->hwcap) != 0;
 773                 break;
 774 #ifdef CONFIG_COMPAT
 775         case CAP_COMPAT_HWCAP:
 776                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
 777                 break;
 778         case CAP_COMPAT_HWCAP2:
 779                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
 780                 break;
 781 #endif
 782         default:
 783                 WARN_ON(1);
 784                 rc = false;
 785         }
 786
 787         return rc;
 788 }
 789
 790 static void __init setup_cpu_hwcaps(void)
 791 {
 792         int i;
 793         const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
 794
 795         for (i = 0; hwcaps[i].matches; i++)
 796                 if (hwcaps[i].matches(&hwcaps[i]))
 797                         cap_set_hwcap(&hwcaps[i]);
 798 }
 799
 800 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 801                             const char *info)
 802 {
 803         int i;
 804
 805         for (i = 0; caps[i].matches; i++) {
 806                 if (!caps[i].matches(&caps[i]))
 807                         continue;
 808
 809                 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
 810                         pr_info("%s %s\n", info, caps[i].desc);
 811                 cpus_set_cap(caps[i].capability);
 812         }
 813 }
 814
 815 /*
 816  * Run through the enabled capabilities and enable() it on all active
 817  * CPUs
 818  */
 819 static void __init
 820 enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 821 {
 822         int i;
 823
 824         for (i = 0; caps[i].matches; i++)
 825                 if (caps[i].enable && cpus_have_cap(caps[i].capability))
 826                         on_each_cpu(caps[i].enable, NULL, true);
 827 }
 828
 829 #ifdef CONFIG_HOTPLUG_CPU
 830
 831 /*
 832  * Flag to indicate if we have computed the system wide
 833  * capabilities based on the boot time active CPUs. This
 834  * will be used to determine if a new booting CPU should
 835  * go through the verification process to make sure that it
 836  * supports the system capabilities, without using a hotplug
 837  * notifier.
 838  */
 839 static bool sys_caps_initialised;
 840
 841 static inline void set_sys_caps_initialised(void)
 842 {
 843         sys_caps_initialised = true;
 844 }
 845
 846 /*
 847  * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
 848  */
 849 static u64 __raw_read_system_reg(u32 sys_id)
 850 {
 851         switch (sys_id) {
 852         case SYS_ID_PFR0_EL1:           return read_cpuid(SYS_ID_PFR0_EL1);
 853         case SYS_ID_PFR1_EL1:           return read_cpuid(SYS_ID_PFR1_EL1);
 854         case SYS_ID_DFR0_EL1:           return read_cpuid(SYS_ID_DFR0_EL1);
 855         case SYS_ID_MMFR0_EL1:          return read_cpuid(SYS_ID_MMFR0_EL1);
 856         case SYS_ID_MMFR1_EL1:          return read_cpuid(SYS_ID_MMFR1_EL1);
 857         case SYS_ID_MMFR2_EL1:          return read_cpuid(SYS_ID_MMFR2_EL1);
 858         case SYS_ID_MMFR3_EL1:          return read_cpuid(SYS_ID_MMFR3_EL1);
 859         case SYS_ID_ISAR0_EL1:          return read_cpuid(SYS_ID_ISAR0_EL1);
 860         case SYS_ID_ISAR1_EL1:          return read_cpuid(SYS_ID_ISAR1_EL1);
 861         case SYS_ID_ISAR2_EL1:          return read_cpuid(SYS_ID_ISAR2_EL1);
 862         case SYS_ID_ISAR3_EL1:          return read_cpuid(SYS_ID_ISAR3_EL1);
 863         case SYS_ID_ISAR4_EL1:          return read_cpuid(SYS_ID_ISAR4_EL1);
 864         case SYS_ID_ISAR5_EL1:          return read_cpuid(SYS_ID_ISAR4_EL1);
 865         case SYS_MVFR0_EL1:             return read_cpuid(SYS_MVFR0_EL1);
 866         case SYS_MVFR1_EL1:             return read_cpuid(SYS_MVFR1_EL1);
 867         case SYS_MVFR2_EL1:             return read_cpuid(SYS_MVFR2_EL1);
 868
 869         case SYS_ID_AA64PFR0_EL1:       return read_cpuid(SYS_ID_AA64PFR0_EL1);
 870         case SYS_ID_AA64PFR1_EL1:       return read_cpuid(SYS_ID_AA64PFR0_EL1);
 871         case SYS_ID_AA64DFR0_EL1:       return read_cpuid(SYS_ID_AA64DFR0_EL1);
 872         case SYS_ID_AA64DFR1_EL1:       return read_cpuid(SYS_ID_AA64DFR0_EL1);
 873         case SYS_ID_AA64MMFR0_EL1:      return read_cpuid(SYS_ID_AA64MMFR0_EL1);
 874         case SYS_ID_AA64MMFR1_EL1:      return read_cpuid(SYS_ID_AA64MMFR1_EL1);
 875         case SYS_ID_AA64MMFR2_EL1:      return read_cpuid(SYS_ID_AA64MMFR2_EL1);
 876         case SYS_ID_AA64ISAR0_EL1:      return read_cpuid(SYS_ID_AA64ISAR0_EL1);
 877         case SYS_ID_AA64ISAR1_EL1:      return read_cpuid(SYS_ID_AA64ISAR1_EL1);
 878
 879         case SYS_CNTFRQ_EL0:            return read_cpuid(SYS_CNTFRQ_EL0);
 880         case SYS_CTR_EL0:               return read_cpuid(SYS_CTR_EL0);
 881         case SYS_DCZID_EL0:             return read_cpuid(SYS_DCZID_EL0);
 882         default:
 883                 BUG();
 884                 return 0;
 885         }
 886 }
 887
 888 /*
 889  * Park the CPU which doesn't have the capability as advertised
 890  * by the system.
 891  */
 892 static void fail_incapable_cpu(char *cap_type,
 893                                  const struct arm64_cpu_capabilities *cap)
 894 {
 895         int cpu = smp_processor_id();
 896
 897         pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
 898         /* Mark this CPU absent */
 899         set_cpu_present(cpu, 0);
 900
 901         /* Check if we can park ourselves */
 902         if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
 903                 cpu_ops[cpu]->cpu_die(cpu);
 904         asm(
 905         "1:     wfe\n"
 906         "       wfi\n"
 907         "       b       1b");
 908 }
 909
 910 /*
 911  * Run through the enabled system capabilities and enable() it on this CPU.
 912  * The capabilities were decided based on the available CPUs at the boot time.
 913  * Any new CPU should match the system wide status of the capability. If the
 914  * new CPU doesn't have a capability which the system now has enabled, we
 915  * cannot do anything to fix it up and could cause unexpected failures. So
 916  * we park the CPU.
 917  */
 918 void verify_local_cpu_capabilities(void)
 919 {
 920         int i;
 921         const struct arm64_cpu_capabilities *caps;
 922
 923         /*
 924          * If we haven't computed the system capabilities, there is nothing
 925          * to verify.
 926          */
 927         if (!sys_caps_initialised)
 928                 return;
 929
 930         caps = arm64_features;
 931         for (i = 0; caps[i].matches; i++) {
 932                 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
 933                         continue;
 934                 /*
 935                  * If the new CPU misses an advertised feature, we cannot proceed
 936                  * further, park the cpu.
 937                  */
 938                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 939                         fail_incapable_cpu("arm64_features", &caps[i]);
 940                 if (caps[i].enable)
 941                         caps[i].enable(NULL);
 942         }
 943
 944         for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
 945                 if (!cpus_have_hwcap(&caps[i]))
 946                         continue;
 947                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 948                         fail_incapable_cpu("arm64_hwcaps", &caps[i]);
 949         }
 950 }
 951
 952 #else   /* !CONFIG_HOTPLUG_CPU */
 953
 954 static inline void set_sys_caps_initialised(void)
 955 {
 956 }
 957
 958 #endif  /* CONFIG_HOTPLUG_CPU */
 959
 960 static void __init setup_feature_capabilities(void)
 961 {
 962         update_cpu_capabilities(arm64_features, "detected feature:");
 963         enable_cpu_capabilities(arm64_features);
 964 }
 965
 966 void __init setup_cpu_features(void)
 967 {
 968         u32 cwg;
 969         int cls;
 970
 971         /* Set the CPU feature capabilies */
 972         setup_feature_capabilities();
 973         setup_cpu_hwcaps();
 974
 975         /* Advertise that we have computed the system capabilities */
 976         set_sys_caps_initialised();
 977
 978         /*
 979          * Check for sane CTR_EL0.CWG value.
 980          */
 981         cwg = cache_type_cwg();
 982         cls = cache_line_size();
 983         if (!cwg)
 984                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
 985                         cls);
 986         if (L1_CACHE_BYTES < cls)
 987                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
 988                         L1_CACHE_BYTES, cls);
 989 }
 990
 991 static bool __maybe_unused
 992 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
 993 {
 994         return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
 995 }