arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/sort.h>
  23 #include <linux/types.h>
  24 #include <asm/cpu.h>
  25 #include <asm/cpufeature.h>
  26 #include <asm/cpu_ops.h>
  27 #include <asm/processor.h>
  28 #include <asm/sysreg.h>
  29 #include <asm/virt.h>
  30
  31 unsigned long elf_hwcap __read_mostly;
  32 EXPORT_SYMBOL_GPL(elf_hwcap);
  33
  34 #ifdef CONFIG_COMPAT
  35 #define COMPAT_ELF_HWCAP_DEFAULT        \
  36                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  37                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  38                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  39                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  40                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  41                                  COMPAT_HWCAP_LPAE)
  42 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  43 unsigned int compat_elf_hwcap2 __read_mostly;
  44 #endif
  45
  46 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  47 EXPORT_SYMBOL(cpu_hwcaps);
  48
  49 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  50         {                                               \
  51                 .sign = SIGNED,                         \
  52                 .strict = STRICT,                       \
  53                 .type = TYPE,                           \
  54                 .shift = SHIFT,                         \
  55                 .width = WIDTH,                         \
  56                 .safe_val = SAFE_VAL,                   \
  57         }
  58
  59 /* Define a feature with signed values */
  60 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  61         __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  62
  63 /* Define a feature with unsigned value */
  64 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  65         __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  66
  67 #define ARM64_FTR_END                                   \
  68         {                                               \
  69                 .width = 0,                             \
  70         }
  71
  72 /* meta feature for alternatives */
  73 static bool __maybe_unused
  74 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
  75
  76 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  77         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  78         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  79         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
  80         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  81         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  82         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  83         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  84         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  85         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
  86         ARM64_FTR_END,
  87 };
  88
  89 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  90         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  91         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
  92         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  93         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  94         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  95         /* Linux doesn't care about the EL3 */
  96         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
  97         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
  98         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
  99         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 100         ARM64_FTR_END,
 101 };
 102
 103 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 104         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 105         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 106         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 107         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 108         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 109         /* Linux shouldn't care about secure memory */
 110         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 111         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 112         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 113         /*
 114          * Differing PARange is fine as long as all peripherals and memory are mapped
 115          * within the minimum PARange of all CPUs
 116          */
 117         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 118         ARM64_FTR_END,
 119 };
 120
 121 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 122         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 123         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 129         ARM64_FTR_END,
 130 };
 131
 132 static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 133         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 134         ARM64_FTR_END,
 135 };
 136
 137 static struct arm64_ftr_bits ftr_ctr[] = {
 138         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),      /* RAO */
 139         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
 140         U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),        /* CWG */
 141         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
 142         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
 143         /*
 144          * Linux can handle differing I-cache policies. Userspace JITs will
 145          * make use of *minLine
 146          */
 147         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),   /* L1Ip */
 148         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),        /* RAZ */
 149         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),  /* IminLine */
 150         ARM64_FTR_END,
 151 };
 152
 153 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
 154         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),        /* InnerShr */
 155         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
 156         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),        /* AuxReg */
 157         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),        /* TCM */
 158         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* ShareLvl */
 159         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
 160         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
 161         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
 162         ARM64_FTR_END,
 163 };
 164
 165 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 166         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 167         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 168         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 169         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 170         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 171         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 172         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 173         ARM64_FTR_END,
 174 };
 175
 176 static struct arm64_ftr_bits ftr_mvfr2[] = {
 177         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 178         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* FPMisc */
 179         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* SIMDMisc */
 180         ARM64_FTR_END,
 181 };
 182
 183 static struct arm64_ftr_bits ftr_dczid[] = {
 184         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0),        /* RAZ */
 185         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1),         /* DZP */
 186         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* BS */
 187         ARM64_FTR_END,
 188 };
 189
 190
 191 static struct arm64_ftr_bits ftr_id_isar5[] = {
 192         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0),        /* RAZ */
 194         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 196         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 197         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 198         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 199         ARM64_FTR_END,
 200 };
 201
 202 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
 203         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 204         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* ac2 */
 205         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* RAZ */
 206         ARM64_FTR_END,
 207 };
 208
 209 static struct arm64_ftr_bits ftr_id_pfr0[] = {
 210         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0),       /* RAZ */
 211         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* State3 */
 212         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),         /* State2 */
 213         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* State1 */
 214         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* State0 */
 215         ARM64_FTR_END,
 216 };
 217
 218 /*
 219  * Common ftr bits for a 32bit register with all hidden, strict
 220  * attributes, with 4bit feature fields and a default safe value of
 221  * 0. Covers the following 32bit registers:
 222  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 223  */
 224 static struct arm64_ftr_bits ftr_generic_32bits[] = {
 225         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 226         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 227         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 228         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 229         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 230         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 231         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 232         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 233         ARM64_FTR_END,
 234 };
 235
 236 static struct arm64_ftr_bits ftr_generic[] = {
 237         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 238         ARM64_FTR_END,
 239 };
 240
 241 static struct arm64_ftr_bits ftr_generic32[] = {
 242         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
 243         ARM64_FTR_END,
 244 };
 245
 246 static struct arm64_ftr_bits ftr_aa64raz[] = {
 247         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 248         ARM64_FTR_END,
 249 };
 250
 251 #define ARM64_FTR_REG(id, table)                \
 252         {                                       \
 253                 .sys_id = id,                   \
 254                 .name = #id,                    \
 255                 .ftr_bits = &((table)[0]),      \
 256         }
 257
 258 static struct arm64_ftr_reg arm64_ftr_regs[] = {
 259
 260         /* Op1 = 0, CRn = 0, CRm = 1 */
 261         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 262         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 263         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
 264         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 265         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 266         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 267         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 268
 269         /* Op1 = 0, CRn = 0, CRm = 2 */
 270         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 271         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 272         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 273         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 274         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 275         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 276         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 277
 278         /* Op1 = 0, CRn = 0, CRm = 3 */
 279         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 280         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 281         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 282
 283         /* Op1 = 0, CRn = 0, CRm = 4 */
 284         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 285         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
 286
 287         /* Op1 = 0, CRn = 0, CRm = 5 */
 288         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 289         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
 290
 291         /* Op1 = 0, CRn = 0, CRm = 6 */
 292         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 293         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
 294
 295         /* Op1 = 0, CRn = 0, CRm = 7 */
 296         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 297         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 298         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 299
 300         /* Op1 = 3, CRn = 0, CRm = 0 */
 301         ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
 302         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 303
 304         /* Op1 = 3, CRn = 14, CRm = 0 */
 305         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
 306 };
 307
 308 static int search_cmp_ftr_reg(const void *id, const void *regp)
 309 {
 310         return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
 311 }
 312
 313 /*
 314  * get_arm64_ftr_reg - Lookup a feature register entry using its
 315  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 316  * ascending order of sys_id , we use binary search to find a matching
 317  * entry.
 318  *
 319  * returns - Upon success,  matching ftr_reg entry for id.
 320  *         - NULL on failure. It is upto the caller to decide
 321  *           the impact of a failure.
 322  */
 323 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 324 {
 325         return bsearch((const void *)(unsigned long)sys_id,
 326                         arm64_ftr_regs,
 327                         ARRAY_SIZE(arm64_ftr_regs),
 328                         sizeof(arm64_ftr_regs[0]),
 329                         search_cmp_ftr_reg);
 330 }
 331
 332 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
 333 {
 334         u64 mask = arm64_ftr_mask(ftrp);
 335
 336         reg &= ~mask;
 337         reg |= (ftr_val << ftrp->shift) & mask;
 338         return reg;
 339 }
 340
 341 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
 342 {
 343         s64 ret = 0;
 344
 345         switch (ftrp->type) {
 346         case FTR_EXACT:
 347                 ret = ftrp->safe_val;
 348                 break;
 349         case FTR_LOWER_SAFE:
 350                 ret = new < cur ? new : cur;
 351                 break;
 352         case FTR_HIGHER_SAFE:
 353                 ret = new > cur ? new : cur;
 354                 break;
 355         default:
 356                 BUG();
 357         }
 358
 359         return ret;
 360 }
 361
 362 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
 363 {
 364         return ((const struct arm64_ftr_reg *)a)->sys_id -
 365                  ((const struct arm64_ftr_reg *)b)->sys_id;
 366 }
 367
 368 static void __init swap_ftr_regs(void *a, void *b, int size)
 369 {
 370         struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
 371         *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
 372         *(struct arm64_ftr_reg *)b = tmp;
 373 }
 374
 375 static void __init sort_ftr_regs(void)
 376 {
 377         /* Keep the array sorted so that we can do the binary search */
 378         sort(arm64_ftr_regs,
 379                 ARRAY_SIZE(arm64_ftr_regs),
 380                 sizeof(arm64_ftr_regs[0]),
 381                 sort_cmp_ftr_regs,
 382                 swap_ftr_regs);
 383 }
 384
 385 /*
 386  * Initialise the CPU feature register from Boot CPU values.
 387  * Also initiliases the strict_mask for the register.
 388  */
 389 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 390 {
 391         u64 val = 0;
 392         u64 strict_mask = ~0x0ULL;
 393         struct arm64_ftr_bits *ftrp;
 394         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 395
 396         BUG_ON(!reg);
 397
 398         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 399                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 400
 401                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 402                 if (!ftrp->strict)
 403                         strict_mask &= ~arm64_ftr_mask(ftrp);
 404         }
 405         reg->sys_val = val;
 406         reg->strict_mask = strict_mask;
 407 }
 408
 409 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 410 {
 411         /* Before we start using the tables, make sure it is sorted */
 412         sort_ftr_regs();
 413
 414         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 415         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 416         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 417         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 418         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 419         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 420         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 421         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 422         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 423         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 424         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 425         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 426         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 427         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 428         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 429         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 430         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 431         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 432         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 433         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 434         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 435         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 436         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 437         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 438         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 439         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 440         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 441         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 442 }
 443
 444 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 445 {
 446         struct arm64_ftr_bits *ftrp;
 447
 448         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 449                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 450                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 451
 452                 if (ftr_cur == ftr_new)
 453                         continue;
 454                 /* Find a safe value */
 455                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 456                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 457         }
 458
 459 }
 460
 461 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 462 {
 463         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 464
 465         BUG_ON(!regp);
 466         update_cpu_ftr_reg(regp, val);
 467         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 468                 return 0;
 469         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 470                         regp->name, boot, cpu, val);
 471         return 1;
 472 }
 473
 474 /*
 475  * Update system wide CPU feature registers with the values from a
 476  * non-boot CPU. Also performs SANITY checks to make sure that there
 477  * aren't any insane variations from that of the boot CPU.
 478  */
 479 void update_cpu_features(int cpu,
 480                          struct cpuinfo_arm64 *info,
 481                          struct cpuinfo_arm64 *boot)
 482 {
 483         int taint = 0;
 484
 485         /*
 486          * The kernel can handle differing I-cache policies, but otherwise
 487          * caches should look identical. Userspace JITs will make use of
 488          * *minLine.
 489          */
 490         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 491                                       info->reg_ctr, boot->reg_ctr);
 492
 493         /*
 494          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 495          * could result in too much or too little memory being zeroed if a
 496          * process is preempted and migrated between CPUs.
 497          */
 498         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 499                                       info->reg_dczid, boot->reg_dczid);
 500
 501         /* If different, timekeeping will be broken (especially with KVM) */
 502         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 503                                       info->reg_cntfrq, boot->reg_cntfrq);
 504
 505         /*
 506          * The kernel uses self-hosted debug features and expects CPUs to
 507          * support identical debug features. We presently need CTX_CMPs, WRPs,
 508          * and BRPs to be identical.
 509          * ID_AA64DFR1 is currently RES0.
 510          */
 511         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 512                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 513         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 514                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 515         /*
 516          * Even in big.LITTLE, processors should be identical instruction-set
 517          * wise.
 518          */
 519         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 520                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 521         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 522                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 523
 524         /*
 525          * Differing PARange support is fine as long as all peripherals and
 526          * memory are mapped within the minimum PARange of all CPUs.
 527          * Linux should not care about secure memory.
 528          */
 529         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 530                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 531         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 532                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 533         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 534                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 535
 536         /*
 537          * EL3 is not our concern.
 538          * ID_AA64PFR1 is currently RES0.
 539          */
 540         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 541                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 542         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 543                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 544
 545         /*
 546          * If we have AArch32, we care about 32-bit features for compat. These
 547          * registers should be RES0 otherwise.
 548          */
 549         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 550                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 551         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 552                                         info->reg_id_isar0, boot->reg_id_isar0);
 553         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 554                                         info->reg_id_isar1, boot->reg_id_isar1);
 555         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 556                                         info->reg_id_isar2, boot->reg_id_isar2);
 557         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 558                                         info->reg_id_isar3, boot->reg_id_isar3);
 559         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 560                                         info->reg_id_isar4, boot->reg_id_isar4);
 561         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 562                                         info->reg_id_isar5, boot->reg_id_isar5);
 563
 564         /*
 565          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 566          * ACTLR formats could differ across CPUs and therefore would have to
 567          * be trapped for virtualization anyway.
 568          */
 569         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 570                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 571         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 572                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 573         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 574                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 575         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 576                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 577         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 578                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 579         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 580                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 581         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 582                                         info->reg_mvfr0, boot->reg_mvfr0);
 583         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 584                                         info->reg_mvfr1, boot->reg_mvfr1);
 585         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 586                                         info->reg_mvfr2, boot->reg_mvfr2);
 587
 588         /*
 589          * Mismatched CPU features are a recipe for disaster. Don't even
 590          * pretend to support them.
 591          */
 592         WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
 593                         "Unsupported CPU feature variation.\n");
 594 }
 595
 596 u64 read_system_reg(u32 id)
 597 {
 598         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 599
 600         /* We shouldn't get a request for an unsupported register */
 601         BUG_ON(!regp);
 602         return regp->sys_val;
 603 }
 604
 605 #include <linux/irqchip/arm-gic-v3.h>
 606
 607 static bool
 608 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 609 {
 610         int val = cpuid_feature_extract_field(reg, entry->field_pos);
 611
 612         return val >= entry->min_field_value;
 613 }
 614
 615 static bool
 616 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
 617 {
 618         u64 val;
 619
 620         val = read_system_reg(entry->sys_reg);
 621         return feature_matches(val, entry);
 622 }
 623
 624 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
 625 {
 626         bool has_sre;
 627
 628         if (!has_cpuid_feature(entry))
 629                 return false;
 630
 631         has_sre = gic_enable_sre();
 632         if (!has_sre)
 633                 pr_warn_once("%s present but disabled by higher exception level\n",
 634                              entry->desc);
 635
 636         return has_sre;
 637 }
 638
 639 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
 640 {
 641         u32 midr = read_cpuid_id();
 642         u32 rv_min, rv_max;
 643
 644         /* Cavium ThunderX pass 1.x and 2.x */
 645         rv_min = 0;
 646         rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
 647
 648         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
 649 }
 650
 651 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
 652 {
 653         return is_kernel_in_hyp_mode();
 654 }
 655
 656 static const struct arm64_cpu_capabilities arm64_features[] = {
 657         {
 658                 .desc = "GIC system register CPU interface",
 659                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 660                 .matches = has_useable_gicv3_cpuif,
 661                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 662                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 663                 .min_field_value = 1,
 664         },
 665 #ifdef CONFIG_ARM64_PAN
 666         {
 667                 .desc = "Privileged Access Never",
 668                 .capability = ARM64_HAS_PAN,
 669                 .matches = has_cpuid_feature,
 670                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 671                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 672                 .min_field_value = 1,
 673                 .enable = cpu_enable_pan,
 674         },
 675 #endif /* CONFIG_ARM64_PAN */
 676 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 677         {
 678                 .desc = "LSE atomic instructions",
 679                 .capability = ARM64_HAS_LSE_ATOMICS,
 680                 .matches = has_cpuid_feature,
 681                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 682                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 683                 .min_field_value = 2,
 684         },
 685 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 686         {
 687                 .desc = "Software prefetching using PRFM",
 688                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 689                 .matches = has_no_hw_prefetch,
 690         },
 691 #ifdef CONFIG_ARM64_UAO
 692         {
 693                 .desc = "User Access Override",
 694                 .capability = ARM64_HAS_UAO,
 695                 .matches = has_cpuid_feature,
 696                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
 697                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
 698                 .min_field_value = 1,
 699                 .enable = cpu_enable_uao,
 700         },
 701 #endif /* CONFIG_ARM64_UAO */
 702 #ifdef CONFIG_ARM64_PAN
 703         {
 704                 .capability = ARM64_ALT_PAN_NOT_UAO,
 705                 .matches = cpufeature_pan_not_uao,
 706         },
 707 #endif /* CONFIG_ARM64_PAN */
 708         {
 709                 .desc = "Virtualization Host Extensions",
 710                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
 711                 .matches = runs_at_el2,
 712         },
 713         {},
 714 };
 715
 716 #define HWCAP_CAP(reg, field, min_value, type, cap)             \
 717         {                                                       \
 718                 .desc = #cap,                                   \
 719                 .matches = has_cpuid_feature,                   \
 720                 .sys_reg = reg,                                 \
 721                 .field_pos = field,                             \
 722                 .min_field_value = min_value,                   \
 723                 .hwcap_type = type,                             \
 724                 .hwcap = cap,                                   \
 725         }
 726
 727 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
 728         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
 729         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
 730         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
 731         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
 732         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
 733         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
 734         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
 735         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
 736 #ifdef CONFIG_COMPAT
 737         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 738         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 739         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 740         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 741         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 742 #endif
 743         {},
 744 };
 745
 746 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
 747 {
 748         switch (cap->hwcap_type) {
 749         case CAP_HWCAP:
 750                 elf_hwcap |= cap->hwcap;
 751                 break;
 752 #ifdef CONFIG_COMPAT
 753         case CAP_COMPAT_HWCAP:
 754                 compat_elf_hwcap |= (u32)cap->hwcap;
 755                 break;
 756         case CAP_COMPAT_HWCAP2:
 757                 compat_elf_hwcap2 |= (u32)cap->hwcap;
 758                 break;
 759 #endif
 760         default:
 761                 WARN_ON(1);
 762                 break;
 763         }
 764 }
 765
 766 /* Check if we have a particular HWCAP enabled */
 767 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
 768 {
 769         bool rc;
 770
 771         switch (cap->hwcap_type) {
 772         case CAP_HWCAP:
 773                 rc = (elf_hwcap & cap->hwcap) != 0;
 774                 break;
 775 #ifdef CONFIG_COMPAT
 776         case CAP_COMPAT_HWCAP:
 777                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
 778                 break;
 779         case CAP_COMPAT_HWCAP2:
 780                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
 781                 break;
 782 #endif
 783         default:
 784                 WARN_ON(1);
 785                 rc = false;
 786         }
 787
 788         return rc;
 789 }
 790
 791 static void __init setup_cpu_hwcaps(void)
 792 {
 793         int i;
 794         const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
 795
 796         for (i = 0; hwcaps[i].matches; i++)
 797                 if (hwcaps[i].matches(&hwcaps[i]))
 798                         cap_set_hwcap(&hwcaps[i]);
 799 }
 800
 801 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 802                             const char *info)
 803 {
 804         int i;
 805
 806         for (i = 0; caps[i].matches; i++) {
 807                 if (!caps[i].matches(&caps[i]))
 808                         continue;
 809
 810                 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
 811                         pr_info("%s %s\n", info, caps[i].desc);
 812                 cpus_set_cap(caps[i].capability);
 813         }
 814 }
 815
 816 /*
 817  * Run through the enabled capabilities and enable() it on all active
 818  * CPUs
 819  */
 820 static void __init
 821 enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 822 {
 823         int i;
 824
 825         for (i = 0; caps[i].matches; i++)
 826                 if (caps[i].enable && cpus_have_cap(caps[i].capability))
 827                         on_each_cpu(caps[i].enable, NULL, true);
 828 }
 829
 830 #ifdef CONFIG_HOTPLUG_CPU
 831
 832 /*
 833  * Flag to indicate if we have computed the system wide
 834  * capabilities based on the boot time active CPUs. This
 835  * will be used to determine if a new booting CPU should
 836  * go through the verification process to make sure that it
 837  * supports the system capabilities, without using a hotplug
 838  * notifier.
 839  */
 840 static bool sys_caps_initialised;
 841
 842 static inline void set_sys_caps_initialised(void)
 843 {
 844         sys_caps_initialised = true;
 845 }
 846
 847 /*
 848  * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
 849  */
 850 static u64 __raw_read_system_reg(u32 sys_id)
 851 {
 852         switch (sys_id) {
 853         case SYS_ID_PFR0_EL1:           return read_cpuid(SYS_ID_PFR0_EL1);
 854         case SYS_ID_PFR1_EL1:           return read_cpuid(SYS_ID_PFR1_EL1);
 855         case SYS_ID_DFR0_EL1:           return read_cpuid(SYS_ID_DFR0_EL1);
 856         case SYS_ID_MMFR0_EL1:          return read_cpuid(SYS_ID_MMFR0_EL1);
 857         case SYS_ID_MMFR1_EL1:          return read_cpuid(SYS_ID_MMFR1_EL1);
 858         case SYS_ID_MMFR2_EL1:          return read_cpuid(SYS_ID_MMFR2_EL1);
 859         case SYS_ID_MMFR3_EL1:          return read_cpuid(SYS_ID_MMFR3_EL1);
 860         case SYS_ID_ISAR0_EL1:          return read_cpuid(SYS_ID_ISAR0_EL1);
 861         case SYS_ID_ISAR1_EL1:          return read_cpuid(SYS_ID_ISAR1_EL1);
 862         case SYS_ID_ISAR2_EL1:          return read_cpuid(SYS_ID_ISAR2_EL1);
 863         case SYS_ID_ISAR3_EL1:          return read_cpuid(SYS_ID_ISAR3_EL1);
 864         case SYS_ID_ISAR4_EL1:          return read_cpuid(SYS_ID_ISAR4_EL1);
 865         case SYS_ID_ISAR5_EL1:          return read_cpuid(SYS_ID_ISAR4_EL1);
 866         case SYS_MVFR0_EL1:             return read_cpuid(SYS_MVFR0_EL1);
 867         case SYS_MVFR1_EL1:             return read_cpuid(SYS_MVFR1_EL1);
 868         case SYS_MVFR2_EL1:             return read_cpuid(SYS_MVFR2_EL1);
 869
 870         case SYS_ID_AA64PFR0_EL1:       return read_cpuid(SYS_ID_AA64PFR0_EL1);
 871         case SYS_ID_AA64PFR1_EL1:       return read_cpuid(SYS_ID_AA64PFR0_EL1);
 872         case SYS_ID_AA64DFR0_EL1:       return read_cpuid(SYS_ID_AA64DFR0_EL1);
 873         case SYS_ID_AA64DFR1_EL1:       return read_cpuid(SYS_ID_AA64DFR0_EL1);
 874         case SYS_ID_AA64MMFR0_EL1:      return read_cpuid(SYS_ID_AA64MMFR0_EL1);
 875         case SYS_ID_AA64MMFR1_EL1:      return read_cpuid(SYS_ID_AA64MMFR1_EL1);
 876         case SYS_ID_AA64MMFR2_EL1:      return read_cpuid(SYS_ID_AA64MMFR2_EL1);
 877         case SYS_ID_AA64ISAR0_EL1:      return read_cpuid(SYS_ID_AA64ISAR0_EL1);
 878         case SYS_ID_AA64ISAR1_EL1:      return read_cpuid(SYS_ID_AA64ISAR1_EL1);
 879
 880         case SYS_CNTFRQ_EL0:            return read_cpuid(SYS_CNTFRQ_EL0);
 881         case SYS_CTR_EL0:               return read_cpuid(SYS_CTR_EL0);
 882         case SYS_DCZID_EL0:             return read_cpuid(SYS_DCZID_EL0);
 883         default:
 884                 BUG();
 885                 return 0;
 886         }
 887 }
 888
 889 /*
 890  * Park the CPU which doesn't have the capability as advertised
 891  * by the system.
 892  */
 893 static void fail_incapable_cpu(char *cap_type,
 894                                  const struct arm64_cpu_capabilities *cap)
 895 {
 896         int cpu = smp_processor_id();
 897
 898         pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
 899         /* Mark this CPU absent */
 900         set_cpu_present(cpu, 0);
 901
 902         /* Check if we can park ourselves */
 903         if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
 904                 cpu_ops[cpu]->cpu_die(cpu);
 905         asm(
 906         "1:     wfe\n"
 907         "       wfi\n"
 908         "       b       1b");
 909 }
 910
 911 /*
 912  * Run through the enabled system capabilities and enable() it on this CPU.
 913  * The capabilities were decided based on the available CPUs at the boot time.
 914  * Any new CPU should match the system wide status of the capability. If the
 915  * new CPU doesn't have a capability which the system now has enabled, we
 916  * cannot do anything to fix it up and could cause unexpected failures. So
 917  * we park the CPU.
 918  */
 919 void verify_local_cpu_capabilities(void)
 920 {
 921         int i;
 922         const struct arm64_cpu_capabilities *caps;
 923
 924         /*
 925          * If we haven't computed the system capabilities, there is nothing
 926          * to verify.
 927          */
 928         if (!sys_caps_initialised)
 929                 return;
 930
 931         caps = arm64_features;
 932         for (i = 0; caps[i].matches; i++) {
 933                 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
 934                         continue;
 935                 /*
 936                  * If the new CPU misses an advertised feature, we cannot proceed
 937                  * further, park the cpu.
 938                  */
 939                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 940                         fail_incapable_cpu("arm64_features", &caps[i]);
 941                 if (caps[i].enable)
 942                         caps[i].enable(NULL);
 943         }
 944
 945         for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
 946                 if (!cpus_have_hwcap(&caps[i]))
 947                         continue;
 948                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 949                         fail_incapable_cpu("arm64_hwcaps", &caps[i]);
 950         }
 951 }
 952
 953 #else   /* !CONFIG_HOTPLUG_CPU */
 954
 955 static inline void set_sys_caps_initialised(void)
 956 {
 957 }
 958
 959 #endif  /* CONFIG_HOTPLUG_CPU */
 960
 961 static void __init setup_feature_capabilities(void)
 962 {
 963         update_cpu_capabilities(arm64_features, "detected feature:");
 964         enable_cpu_capabilities(arm64_features);
 965 }
 966
 967 void __init setup_cpu_features(void)
 968 {
 969         u32 cwg;
 970         int cls;
 971
 972         /* Set the CPU feature capabilies */
 973         setup_feature_capabilities();
 974         setup_cpu_hwcaps();
 975
 976         /* Advertise that we have computed the system capabilities */
 977         set_sys_caps_initialised();
 978
 979         /*
 980          * Check for sane CTR_EL0.CWG value.
 981          */
 982         cwg = cache_type_cwg();
 983         cls = cache_line_size();
 984         if (!cwg)
 985                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
 986                         cls);
 987         if (L1_CACHE_BYTES < cls)
 988                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
 989                         L1_CACHE_BYTES, cls);
 990 }
 991
 992 static bool __maybe_unused
 993 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
 994 {
 995         return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
 996 }