2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/sort.h>
24 #include <linux/stop_machine.h>
25 #include <linux/types.h>
27 #include <asm/cpufeature.h>
28 #include <asm/cpu_ops.h>
29 #include <asm/processor.h>
30 #include <asm/sysreg.h>
33 unsigned long elf_hwcap __read_mostly;
34 EXPORT_SYMBOL_GPL(elf_hwcap);
37 #define COMPAT_ELF_HWCAP_DEFAULT \
38 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
39 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
40 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
41 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
42 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
44 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
45 unsigned int compat_elf_hwcap2 __read_mostly;
48 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
49 EXPORT_SYMBOL(cpu_hwcaps);
51 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
58 .safe_val = SAFE_VAL, \
61 /* Define a feature with signed values */
62 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
63 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
65 /* Define a feature with unsigned value */
66 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
67 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
69 #define ARM64_FTR_END \
74 /* meta feature for alternatives */
75 static bool __maybe_unused
76 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
78 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
79 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
80 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
85 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
86 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
87 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
91 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
92 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
93 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
94 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
95 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
96 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
97 /* Linux doesn't care about the EL3 */
98 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
99 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
100 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
101 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
105 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
106 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
107 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
108 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
109 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
110 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
111 /* Linux shouldn't care about secure memory */
112 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
113 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
114 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
116 * Differing PARange is fine as long as all peripherals and memory are mapped
117 * within the minimum PARange of all CPUs
119 U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
123 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
124 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
125 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
134 static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
135 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
139 static struct arm64_ftr_bits ftr_ctr[] = {
140 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
141 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
142 U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
143 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
144 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
146 * Linux can handle differing I-cache policies. Userspace JITs will
147 * make use of *minLine
149 U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
150 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
151 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
155 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
156 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), /* InnerShr */
157 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
158 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
159 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
160 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
161 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
162 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
163 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
167 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
168 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
169 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
170 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
171 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
172 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
173 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
174 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
178 static struct arm64_ftr_bits ftr_mvfr2[] = {
179 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
180 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
181 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
185 static struct arm64_ftr_bits ftr_dczid[] = {
186 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
187 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
188 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
193 static struct arm64_ftr_bits ftr_id_isar5[] = {
194 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
196 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
204 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
205 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
206 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
207 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
211 static struct arm64_ftr_bits ftr_id_pfr0[] = {
212 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
213 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
214 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
215 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
216 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
221 * Common ftr bits for a 32bit register with all hidden, strict
222 * attributes, with 4bit feature fields and a default safe value of
223 * 0. Covers the following 32bit registers:
224 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
226 static struct arm64_ftr_bits ftr_generic_32bits[] = {
227 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
228 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
229 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
230 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
231 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
232 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
233 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
234 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
238 static struct arm64_ftr_bits ftr_generic[] = {
239 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
243 static struct arm64_ftr_bits ftr_generic32[] = {
244 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
248 static struct arm64_ftr_bits ftr_aa64raz[] = {
249 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
253 #define ARM64_FTR_REG(id, table) \
257 .ftr_bits = &((table)[0]), \
260 static struct arm64_ftr_reg arm64_ftr_regs[] = {
262 /* Op1 = 0, CRn = 0, CRm = 1 */
263 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
264 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
265 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
266 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
267 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
268 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
269 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
271 /* Op1 = 0, CRn = 0, CRm = 2 */
272 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
273 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
274 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
275 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
276 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
277 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
278 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
280 /* Op1 = 0, CRn = 0, CRm = 3 */
281 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
282 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
283 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
285 /* Op1 = 0, CRn = 0, CRm = 4 */
286 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
287 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
289 /* Op1 = 0, CRn = 0, CRm = 5 */
290 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
291 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
293 /* Op1 = 0, CRn = 0, CRm = 6 */
294 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
295 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
297 /* Op1 = 0, CRn = 0, CRm = 7 */
298 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
299 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
300 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
302 /* Op1 = 3, CRn = 0, CRm = 0 */
303 ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
304 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
306 /* Op1 = 3, CRn = 14, CRm = 0 */
307 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
310 static int search_cmp_ftr_reg(const void *id, const void *regp)
312 return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
316 * get_arm64_ftr_reg - Lookup a feature register entry using its
317 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
318 * ascending order of sys_id , we use binary search to find a matching
321 * returns - Upon success, matching ftr_reg entry for id.
322 * - NULL on failure. It is upto the caller to decide
323 * the impact of a failure.
325 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
327 return bsearch((const void *)(unsigned long)sys_id,
329 ARRAY_SIZE(arm64_ftr_regs),
330 sizeof(arm64_ftr_regs[0]),
334 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
336 u64 mask = arm64_ftr_mask(ftrp);
339 reg |= (ftr_val << ftrp->shift) & mask;
343 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
347 switch (ftrp->type) {
349 ret = ftrp->safe_val;
352 ret = new < cur ? new : cur;
354 case FTR_HIGHER_SAFE:
355 ret = new > cur ? new : cur;
364 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
366 return ((const struct arm64_ftr_reg *)a)->sys_id -
367 ((const struct arm64_ftr_reg *)b)->sys_id;
370 static void __init swap_ftr_regs(void *a, void *b, int size)
372 struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
373 *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
374 *(struct arm64_ftr_reg *)b = tmp;
377 static void __init sort_ftr_regs(void)
379 /* Keep the array sorted so that we can do the binary search */
381 ARRAY_SIZE(arm64_ftr_regs),
382 sizeof(arm64_ftr_regs[0]),
388 * Initialise the CPU feature register from Boot CPU values.
389 * Also initiliases the strict_mask for the register.
391 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
394 u64 strict_mask = ~0x0ULL;
395 struct arm64_ftr_bits *ftrp;
396 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
400 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
401 s64 ftr_new = arm64_ftr_value(ftrp, new);
403 val = arm64_ftr_set_value(ftrp, val, ftr_new);
405 strict_mask &= ~arm64_ftr_mask(ftrp);
408 reg->strict_mask = strict_mask;
411 void __init init_cpu_features(struct cpuinfo_arm64 *info)
413 /* Before we start using the tables, make sure it is sorted */
416 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
417 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
418 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
419 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
420 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
421 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
422 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
423 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
424 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
425 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
426 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
427 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
428 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
429 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
430 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
431 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
432 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
433 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
434 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
435 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
436 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
437 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
438 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
439 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
440 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
441 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
442 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
443 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
446 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
448 struct arm64_ftr_bits *ftrp;
450 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
451 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
452 s64 ftr_new = arm64_ftr_value(ftrp, new);
454 if (ftr_cur == ftr_new)
456 /* Find a safe value */
457 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
458 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
463 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
465 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
468 update_cpu_ftr_reg(regp, val);
469 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
471 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
472 regp->name, boot, cpu, val);
477 * Update system wide CPU feature registers with the values from a
478 * non-boot CPU. Also performs SANITY checks to make sure that there
479 * aren't any insane variations from that of the boot CPU.
481 void update_cpu_features(int cpu,
482 struct cpuinfo_arm64 *info,
483 struct cpuinfo_arm64 *boot)
488 * The kernel can handle differing I-cache policies, but otherwise
489 * caches should look identical. Userspace JITs will make use of
492 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
493 info->reg_ctr, boot->reg_ctr);
496 * Userspace may perform DC ZVA instructions. Mismatched block sizes
497 * could result in too much or too little memory being zeroed if a
498 * process is preempted and migrated between CPUs.
500 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
501 info->reg_dczid, boot->reg_dczid);
503 /* If different, timekeeping will be broken (especially with KVM) */
504 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
505 info->reg_cntfrq, boot->reg_cntfrq);
508 * The kernel uses self-hosted debug features and expects CPUs to
509 * support identical debug features. We presently need CTX_CMPs, WRPs,
510 * and BRPs to be identical.
511 * ID_AA64DFR1 is currently RES0.
513 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
514 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
515 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
516 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
518 * Even in big.LITTLE, processors should be identical instruction-set
521 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
522 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
523 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
524 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
527 * Differing PARange support is fine as long as all peripherals and
528 * memory are mapped within the minimum PARange of all CPUs.
529 * Linux should not care about secure memory.
531 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
532 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
533 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
534 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
535 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
536 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
539 * EL3 is not our concern.
540 * ID_AA64PFR1 is currently RES0.
542 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
543 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
544 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
545 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
548 * If we have AArch32, we care about 32-bit features for compat. These
549 * registers should be RES0 otherwise.
551 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
552 info->reg_id_dfr0, boot->reg_id_dfr0);
553 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
554 info->reg_id_isar0, boot->reg_id_isar0);
555 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
556 info->reg_id_isar1, boot->reg_id_isar1);
557 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
558 info->reg_id_isar2, boot->reg_id_isar2);
559 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
560 info->reg_id_isar3, boot->reg_id_isar3);
561 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
562 info->reg_id_isar4, boot->reg_id_isar4);
563 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
564 info->reg_id_isar5, boot->reg_id_isar5);
567 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
568 * ACTLR formats could differ across CPUs and therefore would have to
569 * be trapped for virtualization anyway.
571 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
572 info->reg_id_mmfr0, boot->reg_id_mmfr0);
573 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
574 info->reg_id_mmfr1, boot->reg_id_mmfr1);
575 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
576 info->reg_id_mmfr2, boot->reg_id_mmfr2);
577 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
578 info->reg_id_mmfr3, boot->reg_id_mmfr3);
579 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
580 info->reg_id_pfr0, boot->reg_id_pfr0);
581 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
582 info->reg_id_pfr1, boot->reg_id_pfr1);
583 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
584 info->reg_mvfr0, boot->reg_mvfr0);
585 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
586 info->reg_mvfr1, boot->reg_mvfr1);
587 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
588 info->reg_mvfr2, boot->reg_mvfr2);
591 * Mismatched CPU features are a recipe for disaster. Don't even
592 * pretend to support them.
594 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
595 "Unsupported CPU feature variation.\n");
598 u64 read_system_reg(u32 id)
600 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
602 /* We shouldn't get a request for an unsupported register */
604 return regp->sys_val;
607 #include <linux/irqchip/arm-gic-v3.h>
610 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
612 int val = cpuid_feature_extract_field(reg, entry->field_pos);
614 return val >= entry->min_field_value;
618 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
622 val = read_system_reg(entry->sys_reg);
623 return feature_matches(val, entry);
626 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
630 if (!has_cpuid_feature(entry))
633 has_sre = gic_enable_sre();
635 pr_warn_once("%s present but disabled by higher exception level\n",
641 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
643 u32 midr = read_cpuid_id();
646 /* Cavium ThunderX pass 1.x and 2.x */
648 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
650 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
653 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
655 return is_kernel_in_hyp_mode();
658 static const struct arm64_cpu_capabilities arm64_features[] = {
660 .desc = "GIC system register CPU interface",
661 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
662 .matches = has_useable_gicv3_cpuif,
663 .sys_reg = SYS_ID_AA64PFR0_EL1,
664 .field_pos = ID_AA64PFR0_GIC_SHIFT,
665 .min_field_value = 1,
667 #ifdef CONFIG_ARM64_PAN
669 .desc = "Privileged Access Never",
670 .capability = ARM64_HAS_PAN,
671 .matches = has_cpuid_feature,
672 .sys_reg = SYS_ID_AA64MMFR1_EL1,
673 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
674 .min_field_value = 1,
675 .enable = cpu_enable_pan,
677 #endif /* CONFIG_ARM64_PAN */
678 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
680 .desc = "LSE atomic instructions",
681 .capability = ARM64_HAS_LSE_ATOMICS,
682 .matches = has_cpuid_feature,
683 .sys_reg = SYS_ID_AA64ISAR0_EL1,
684 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
685 .min_field_value = 2,
687 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
689 .desc = "Software prefetching using PRFM",
690 .capability = ARM64_HAS_NO_HW_PREFETCH,
691 .matches = has_no_hw_prefetch,
693 #ifdef CONFIG_ARM64_UAO
695 .desc = "User Access Override",
696 .capability = ARM64_HAS_UAO,
697 .matches = has_cpuid_feature,
698 .sys_reg = SYS_ID_AA64MMFR2_EL1,
699 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
700 .min_field_value = 1,
701 .enable = cpu_enable_uao,
703 #endif /* CONFIG_ARM64_UAO */
704 #ifdef CONFIG_ARM64_PAN
706 .capability = ARM64_ALT_PAN_NOT_UAO,
707 .matches = cpufeature_pan_not_uao,
709 #endif /* CONFIG_ARM64_PAN */
711 .desc = "Virtualization Host Extensions",
712 .capability = ARM64_HAS_VIRT_HOST_EXTN,
713 .matches = runs_at_el2,
718 #define HWCAP_CAP(reg, field, min_value, type, cap) \
721 .matches = has_cpuid_feature, \
723 .field_pos = field, \
724 .min_field_value = min_value, \
725 .hwcap_type = type, \
729 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
730 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
731 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
732 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
733 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
734 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
735 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
736 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
737 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
739 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
740 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
741 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
742 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
743 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
748 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
750 switch (cap->hwcap_type) {
752 elf_hwcap |= cap->hwcap;
755 case CAP_COMPAT_HWCAP:
756 compat_elf_hwcap |= (u32)cap->hwcap;
758 case CAP_COMPAT_HWCAP2:
759 compat_elf_hwcap2 |= (u32)cap->hwcap;
768 /* Check if we have a particular HWCAP enabled */
769 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
773 switch (cap->hwcap_type) {
775 rc = (elf_hwcap & cap->hwcap) != 0;
778 case CAP_COMPAT_HWCAP:
779 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
781 case CAP_COMPAT_HWCAP2:
782 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
793 static void __init setup_cpu_hwcaps(void)
796 const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
798 for (i = 0; hwcaps[i].matches; i++)
799 if (hwcaps[i].matches(&hwcaps[i]))
800 cap_set_hwcap(&hwcaps[i]);
803 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
808 for (i = 0; caps[i].matches; i++) {
809 if (!caps[i].matches(&caps[i]))
812 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
813 pr_info("%s %s\n", info, caps[i].desc);
814 cpus_set_cap(caps[i].capability);
819 * Run through the enabled capabilities and enable() it on all active
823 enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
827 for (i = 0; caps[i].matches; i++)
828 if (caps[i].enable && cpus_have_cap(caps[i].capability))
830 * Use stop_machine() as it schedules the work allowing
831 * us to modify PSTATE, instead of on_each_cpu() which
832 * uses an IPI, giving us a PSTATE that disappears when
835 stop_machine(caps[i].enable, NULL, cpu_online_mask);
838 #ifdef CONFIG_HOTPLUG_CPU
841 * Flag to indicate if we have computed the system wide
842 * capabilities based on the boot time active CPUs. This
843 * will be used to determine if a new booting CPU should
844 * go through the verification process to make sure that it
845 * supports the system capabilities, without using a hotplug
848 static bool sys_caps_initialised;
850 static inline void set_sys_caps_initialised(void)
852 sys_caps_initialised = true;
856 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
858 static u64 __raw_read_system_reg(u32 sys_id)
861 case SYS_ID_PFR0_EL1: return read_cpuid(SYS_ID_PFR0_EL1);
862 case SYS_ID_PFR1_EL1: return read_cpuid(SYS_ID_PFR1_EL1);
863 case SYS_ID_DFR0_EL1: return read_cpuid(SYS_ID_DFR0_EL1);
864 case SYS_ID_MMFR0_EL1: return read_cpuid(SYS_ID_MMFR0_EL1);
865 case SYS_ID_MMFR1_EL1: return read_cpuid(SYS_ID_MMFR1_EL1);
866 case SYS_ID_MMFR2_EL1: return read_cpuid(SYS_ID_MMFR2_EL1);
867 case SYS_ID_MMFR3_EL1: return read_cpuid(SYS_ID_MMFR3_EL1);
868 case SYS_ID_ISAR0_EL1: return read_cpuid(SYS_ID_ISAR0_EL1);
869 case SYS_ID_ISAR1_EL1: return read_cpuid(SYS_ID_ISAR1_EL1);
870 case SYS_ID_ISAR2_EL1: return read_cpuid(SYS_ID_ISAR2_EL1);
871 case SYS_ID_ISAR3_EL1: return read_cpuid(SYS_ID_ISAR3_EL1);
872 case SYS_ID_ISAR4_EL1: return read_cpuid(SYS_ID_ISAR4_EL1);
873 case SYS_ID_ISAR5_EL1: return read_cpuid(SYS_ID_ISAR4_EL1);
874 case SYS_MVFR0_EL1: return read_cpuid(SYS_MVFR0_EL1);
875 case SYS_MVFR1_EL1: return read_cpuid(SYS_MVFR1_EL1);
876 case SYS_MVFR2_EL1: return read_cpuid(SYS_MVFR2_EL1);
878 case SYS_ID_AA64PFR0_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1);
879 case SYS_ID_AA64PFR1_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1);
880 case SYS_ID_AA64DFR0_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1);
881 case SYS_ID_AA64DFR1_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1);
882 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(SYS_ID_AA64MMFR0_EL1);
883 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(SYS_ID_AA64MMFR1_EL1);
884 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(SYS_ID_AA64MMFR2_EL1);
885 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(SYS_ID_AA64ISAR0_EL1);
886 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(SYS_ID_AA64ISAR1_EL1);
888 case SYS_CNTFRQ_EL0: return read_cpuid(SYS_CNTFRQ_EL0);
889 case SYS_CTR_EL0: return read_cpuid(SYS_CTR_EL0);
890 case SYS_DCZID_EL0: return read_cpuid(SYS_DCZID_EL0);
898 * Park the CPU which doesn't have the capability as advertised
901 static void fail_incapable_cpu(char *cap_type,
902 const struct arm64_cpu_capabilities *cap)
904 int cpu = smp_processor_id();
906 pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
907 /* Mark this CPU absent */
908 set_cpu_present(cpu, 0);
910 /* Check if we can park ourselves */
911 if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
912 cpu_ops[cpu]->cpu_die(cpu);
920 * Run through the enabled system capabilities and enable() it on this CPU.
921 * The capabilities were decided based on the available CPUs at the boot time.
922 * Any new CPU should match the system wide status of the capability. If the
923 * new CPU doesn't have a capability which the system now has enabled, we
924 * cannot do anything to fix it up and could cause unexpected failures. So
927 void verify_local_cpu_capabilities(void)
930 const struct arm64_cpu_capabilities *caps;
933 * If we haven't computed the system capabilities, there is nothing
936 if (!sys_caps_initialised)
939 caps = arm64_features;
940 for (i = 0; caps[i].matches; i++) {
941 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
944 * If the new CPU misses an advertised feature, we cannot proceed
945 * further, park the cpu.
947 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
948 fail_incapable_cpu("arm64_features", &caps[i]);
950 caps[i].enable(NULL);
953 for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
954 if (!cpus_have_hwcap(&caps[i]))
956 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
957 fail_incapable_cpu("arm64_hwcaps", &caps[i]);
961 #else /* !CONFIG_HOTPLUG_CPU */
963 static inline void set_sys_caps_initialised(void)
967 #endif /* CONFIG_HOTPLUG_CPU */
969 static void __init setup_feature_capabilities(void)
971 update_cpu_capabilities(arm64_features, "detected feature:");
972 enable_cpu_capabilities(arm64_features);
975 void __init setup_cpu_features(void)
980 /* Set the CPU feature capabilies */
981 setup_feature_capabilities();
984 /* Advertise that we have computed the system capabilities */
985 set_sys_caps_initialised();
988 * Check for sane CTR_EL0.CWG value.
990 cwg = cache_type_cwg();
991 cls = cache_line_size();
993 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
995 if (L1_CACHE_BYTES < cls)
996 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
997 L1_CACHE_BYTES, cls);
1000 static bool __maybe_unused
1001 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
1003 return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));