arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/sort.h>
  23 #include <linux/types.h>
  24 #include <asm/cpu.h>
  25 #include <asm/cpufeature.h>
  26 #include <asm/cpu_ops.h>
  27 #include <asm/processor.h>
  28 #include <asm/sysreg.h>
  29
  30 unsigned long elf_hwcap __read_mostly;
  31 EXPORT_SYMBOL_GPL(elf_hwcap);
  32
  33 #ifdef CONFIG_COMPAT
  34 #define COMPAT_ELF_HWCAP_DEFAULT        \
  35                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  36                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  37                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  38                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  39                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  40                                  COMPAT_HWCAP_LPAE)
  41 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  42 unsigned int compat_elf_hwcap2 __read_mostly;
  43 #endif
  44
  45 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  46
  47 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  48         {                                               \
  49                 .sign = SIGNED,                         \
  50                 .strict = STRICT,                       \
  51                 .type = TYPE,                           \
  52                 .shift = SHIFT,                         \
  53                 .width = WIDTH,                         \
  54                 .safe_val = SAFE_VAL,                   \
  55         }
  56
  57 /* Define a feature with signed values */
  58 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  59         __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  60
  61 /* Define a feature with unsigned value */
  62 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  63         __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  64
  65 #define ARM64_FTR_END                                   \
  66         {                                               \
  67                 .width = 0,                             \
  68         }
  69
  70 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  71         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  72         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  73         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
  74         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  75         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  76         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  77         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  78         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  79         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
  80         ARM64_FTR_END,
  81 };
  82
  83 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  84         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  85         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
  86         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  87         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  88         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  89         /* Linux doesn't care about the EL3 */
  90         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
  91         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
  92         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
  93         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
  94         ARM64_FTR_END,
  95 };
  96
  97 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
  98         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  99         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 100         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 101         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 102         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 103         /* Linux shouldn't care about secure memory */
 104         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 105         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 106         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 107         /*
 108          * Differing PARange is fine as long as all peripherals and memory are mapped
 109          * within the minimum PARange of all CPUs
 110          */
 111         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 112         ARM64_FTR_END,
 113 };
 114
 115 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 116         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 117         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 118         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 119         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 120         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 121         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 122         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 123         ARM64_FTR_END,
 124 };
 125
 126 static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 127         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 128         ARM64_FTR_END,
 129 };
 130
 131 static struct arm64_ftr_bits ftr_ctr[] = {
 132         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),      /* RAO */
 133         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
 134         U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),        /* CWG */
 135         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
 136         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
 137         /*
 138          * Linux can handle differing I-cache policies. Userspace JITs will
 139          * make use of *minLine
 140          */
 141         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),   /* L1Ip */
 142         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),        /* RAZ */
 143         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),  /* IminLine */
 144         ARM64_FTR_END,
 145 };
 146
 147 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
 148         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),        /* InnerShr */
 149         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
 150         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),        /* AuxReg */
 151         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),        /* TCM */
 152         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* ShareLvl */
 153         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
 154         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
 155         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
 156         ARM64_FTR_END,
 157 };
 158
 159 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 160         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 161         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 162         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 163         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 164         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 165         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 166         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 167         ARM64_FTR_END,
 168 };
 169
 170 static struct arm64_ftr_bits ftr_mvfr2[] = {
 171         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 172         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* FPMisc */
 173         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* SIMDMisc */
 174         ARM64_FTR_END,
 175 };
 176
 177 static struct arm64_ftr_bits ftr_dczid[] = {
 178         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0),        /* RAZ */
 179         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1),         /* DZP */
 180         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* BS */
 181         ARM64_FTR_END,
 182 };
 183
 184
 185 static struct arm64_ftr_bits ftr_id_isar5[] = {
 186         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 187         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0),        /* RAZ */
 188         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 189         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 190         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 192         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 193         ARM64_FTR_END,
 194 };
 195
 196 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
 197         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 198         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* ac2 */
 199         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* RAZ */
 200         ARM64_FTR_END,
 201 };
 202
 203 static struct arm64_ftr_bits ftr_id_pfr0[] = {
 204         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0),       /* RAZ */
 205         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* State3 */
 206         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),         /* State2 */
 207         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* State1 */
 208         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* State0 */
 209         ARM64_FTR_END,
 210 };
 211
 212 /*
 213  * Common ftr bits for a 32bit register with all hidden, strict
 214  * attributes, with 4bit feature fields and a default safe value of
 215  * 0. Covers the following 32bit registers:
 216  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 217  */
 218 static struct arm64_ftr_bits ftr_generic_32bits[] = {
 219         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 220         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 221         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 222         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 223         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 224         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 225         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 226         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 227         ARM64_FTR_END,
 228 };
 229
 230 static struct arm64_ftr_bits ftr_generic[] = {
 231         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 232         ARM64_FTR_END,
 233 };
 234
 235 static struct arm64_ftr_bits ftr_generic32[] = {
 236         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
 237         ARM64_FTR_END,
 238 };
 239
 240 static struct arm64_ftr_bits ftr_aa64raz[] = {
 241         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 242         ARM64_FTR_END,
 243 };
 244
 245 #define ARM64_FTR_REG(id, table)                \
 246         {                                       \
 247                 .sys_id = id,                   \
 248                 .name = #id,                    \
 249                 .ftr_bits = &((table)[0]),      \
 250         }
 251
 252 static struct arm64_ftr_reg arm64_ftr_regs[] = {
 253
 254         /* Op1 = 0, CRn = 0, CRm = 1 */
 255         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 256         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 257         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
 258         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 259         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 260         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 261         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 262
 263         /* Op1 = 0, CRn = 0, CRm = 2 */
 264         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 265         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 266         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 267         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 268         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 269         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 270         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 271
 272         /* Op1 = 0, CRn = 0, CRm = 3 */
 273         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 274         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 275         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 276
 277         /* Op1 = 0, CRn = 0, CRm = 4 */
 278         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 279         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
 280
 281         /* Op1 = 0, CRn = 0, CRm = 5 */
 282         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 283         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
 284
 285         /* Op1 = 0, CRn = 0, CRm = 6 */
 286         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 287         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
 288
 289         /* Op1 = 0, CRn = 0, CRm = 7 */
 290         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 291         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 292         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 293
 294         /* Op1 = 3, CRn = 0, CRm = 0 */
 295         ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
 296         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 297
 298         /* Op1 = 3, CRn = 14, CRm = 0 */
 299         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
 300 };
 301
 302 static int search_cmp_ftr_reg(const void *id, const void *regp)
 303 {
 304         return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
 305 }
 306
 307 /*
 308  * get_arm64_ftr_reg - Lookup a feature register entry using its
 309  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 310  * ascending order of sys_id , we use binary search to find a matching
 311  * entry.
 312  *
 313  * returns - Upon success,  matching ftr_reg entry for id.
 314  *         - NULL on failure. It is upto the caller to decide
 315  *           the impact of a failure.
 316  */
 317 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 318 {
 319         return bsearch((const void *)(unsigned long)sys_id,
 320                         arm64_ftr_regs,
 321                         ARRAY_SIZE(arm64_ftr_regs),
 322                         sizeof(arm64_ftr_regs[0]),
 323                         search_cmp_ftr_reg);
 324 }
 325
 326 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
 327 {
 328         u64 mask = arm64_ftr_mask(ftrp);
 329
 330         reg &= ~mask;
 331         reg |= (ftr_val << ftrp->shift) & mask;
 332         return reg;
 333 }
 334
 335 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
 336 {
 337         s64 ret = 0;
 338
 339         switch (ftrp->type) {
 340         case FTR_EXACT:
 341                 ret = ftrp->safe_val;
 342                 break;
 343         case FTR_LOWER_SAFE:
 344                 ret = new < cur ? new : cur;
 345                 break;
 346         case FTR_HIGHER_SAFE:
 347                 ret = new > cur ? new : cur;
 348                 break;
 349         default:
 350                 BUG();
 351         }
 352
 353         return ret;
 354 }
 355
 356 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
 357 {
 358         return ((const struct arm64_ftr_reg *)a)->sys_id -
 359                  ((const struct arm64_ftr_reg *)b)->sys_id;
 360 }
 361
 362 static void __init swap_ftr_regs(void *a, void *b, int size)
 363 {
 364         struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
 365         *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
 366         *(struct arm64_ftr_reg *)b = tmp;
 367 }
 368
 369 static void __init sort_ftr_regs(void)
 370 {
 371         /* Keep the array sorted so that we can do the binary search */
 372         sort(arm64_ftr_regs,
 373                 ARRAY_SIZE(arm64_ftr_regs),
 374                 sizeof(arm64_ftr_regs[0]),
 375                 sort_cmp_ftr_regs,
 376                 swap_ftr_regs);
 377 }
 378
 379 /*
 380  * Initialise the CPU feature register from Boot CPU values.
 381  * Also initiliases the strict_mask for the register.
 382  */
 383 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 384 {
 385         u64 val = 0;
 386         u64 strict_mask = ~0x0ULL;
 387         struct arm64_ftr_bits *ftrp;
 388         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 389
 390         BUG_ON(!reg);
 391
 392         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 393                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 394
 395                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 396                 if (!ftrp->strict)
 397                         strict_mask &= ~arm64_ftr_mask(ftrp);
 398         }
 399         reg->sys_val = val;
 400         reg->strict_mask = strict_mask;
 401 }
 402
 403 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 404 {
 405         /* Before we start using the tables, make sure it is sorted */
 406         sort_ftr_regs();
 407
 408         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 409         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 410         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 411         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 412         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 413         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 414         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 415         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 416         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 417         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 418         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 419         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 420         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 421         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 422         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 423         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 424         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 425         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 426         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 427         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 428         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 429         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 430         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 431         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 432         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 433         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 434         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 435         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 436 }
 437
 438 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 439 {
 440         struct arm64_ftr_bits *ftrp;
 441
 442         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 443                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 444                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 445
 446                 if (ftr_cur == ftr_new)
 447                         continue;
 448                 /* Find a safe value */
 449                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 450                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 451         }
 452
 453 }
 454
 455 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 456 {
 457         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 458
 459         BUG_ON(!regp);
 460         update_cpu_ftr_reg(regp, val);
 461         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 462                 return 0;
 463         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 464                         regp->name, boot, cpu, val);
 465         return 1;
 466 }
 467
 468 /*
 469  * Update system wide CPU feature registers with the values from a
 470  * non-boot CPU. Also performs SANITY checks to make sure that there
 471  * aren't any insane variations from that of the boot CPU.
 472  */
 473 void update_cpu_features(int cpu,
 474                          struct cpuinfo_arm64 *info,
 475                          struct cpuinfo_arm64 *boot)
 476 {
 477         int taint = 0;
 478
 479         /*
 480          * The kernel can handle differing I-cache policies, but otherwise
 481          * caches should look identical. Userspace JITs will make use of
 482          * *minLine.
 483          */
 484         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 485                                       info->reg_ctr, boot->reg_ctr);
 486
 487         /*
 488          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 489          * could result in too much or too little memory being zeroed if a
 490          * process is preempted and migrated between CPUs.
 491          */
 492         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 493                                       info->reg_dczid, boot->reg_dczid);
 494
 495         /* If different, timekeeping will be broken (especially with KVM) */
 496         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 497                                       info->reg_cntfrq, boot->reg_cntfrq);
 498
 499         /*
 500          * The kernel uses self-hosted debug features and expects CPUs to
 501          * support identical debug features. We presently need CTX_CMPs, WRPs,
 502          * and BRPs to be identical.
 503          * ID_AA64DFR1 is currently RES0.
 504          */
 505         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 506                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 507         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 508                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 509         /*
 510          * Even in big.LITTLE, processors should be identical instruction-set
 511          * wise.
 512          */
 513         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 514                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 515         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 516                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 517
 518         /*
 519          * Differing PARange support is fine as long as all peripherals and
 520          * memory are mapped within the minimum PARange of all CPUs.
 521          * Linux should not care about secure memory.
 522          */
 523         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 524                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 525         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 526                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 527         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 528                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 529
 530         /*
 531          * EL3 is not our concern.
 532          * ID_AA64PFR1 is currently RES0.
 533          */
 534         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 535                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 536         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 537                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 538
 539         /*
 540          * If we have AArch32, we care about 32-bit features for compat. These
 541          * registers should be RES0 otherwise.
 542          */
 543         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 544                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 545         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 546                                         info->reg_id_isar0, boot->reg_id_isar0);
 547         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 548                                         info->reg_id_isar1, boot->reg_id_isar1);
 549         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 550                                         info->reg_id_isar2, boot->reg_id_isar2);
 551         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 552                                         info->reg_id_isar3, boot->reg_id_isar3);
 553         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 554                                         info->reg_id_isar4, boot->reg_id_isar4);
 555         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 556                                         info->reg_id_isar5, boot->reg_id_isar5);
 557
 558         /*
 559          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 560          * ACTLR formats could differ across CPUs and therefore would have to
 561          * be trapped for virtualization anyway.
 562          */
 563         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 564                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 565         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 566                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 567         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 568                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 569         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 570                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 571         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 572                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 573         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 574                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 575         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 576                                         info->reg_mvfr0, boot->reg_mvfr0);
 577         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 578                                         info->reg_mvfr1, boot->reg_mvfr1);
 579         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 580                                         info->reg_mvfr2, boot->reg_mvfr2);
 581
 582         /*
 583          * Mismatched CPU features are a recipe for disaster. Don't even
 584          * pretend to support them.
 585          */
 586         WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
 587                         "Unsupported CPU feature variation.\n");
 588 }
 589
 590 u64 read_system_reg(u32 id)
 591 {
 592         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 593
 594         /* We shouldn't get a request for an unsupported register */
 595         BUG_ON(!regp);
 596         return regp->sys_val;
 597 }
 598
 599 #include <linux/irqchip/arm-gic-v3.h>
 600
 601 static bool
 602 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 603 {
 604         int val = cpuid_feature_extract_field(reg, entry->field_pos);
 605
 606         return val >= entry->min_field_value;
 607 }
 608
 609 static bool
 610 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
 611 {
 612         u64 val;
 613
 614         val = read_system_reg(entry->sys_reg);
 615         return feature_matches(val, entry);
 616 }
 617
 618 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
 619 {
 620         bool has_sre;
 621
 622         if (!has_cpuid_feature(entry))
 623                 return false;
 624
 625         has_sre = gic_enable_sre();
 626         if (!has_sre)
 627                 pr_warn_once("%s present but disabled by higher exception level\n",
 628                              entry->desc);
 629
 630         return has_sre;
 631 }
 632
 633 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
 634 {
 635         u32 midr = read_cpuid_id();
 636         u32 rv_min, rv_max;
 637
 638         /* Cavium ThunderX pass 1.x and 2.x */
 639         rv_min = 0;
 640         rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
 641
 642         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
 643 }
 644
 645 static const struct arm64_cpu_capabilities arm64_features[] = {
 646         {
 647                 .desc = "GIC system register CPU interface",
 648                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 649                 .matches = has_useable_gicv3_cpuif,
 650                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 651                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 652                 .min_field_value = 1,
 653         },
 654 #ifdef CONFIG_ARM64_PAN
 655         {
 656                 .desc = "Privileged Access Never",
 657                 .capability = ARM64_HAS_PAN,
 658                 .matches = has_cpuid_feature,
 659                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 660                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 661                 .min_field_value = 1,
 662                 .enable = cpu_enable_pan,
 663         },
 664 #endif /* CONFIG_ARM64_PAN */
 665 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 666         {
 667                 .desc = "LSE atomic instructions",
 668                 .capability = ARM64_HAS_LSE_ATOMICS,
 669                 .matches = has_cpuid_feature,
 670                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 671                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 672                 .min_field_value = 2,
 673         },
 674 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 675         {
 676                 .desc = "Software prefetching using PRFM",
 677                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 678                 .matches = has_no_hw_prefetch,
 679         },
 680 #ifdef CONFIG_ARM64_UAO
 681         {
 682                 .desc = "User Access Override",
 683                 .capability = ARM64_HAS_UAO,
 684                 .matches = has_cpuid_feature,
 685                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
 686                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
 687                 .min_field_value = 1,
 688                 .enable = cpu_enable_uao,
 689         },
 690 #endif /* CONFIG_ARM64_UAO */
 691         {},
 692 };
 693
 694 #define HWCAP_CAP(reg, field, min_value, type, cap)             \
 695         {                                                       \
 696                 .desc = #cap,                                   \
 697                 .matches = has_cpuid_feature,                   \
 698                 .sys_reg = reg,                                 \
 699                 .field_pos = field,                             \
 700                 .min_field_value = min_value,                   \
 701                 .hwcap_type = type,                             \
 702                 .hwcap = cap,                                   \
 703         }
 704
 705 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
 706         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
 707         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
 708         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
 709         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
 710         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
 711         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
 712         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
 713         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
 714 #ifdef CONFIG_COMPAT
 715         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 716         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 717         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 718         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 719         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 720 #endif
 721         {},
 722 };
 723
 724 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
 725 {
 726         switch (cap->hwcap_type) {
 727         case CAP_HWCAP:
 728                 elf_hwcap |= cap->hwcap;
 729                 break;
 730 #ifdef CONFIG_COMPAT
 731         case CAP_COMPAT_HWCAP:
 732                 compat_elf_hwcap |= (u32)cap->hwcap;
 733                 break;
 734         case CAP_COMPAT_HWCAP2:
 735                 compat_elf_hwcap2 |= (u32)cap->hwcap;
 736                 break;
 737 #endif
 738         default:
 739                 WARN_ON(1);
 740                 break;
 741         }
 742 }
 743
 744 /* Check if we have a particular HWCAP enabled */
 745 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
 746 {
 747         bool rc;
 748
 749         switch (cap->hwcap_type) {
 750         case CAP_HWCAP:
 751                 rc = (elf_hwcap & cap->hwcap) != 0;
 752                 break;
 753 #ifdef CONFIG_COMPAT
 754         case CAP_COMPAT_HWCAP:
 755                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
 756                 break;
 757         case CAP_COMPAT_HWCAP2:
 758                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
 759                 break;
 760 #endif
 761         default:
 762                 WARN_ON(1);
 763                 rc = false;
 764         }
 765
 766         return rc;
 767 }
 768
 769 static void __init setup_cpu_hwcaps(void)
 770 {
 771         int i;
 772         const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
 773
 774         for (i = 0; hwcaps[i].matches; i++)
 775                 if (hwcaps[i].matches(&hwcaps[i]))
 776                         cap_set_hwcap(&hwcaps[i]);
 777 }
 778
 779 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 780                             const char *info)
 781 {
 782         int i;
 783
 784         for (i = 0; caps[i].matches; i++) {
 785                 if (!caps[i].matches(&caps[i]))
 786                         continue;
 787
 788                 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
 789                         pr_info("%s %s\n", info, caps[i].desc);
 790                 cpus_set_cap(caps[i].capability);
 791         }
 792 }
 793
 794 /*
 795  * Run through the enabled capabilities and enable() it on all active
 796  * CPUs
 797  */
 798 static void __init
 799 enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 800 {
 801         int i;
 802
 803         for (i = 0; caps[i].matches; i++)
 804                 if (caps[i].enable && cpus_have_cap(caps[i].capability))
 805                         on_each_cpu(caps[i].enable, NULL, true);
 806 }
 807
 808 #ifdef CONFIG_HOTPLUG_CPU
 809
 810 /*
 811  * Flag to indicate if we have computed the system wide
 812  * capabilities based on the boot time active CPUs. This
 813  * will be used to determine if a new booting CPU should
 814  * go through the verification process to make sure that it
 815  * supports the system capabilities, without using a hotplug
 816  * notifier.
 817  */
 818 static bool sys_caps_initialised;
 819
 820 static inline void set_sys_caps_initialised(void)
 821 {
 822         sys_caps_initialised = true;
 823 }
 824
 825 /*
 826  * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
 827  */
 828 static u64 __raw_read_system_reg(u32 sys_id)
 829 {
 830         switch (sys_id) {
 831         case SYS_ID_PFR0_EL1:           return read_cpuid(SYS_ID_PFR0_EL1);
 832         case SYS_ID_PFR1_EL1:           return read_cpuid(SYS_ID_PFR1_EL1);
 833         case SYS_ID_DFR0_EL1:           return read_cpuid(SYS_ID_DFR0_EL1);
 834         case SYS_ID_MMFR0_EL1:          return read_cpuid(SYS_ID_MMFR0_EL1);
 835         case SYS_ID_MMFR1_EL1:          return read_cpuid(SYS_ID_MMFR1_EL1);
 836         case SYS_ID_MMFR2_EL1:          return read_cpuid(SYS_ID_MMFR2_EL1);
 837         case SYS_ID_MMFR3_EL1:          return read_cpuid(SYS_ID_MMFR3_EL1);
 838         case SYS_ID_ISAR0_EL1:          return read_cpuid(SYS_ID_ISAR0_EL1);
 839         case SYS_ID_ISAR1_EL1:          return read_cpuid(SYS_ID_ISAR1_EL1);
 840         case SYS_ID_ISAR2_EL1:          return read_cpuid(SYS_ID_ISAR2_EL1);
 841         case SYS_ID_ISAR3_EL1:          return read_cpuid(SYS_ID_ISAR3_EL1);
 842         case SYS_ID_ISAR4_EL1:          return read_cpuid(SYS_ID_ISAR4_EL1);
 843         case SYS_ID_ISAR5_EL1:          return read_cpuid(SYS_ID_ISAR4_EL1);
 844         case SYS_MVFR0_EL1:             return read_cpuid(SYS_MVFR0_EL1);
 845         case SYS_MVFR1_EL1:             return read_cpuid(SYS_MVFR1_EL1);
 846         case SYS_MVFR2_EL1:             return read_cpuid(SYS_MVFR2_EL1);
 847
 848         case SYS_ID_AA64PFR0_EL1:       return read_cpuid(SYS_ID_AA64PFR0_EL1);
 849         case SYS_ID_AA64PFR1_EL1:       return read_cpuid(SYS_ID_AA64PFR0_EL1);
 850         case SYS_ID_AA64DFR0_EL1:       return read_cpuid(SYS_ID_AA64DFR0_EL1);
 851         case SYS_ID_AA64DFR1_EL1:       return read_cpuid(SYS_ID_AA64DFR0_EL1);
 852         case SYS_ID_AA64MMFR0_EL1:      return read_cpuid(SYS_ID_AA64MMFR0_EL1);
 853         case SYS_ID_AA64MMFR1_EL1:      return read_cpuid(SYS_ID_AA64MMFR1_EL1);
 854         case SYS_ID_AA64MMFR2_EL1:      return read_cpuid(SYS_ID_AA64MMFR2_EL1);
 855         case SYS_ID_AA64ISAR0_EL1:      return read_cpuid(SYS_ID_AA64ISAR0_EL1);
 856         case SYS_ID_AA64ISAR1_EL1:      return read_cpuid(SYS_ID_AA64ISAR1_EL1);
 857
 858         case SYS_CNTFRQ_EL0:            return read_cpuid(SYS_CNTFRQ_EL0);
 859         case SYS_CTR_EL0:               return read_cpuid(SYS_CTR_EL0);
 860         case SYS_DCZID_EL0:             return read_cpuid(SYS_DCZID_EL0);
 861         default:
 862                 BUG();
 863                 return 0;
 864         }
 865 }
 866
 867 /*
 868  * Park the CPU which doesn't have the capability as advertised
 869  * by the system.
 870  */
 871 static void fail_incapable_cpu(char *cap_type,
 872                                  const struct arm64_cpu_capabilities *cap)
 873 {
 874         int cpu = smp_processor_id();
 875
 876         pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
 877         /* Mark this CPU absent */
 878         set_cpu_present(cpu, 0);
 879
 880         /* Check if we can park ourselves */
 881         if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
 882                 cpu_ops[cpu]->cpu_die(cpu);
 883         asm(
 884         "1:     wfe\n"
 885         "       wfi\n"
 886         "       b       1b");
 887 }
 888
 889 /*
 890  * Run through the enabled system capabilities and enable() it on this CPU.
 891  * The capabilities were decided based on the available CPUs at the boot time.
 892  * Any new CPU should match the system wide status of the capability. If the
 893  * new CPU doesn't have a capability which the system now has enabled, we
 894  * cannot do anything to fix it up and could cause unexpected failures. So
 895  * we park the CPU.
 896  */
 897 void verify_local_cpu_capabilities(void)
 898 {
 899         int i;
 900         const struct arm64_cpu_capabilities *caps;
 901
 902         /*
 903          * If we haven't computed the system capabilities, there is nothing
 904          * to verify.
 905          */
 906         if (!sys_caps_initialised)
 907                 return;
 908
 909         caps = arm64_features;
 910         for (i = 0; caps[i].matches; i++) {
 911                 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
 912                         continue;
 913                 /*
 914                  * If the new CPU misses an advertised feature, we cannot proceed
 915                  * further, park the cpu.
 916                  */
 917                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 918                         fail_incapable_cpu("arm64_features", &caps[i]);
 919                 if (caps[i].enable)
 920                         caps[i].enable(NULL);
 921         }
 922
 923         for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
 924                 if (!cpus_have_hwcap(&caps[i]))
 925                         continue;
 926                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 927                         fail_incapable_cpu("arm64_hwcaps", &caps[i]);
 928         }
 929 }
 930
 931 #else   /* !CONFIG_HOTPLUG_CPU */
 932
 933 static inline void set_sys_caps_initialised(void)
 934 {
 935 }
 936
 937 #endif  /* CONFIG_HOTPLUG_CPU */
 938
 939 static void __init setup_feature_capabilities(void)
 940 {
 941         update_cpu_capabilities(arm64_features, "detected feature:");
 942         enable_cpu_capabilities(arm64_features);
 943 }
 944
 945 void __init setup_cpu_features(void)
 946 {
 947         u32 cwg;
 948         int cls;
 949
 950         /* Set the CPU feature capabilies */
 951         setup_feature_capabilities();
 952         setup_cpu_hwcaps();
 953
 954         /* Advertise that we have computed the system capabilities */
 955         set_sys_caps_initialised();
 956
 957         /*
 958          * Check for sane CTR_EL0.CWG value.
 959          */
 960         cwg = cache_type_cwg();
 961         cls = cache_line_size();
 962         if (!cwg)
 963                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
 964                         cls);
 965         if (L1_CACHE_BYTES < cls)
 966                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
 967                         L1_CACHE_BYTES, cls);
 968 }