2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/sort.h>
24 #include <linux/stop_machine.h>
25 #include <linux/types.h>
27 #include <asm/cpufeature.h>
28 #include <asm/cpu_ops.h>
29 #include <asm/processor.h>
30 #include <asm/sysreg.h>
33 unsigned long elf_hwcap __read_mostly;
34 EXPORT_SYMBOL_GPL(elf_hwcap);
37 #define COMPAT_ELF_HWCAP_DEFAULT \
38 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
39 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
40 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
41 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
42 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
44 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
45 unsigned int compat_elf_hwcap2 __read_mostly;
48 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
50 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
57 .safe_val = SAFE_VAL, \
60 /* Define a feature with signed values */
61 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
62 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
64 /* Define a feature with unsigned value */
65 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
66 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
68 #define ARM64_FTR_END \
73 /* meta feature for alternatives */
74 static bool __maybe_unused
75 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
77 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
78 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
79 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
85 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
86 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
90 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
91 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
92 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
93 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
94 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
95 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
96 /* Linux doesn't care about the EL3 */
97 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
98 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
99 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
100 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
104 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
105 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
106 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
107 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
108 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
109 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
110 /* Linux shouldn't care about secure memory */
111 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
112 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
113 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
115 * Differing PARange is fine as long as all peripherals and memory are mapped
116 * within the minimum PARange of all CPUs
118 U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
122 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
123 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
124 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
133 static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
134 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
138 static struct arm64_ftr_bits ftr_ctr[] = {
139 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
140 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
141 U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
142 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
143 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
145 * Linux can handle differing I-cache policies. Userspace JITs will
146 * make use of *minLine
148 U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
149 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
150 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
154 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
155 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), /* InnerShr */
156 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
157 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
158 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
159 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
160 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
161 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
162 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
166 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
167 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
168 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
169 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
170 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
171 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
172 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
173 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
177 static struct arm64_ftr_bits ftr_mvfr2[] = {
178 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
179 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
180 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
184 static struct arm64_ftr_bits ftr_dczid[] = {
185 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
186 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
187 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
192 static struct arm64_ftr_bits ftr_id_isar5[] = {
193 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
195 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
203 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
204 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
205 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
206 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
210 static struct arm64_ftr_bits ftr_id_pfr0[] = {
211 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
212 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
213 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
214 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
215 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
220 * Common ftr bits for a 32bit register with all hidden, strict
221 * attributes, with 4bit feature fields and a default safe value of
222 * 0. Covers the following 32bit registers:
223 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
225 static struct arm64_ftr_bits ftr_generic_32bits[] = {
226 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
227 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
228 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
229 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
230 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
231 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
232 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
233 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
237 static struct arm64_ftr_bits ftr_generic[] = {
238 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
242 static struct arm64_ftr_bits ftr_generic32[] = {
243 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
247 static struct arm64_ftr_bits ftr_aa64raz[] = {
248 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
252 #define ARM64_FTR_REG(id, table) \
256 .ftr_bits = &((table)[0]), \
259 static struct arm64_ftr_reg arm64_ftr_regs[] = {
261 /* Op1 = 0, CRn = 0, CRm = 1 */
262 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
263 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
264 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
265 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
266 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
267 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
268 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
270 /* Op1 = 0, CRn = 0, CRm = 2 */
271 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
272 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
273 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
274 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
275 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
276 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
277 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
279 /* Op1 = 0, CRn = 0, CRm = 3 */
280 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
281 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
282 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
284 /* Op1 = 0, CRn = 0, CRm = 4 */
285 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
286 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
288 /* Op1 = 0, CRn = 0, CRm = 5 */
289 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
290 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
292 /* Op1 = 0, CRn = 0, CRm = 6 */
293 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
294 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
296 /* Op1 = 0, CRn = 0, CRm = 7 */
297 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
298 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
299 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
301 /* Op1 = 3, CRn = 0, CRm = 0 */
302 ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
303 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
305 /* Op1 = 3, CRn = 14, CRm = 0 */
306 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
309 static int search_cmp_ftr_reg(const void *id, const void *regp)
311 return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
315 * get_arm64_ftr_reg - Lookup a feature register entry using its
316 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
317 * ascending order of sys_id , we use binary search to find a matching
320 * returns - Upon success, matching ftr_reg entry for id.
321 * - NULL on failure. It is upto the caller to decide
322 * the impact of a failure.
324 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
326 return bsearch((const void *)(unsigned long)sys_id,
328 ARRAY_SIZE(arm64_ftr_regs),
329 sizeof(arm64_ftr_regs[0]),
333 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
335 u64 mask = arm64_ftr_mask(ftrp);
338 reg |= (ftr_val << ftrp->shift) & mask;
342 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
346 switch (ftrp->type) {
348 ret = ftrp->safe_val;
351 ret = new < cur ? new : cur;
353 case FTR_HIGHER_SAFE:
354 ret = new > cur ? new : cur;
363 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
365 return ((const struct arm64_ftr_reg *)a)->sys_id -
366 ((const struct arm64_ftr_reg *)b)->sys_id;
369 static void __init swap_ftr_regs(void *a, void *b, int size)
371 struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
372 *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
373 *(struct arm64_ftr_reg *)b = tmp;
376 static void __init sort_ftr_regs(void)
378 /* Keep the array sorted so that we can do the binary search */
380 ARRAY_SIZE(arm64_ftr_regs),
381 sizeof(arm64_ftr_regs[0]),
387 * Initialise the CPU feature register from Boot CPU values.
388 * Also initiliases the strict_mask for the register.
390 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
393 u64 strict_mask = ~0x0ULL;
394 struct arm64_ftr_bits *ftrp;
395 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
399 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
400 s64 ftr_new = arm64_ftr_value(ftrp, new);
402 val = arm64_ftr_set_value(ftrp, val, ftr_new);
404 strict_mask &= ~arm64_ftr_mask(ftrp);
407 reg->strict_mask = strict_mask;
410 void __init init_cpu_features(struct cpuinfo_arm64 *info)
412 /* Before we start using the tables, make sure it is sorted */
415 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
416 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
417 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
418 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
419 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
420 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
421 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
422 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
423 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
424 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
425 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
426 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
427 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
428 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
429 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
430 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
431 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
432 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
433 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
434 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
435 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
436 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
437 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
438 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
439 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
440 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
441 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
442 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
445 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
447 struct arm64_ftr_bits *ftrp;
449 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
450 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
451 s64 ftr_new = arm64_ftr_value(ftrp, new);
453 if (ftr_cur == ftr_new)
455 /* Find a safe value */
456 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
457 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
462 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
464 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
467 update_cpu_ftr_reg(regp, val);
468 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
470 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
471 regp->name, boot, cpu, val);
476 * Update system wide CPU feature registers with the values from a
477 * non-boot CPU. Also performs SANITY checks to make sure that there
478 * aren't any insane variations from that of the boot CPU.
480 void update_cpu_features(int cpu,
481 struct cpuinfo_arm64 *info,
482 struct cpuinfo_arm64 *boot)
487 * The kernel can handle differing I-cache policies, but otherwise
488 * caches should look identical. Userspace JITs will make use of
491 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
492 info->reg_ctr, boot->reg_ctr);
495 * Userspace may perform DC ZVA instructions. Mismatched block sizes
496 * could result in too much or too little memory being zeroed if a
497 * process is preempted and migrated between CPUs.
499 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
500 info->reg_dczid, boot->reg_dczid);
502 /* If different, timekeeping will be broken (especially with KVM) */
503 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
504 info->reg_cntfrq, boot->reg_cntfrq);
507 * The kernel uses self-hosted debug features and expects CPUs to
508 * support identical debug features. We presently need CTX_CMPs, WRPs,
509 * and BRPs to be identical.
510 * ID_AA64DFR1 is currently RES0.
512 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
513 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
514 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
515 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
517 * Even in big.LITTLE, processors should be identical instruction-set
520 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
521 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
522 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
523 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
526 * Differing PARange support is fine as long as all peripherals and
527 * memory are mapped within the minimum PARange of all CPUs.
528 * Linux should not care about secure memory.
530 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
531 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
532 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
533 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
534 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
535 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
538 * EL3 is not our concern.
539 * ID_AA64PFR1 is currently RES0.
541 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
542 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
543 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
544 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
547 * If we have AArch32, we care about 32-bit features for compat. These
548 * registers should be RES0 otherwise.
550 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
551 info->reg_id_dfr0, boot->reg_id_dfr0);
552 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
553 info->reg_id_isar0, boot->reg_id_isar0);
554 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
555 info->reg_id_isar1, boot->reg_id_isar1);
556 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
557 info->reg_id_isar2, boot->reg_id_isar2);
558 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
559 info->reg_id_isar3, boot->reg_id_isar3);
560 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
561 info->reg_id_isar4, boot->reg_id_isar4);
562 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
563 info->reg_id_isar5, boot->reg_id_isar5);
566 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
567 * ACTLR formats could differ across CPUs and therefore would have to
568 * be trapped for virtualization anyway.
570 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
571 info->reg_id_mmfr0, boot->reg_id_mmfr0);
572 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
573 info->reg_id_mmfr1, boot->reg_id_mmfr1);
574 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
575 info->reg_id_mmfr2, boot->reg_id_mmfr2);
576 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
577 info->reg_id_mmfr3, boot->reg_id_mmfr3);
578 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
579 info->reg_id_pfr0, boot->reg_id_pfr0);
580 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
581 info->reg_id_pfr1, boot->reg_id_pfr1);
582 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
583 info->reg_mvfr0, boot->reg_mvfr0);
584 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
585 info->reg_mvfr1, boot->reg_mvfr1);
586 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
587 info->reg_mvfr2, boot->reg_mvfr2);
590 * Mismatched CPU features are a recipe for disaster. Don't even
591 * pretend to support them.
593 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
594 "Unsupported CPU feature variation.\n");
597 u64 read_system_reg(u32 id)
599 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
601 /* We shouldn't get a request for an unsupported register */
603 return regp->sys_val;
606 #include <linux/irqchip/arm-gic-v3.h>
609 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
611 int val = cpuid_feature_extract_field(reg, entry->field_pos);
613 return val >= entry->min_field_value;
617 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
621 val = read_system_reg(entry->sys_reg);
622 return feature_matches(val, entry);
625 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
629 if (!has_cpuid_feature(entry))
632 has_sre = gic_enable_sre();
634 pr_warn_once("%s present but disabled by higher exception level\n",
640 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
642 u32 midr = read_cpuid_id();
645 /* Cavium ThunderX pass 1.x and 2.x */
647 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
649 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
652 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
654 return is_kernel_in_hyp_mode();
657 static const struct arm64_cpu_capabilities arm64_features[] = {
659 .desc = "GIC system register CPU interface",
660 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
661 .matches = has_useable_gicv3_cpuif,
662 .sys_reg = SYS_ID_AA64PFR0_EL1,
663 .field_pos = ID_AA64PFR0_GIC_SHIFT,
664 .min_field_value = 1,
666 #ifdef CONFIG_ARM64_PAN
668 .desc = "Privileged Access Never",
669 .capability = ARM64_HAS_PAN,
670 .matches = has_cpuid_feature,
671 .sys_reg = SYS_ID_AA64MMFR1_EL1,
672 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
673 .min_field_value = 1,
674 .enable = cpu_enable_pan,
676 #endif /* CONFIG_ARM64_PAN */
677 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
679 .desc = "LSE atomic instructions",
680 .capability = ARM64_HAS_LSE_ATOMICS,
681 .matches = has_cpuid_feature,
682 .sys_reg = SYS_ID_AA64ISAR0_EL1,
683 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
684 .min_field_value = 2,
686 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
688 .desc = "Software prefetching using PRFM",
689 .capability = ARM64_HAS_NO_HW_PREFETCH,
690 .matches = has_no_hw_prefetch,
692 #ifdef CONFIG_ARM64_UAO
694 .desc = "User Access Override",
695 .capability = ARM64_HAS_UAO,
696 .matches = has_cpuid_feature,
697 .sys_reg = SYS_ID_AA64MMFR2_EL1,
698 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
699 .min_field_value = 1,
700 .enable = cpu_enable_uao,
702 #endif /* CONFIG_ARM64_UAO */
703 #ifdef CONFIG_ARM64_PAN
705 .capability = ARM64_ALT_PAN_NOT_UAO,
706 .matches = cpufeature_pan_not_uao,
708 #endif /* CONFIG_ARM64_PAN */
710 .desc = "Virtualization Host Extensions",
711 .capability = ARM64_HAS_VIRT_HOST_EXTN,
712 .matches = runs_at_el2,
717 #define HWCAP_CAP(reg, field, min_value, type, cap) \
720 .matches = has_cpuid_feature, \
722 .field_pos = field, \
723 .min_field_value = min_value, \
724 .hwcap_type = type, \
728 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
729 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
730 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
731 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
732 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
733 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
734 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
735 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
736 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
738 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
739 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
740 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
741 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
742 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
747 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
749 switch (cap->hwcap_type) {
751 elf_hwcap |= cap->hwcap;
754 case CAP_COMPAT_HWCAP:
755 compat_elf_hwcap |= (u32)cap->hwcap;
757 case CAP_COMPAT_HWCAP2:
758 compat_elf_hwcap2 |= (u32)cap->hwcap;
767 /* Check if we have a particular HWCAP enabled */
768 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
772 switch (cap->hwcap_type) {
774 rc = (elf_hwcap & cap->hwcap) != 0;
777 case CAP_COMPAT_HWCAP:
778 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
780 case CAP_COMPAT_HWCAP2:
781 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
792 static void __init setup_cpu_hwcaps(void)
795 const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
797 for (i = 0; hwcaps[i].matches; i++)
798 if (hwcaps[i].matches(&hwcaps[i]))
799 cap_set_hwcap(&hwcaps[i]);
802 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
807 for (i = 0; caps[i].matches; i++) {
808 if (!caps[i].matches(&caps[i]))
811 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
812 pr_info("%s %s\n", info, caps[i].desc);
813 cpus_set_cap(caps[i].capability);
818 * Run through the enabled capabilities and enable() it on all active
822 enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
826 for (i = 0; caps[i].matches; i++)
827 if (caps[i].enable && cpus_have_cap(caps[i].capability))
829 * Use stop_machine() as it schedules the work allowing
830 * us to modify PSTATE, instead of on_each_cpu() which
831 * uses an IPI, giving us a PSTATE that disappears when
834 stop_machine(caps[i].enable, NULL, cpu_online_mask);
837 #ifdef CONFIG_HOTPLUG_CPU
840 * Flag to indicate if we have computed the system wide
841 * capabilities based on the boot time active CPUs. This
842 * will be used to determine if a new booting CPU should
843 * go through the verification process to make sure that it
844 * supports the system capabilities, without using a hotplug
847 static bool sys_caps_initialised;
849 static inline void set_sys_caps_initialised(void)
851 sys_caps_initialised = true;
855 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
857 static u64 __raw_read_system_reg(u32 sys_id)
860 case SYS_ID_PFR0_EL1: return read_cpuid(SYS_ID_PFR0_EL1);
861 case SYS_ID_PFR1_EL1: return read_cpuid(SYS_ID_PFR1_EL1);
862 case SYS_ID_DFR0_EL1: return read_cpuid(SYS_ID_DFR0_EL1);
863 case SYS_ID_MMFR0_EL1: return read_cpuid(SYS_ID_MMFR0_EL1);
864 case SYS_ID_MMFR1_EL1: return read_cpuid(SYS_ID_MMFR1_EL1);
865 case SYS_ID_MMFR2_EL1: return read_cpuid(SYS_ID_MMFR2_EL1);
866 case SYS_ID_MMFR3_EL1: return read_cpuid(SYS_ID_MMFR3_EL1);
867 case SYS_ID_ISAR0_EL1: return read_cpuid(SYS_ID_ISAR0_EL1);
868 case SYS_ID_ISAR1_EL1: return read_cpuid(SYS_ID_ISAR1_EL1);
869 case SYS_ID_ISAR2_EL1: return read_cpuid(SYS_ID_ISAR2_EL1);
870 case SYS_ID_ISAR3_EL1: return read_cpuid(SYS_ID_ISAR3_EL1);
871 case SYS_ID_ISAR4_EL1: return read_cpuid(SYS_ID_ISAR4_EL1);
872 case SYS_ID_ISAR5_EL1: return read_cpuid(SYS_ID_ISAR4_EL1);
873 case SYS_MVFR0_EL1: return read_cpuid(SYS_MVFR0_EL1);
874 case SYS_MVFR1_EL1: return read_cpuid(SYS_MVFR1_EL1);
875 case SYS_MVFR2_EL1: return read_cpuid(SYS_MVFR2_EL1);
877 case SYS_ID_AA64PFR0_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1);
878 case SYS_ID_AA64PFR1_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1);
879 case SYS_ID_AA64DFR0_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1);
880 case SYS_ID_AA64DFR1_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1);
881 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(SYS_ID_AA64MMFR0_EL1);
882 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(SYS_ID_AA64MMFR1_EL1);
883 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(SYS_ID_AA64MMFR2_EL1);
884 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(SYS_ID_AA64ISAR0_EL1);
885 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(SYS_ID_AA64ISAR1_EL1);
887 case SYS_CNTFRQ_EL0: return read_cpuid(SYS_CNTFRQ_EL0);
888 case SYS_CTR_EL0: return read_cpuid(SYS_CTR_EL0);
889 case SYS_DCZID_EL0: return read_cpuid(SYS_DCZID_EL0);
897 * Park the CPU which doesn't have the capability as advertised
900 static void fail_incapable_cpu(char *cap_type,
901 const struct arm64_cpu_capabilities *cap)
903 int cpu = smp_processor_id();
905 pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
906 /* Mark this CPU absent */
907 set_cpu_present(cpu, 0);
909 /* Check if we can park ourselves */
910 if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
911 cpu_ops[cpu]->cpu_die(cpu);
919 * Run through the enabled system capabilities and enable() it on this CPU.
920 * The capabilities were decided based on the available CPUs at the boot time.
921 * Any new CPU should match the system wide status of the capability. If the
922 * new CPU doesn't have a capability which the system now has enabled, we
923 * cannot do anything to fix it up and could cause unexpected failures. So
926 void verify_local_cpu_capabilities(void)
929 const struct arm64_cpu_capabilities *caps;
932 * If we haven't computed the system capabilities, there is nothing
935 if (!sys_caps_initialised)
938 caps = arm64_features;
939 for (i = 0; caps[i].matches; i++) {
940 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
943 * If the new CPU misses an advertised feature, we cannot proceed
944 * further, park the cpu.
946 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
947 fail_incapable_cpu("arm64_features", &caps[i]);
949 caps[i].enable(NULL);
952 for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
953 if (!cpus_have_hwcap(&caps[i]))
955 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
956 fail_incapable_cpu("arm64_hwcaps", &caps[i]);
960 #else /* !CONFIG_HOTPLUG_CPU */
962 static inline void set_sys_caps_initialised(void)
966 #endif /* CONFIG_HOTPLUG_CPU */
968 static void __init setup_feature_capabilities(void)
970 update_cpu_capabilities(arm64_features, "detected feature:");
971 enable_cpu_capabilities(arm64_features);
974 void __init setup_cpu_features(void)
979 /* Set the CPU feature capabilies */
980 setup_feature_capabilities();
983 /* Advertise that we have computed the system capabilities */
984 set_sys_caps_initialised();
987 * Check for sane CTR_EL0.CWG value.
989 cwg = cache_type_cwg();
990 cls = cache_line_size();
992 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
994 if (L1_CACHE_BYTES < cls)
995 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
996 L1_CACHE_BYTES, cls);
999 static bool __maybe_unused
1000 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
1002 return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));