2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "alternatives: " fmt
21 #include <linux/types.h>
23 #include <asm/cpufeature.h>
24 #include <asm/processor.h>
26 #include <linux/irqchip/arm-gic-v3.h>
29 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
31 int val = cpuid_feature_extract_field(reg, entry->field_pos);
33 return val >= entry->min_field_value;
36 #define __ID_FEAT_CHK(reg) \
37 static bool __maybe_unused \
38 has_##reg##_feature(const struct arm64_cpu_capabilities *entry) \
42 val = read_cpuid(reg##_el1); \
43 return feature_matches(val, entry); \
46 __ID_FEAT_CHK(id_aa64pfr0);
47 __ID_FEAT_CHK(id_aa64mmfr1);
48 __ID_FEAT_CHK(id_aa64isar0);
50 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
54 if (!has_id_aa64pfr0_feature(entry))
57 has_sre = gic_enable_sre();
59 pr_warn_once("%s present but disabled by higher exception level\n",
65 static const struct arm64_cpu_capabilities arm64_features[] = {
67 .desc = "GIC system register CPU interface",
68 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
69 .matches = has_useable_gicv3_cpuif,
73 #ifdef CONFIG_ARM64_PAN
75 .desc = "Privileged Access Never",
76 .capability = ARM64_HAS_PAN,
77 .matches = has_id_aa64mmfr1_feature,
80 .enable = cpu_enable_pan,
82 #endif /* CONFIG_ARM64_PAN */
83 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
85 .desc = "LSE atomic instructions",
86 .capability = ARM64_HAS_LSE_ATOMICS,
87 .matches = has_id_aa64isar0_feature,
91 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
95 void check_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
100 for (i = 0; caps[i].desc; i++) {
101 if (!caps[i].matches(&caps[i]))
104 if (!cpus_have_cap(caps[i].capability))
105 pr_info("%s %s\n", info, caps[i].desc);
106 cpus_set_cap(caps[i].capability);
109 /* second pass allows enable() to consider interacting capabilities */
110 for (i = 0; caps[i].desc; i++) {
111 if (cpus_have_cap(caps[i].capability) && caps[i].enable)
116 void check_local_cpu_features(void)
118 check_cpu_capabilities(arm64_features, "detected feature:");