2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/sort.h>
23 #include <linux/types.h>
25 #include <asm/cpufeature.h>
26 #include <asm/cpu_ops.h>
27 #include <asm/processor.h>
28 #include <asm/sysreg.h>
30 unsigned long elf_hwcap __read_mostly;
31 EXPORT_SYMBOL_GPL(elf_hwcap);
34 #define COMPAT_ELF_HWCAP_DEFAULT \
35 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
36 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
37 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
38 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
39 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
41 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
42 unsigned int compat_elf_hwcap2 __read_mostly;
45 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
46 EXPORT_SYMBOL(cpu_hwcaps);
48 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
55 .safe_val = SAFE_VAL, \
58 /* Define a feature with signed values */
59 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
60 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
62 /* Define a feature with unsigned value */
63 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
64 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
66 #define ARM64_FTR_END \
71 /* meta feature for alternatives */
72 static bool __maybe_unused
73 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
75 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
76 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
77 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
78 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
79 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
88 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
89 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
90 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
91 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
92 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
93 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
94 /* Linux doesn't care about the EL3 */
95 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
96 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
97 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
98 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
102 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
103 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
104 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
105 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
106 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
107 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
108 /* Linux shouldn't care about secure memory */
109 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
110 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
111 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
113 * Differing PARange is fine as long as all peripherals and memory are mapped
114 * within the minimum PARange of all CPUs
116 U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
120 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
121 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
122 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
123 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
124 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
131 static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
132 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
136 static struct arm64_ftr_bits ftr_ctr[] = {
137 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
138 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
139 U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
140 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
141 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
143 * Linux can handle differing I-cache policies. Userspace JITs will
144 * make use of *minLine
146 U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
147 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
148 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
152 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
153 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), /* InnerShr */
154 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
155 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
156 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
157 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
158 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
159 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
160 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
164 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
165 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
166 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
167 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
168 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
169 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
170 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
171 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
175 static struct arm64_ftr_bits ftr_mvfr2[] = {
176 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
177 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
178 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
182 static struct arm64_ftr_bits ftr_dczid[] = {
183 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
184 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
185 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
190 static struct arm64_ftr_bits ftr_id_isar5[] = {
191 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
193 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
201 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
202 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
203 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
204 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
208 static struct arm64_ftr_bits ftr_id_pfr0[] = {
209 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
210 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
211 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
212 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
213 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
218 * Common ftr bits for a 32bit register with all hidden, strict
219 * attributes, with 4bit feature fields and a default safe value of
220 * 0. Covers the following 32bit registers:
221 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
223 static struct arm64_ftr_bits ftr_generic_32bits[] = {
224 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
225 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
226 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
227 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
228 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
229 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
230 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
231 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
235 static struct arm64_ftr_bits ftr_generic[] = {
236 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
240 static struct arm64_ftr_bits ftr_generic32[] = {
241 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
245 static struct arm64_ftr_bits ftr_aa64raz[] = {
246 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
250 #define ARM64_FTR_REG(id, table) \
254 .ftr_bits = &((table)[0]), \
257 static struct arm64_ftr_reg arm64_ftr_regs[] = {
259 /* Op1 = 0, CRn = 0, CRm = 1 */
260 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
261 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
262 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
263 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
264 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
265 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
266 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
268 /* Op1 = 0, CRn = 0, CRm = 2 */
269 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
270 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
271 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
272 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
273 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
274 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
275 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
277 /* Op1 = 0, CRn = 0, CRm = 3 */
278 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
279 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
280 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
282 /* Op1 = 0, CRn = 0, CRm = 4 */
283 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
284 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
286 /* Op1 = 0, CRn = 0, CRm = 5 */
287 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
288 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
290 /* Op1 = 0, CRn = 0, CRm = 6 */
291 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
292 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
294 /* Op1 = 0, CRn = 0, CRm = 7 */
295 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
296 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
297 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
299 /* Op1 = 3, CRn = 0, CRm = 0 */
300 ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
301 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
303 /* Op1 = 3, CRn = 14, CRm = 0 */
304 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
307 static int search_cmp_ftr_reg(const void *id, const void *regp)
309 return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
313 * get_arm64_ftr_reg - Lookup a feature register entry using its
314 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
315 * ascending order of sys_id , we use binary search to find a matching
318 * returns - Upon success, matching ftr_reg entry for id.
319 * - NULL on failure. It is upto the caller to decide
320 * the impact of a failure.
322 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
324 return bsearch((const void *)(unsigned long)sys_id,
326 ARRAY_SIZE(arm64_ftr_regs),
327 sizeof(arm64_ftr_regs[0]),
331 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
333 u64 mask = arm64_ftr_mask(ftrp);
336 reg |= (ftr_val << ftrp->shift) & mask;
340 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
344 switch (ftrp->type) {
346 ret = ftrp->safe_val;
349 ret = new < cur ? new : cur;
351 case FTR_HIGHER_SAFE:
352 ret = new > cur ? new : cur;
361 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
363 return ((const struct arm64_ftr_reg *)a)->sys_id -
364 ((const struct arm64_ftr_reg *)b)->sys_id;
367 static void __init swap_ftr_regs(void *a, void *b, int size)
369 struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
370 *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
371 *(struct arm64_ftr_reg *)b = tmp;
374 static void __init sort_ftr_regs(void)
376 /* Keep the array sorted so that we can do the binary search */
378 ARRAY_SIZE(arm64_ftr_regs),
379 sizeof(arm64_ftr_regs[0]),
385 * Initialise the CPU feature register from Boot CPU values.
386 * Also initiliases the strict_mask for the register.
388 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
391 u64 strict_mask = ~0x0ULL;
392 struct arm64_ftr_bits *ftrp;
393 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
397 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
398 s64 ftr_new = arm64_ftr_value(ftrp, new);
400 val = arm64_ftr_set_value(ftrp, val, ftr_new);
402 strict_mask &= ~arm64_ftr_mask(ftrp);
405 reg->strict_mask = strict_mask;
408 void __init init_cpu_features(struct cpuinfo_arm64 *info)
410 /* Before we start using the tables, make sure it is sorted */
413 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
414 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
415 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
416 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
417 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
418 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
419 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
420 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
421 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
422 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
423 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
424 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
425 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
426 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
427 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
428 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
429 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
430 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
431 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
432 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
433 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
434 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
435 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
436 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
437 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
438 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
439 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
440 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
443 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
445 struct arm64_ftr_bits *ftrp;
447 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
448 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
449 s64 ftr_new = arm64_ftr_value(ftrp, new);
451 if (ftr_cur == ftr_new)
453 /* Find a safe value */
454 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
455 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
460 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
462 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
465 update_cpu_ftr_reg(regp, val);
466 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
468 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
469 regp->name, boot, cpu, val);
474 * Update system wide CPU feature registers with the values from a
475 * non-boot CPU. Also performs SANITY checks to make sure that there
476 * aren't any insane variations from that of the boot CPU.
478 void update_cpu_features(int cpu,
479 struct cpuinfo_arm64 *info,
480 struct cpuinfo_arm64 *boot)
485 * The kernel can handle differing I-cache policies, but otherwise
486 * caches should look identical. Userspace JITs will make use of
489 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
490 info->reg_ctr, boot->reg_ctr);
493 * Userspace may perform DC ZVA instructions. Mismatched block sizes
494 * could result in too much or too little memory being zeroed if a
495 * process is preempted and migrated between CPUs.
497 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
498 info->reg_dczid, boot->reg_dczid);
500 /* If different, timekeeping will be broken (especially with KVM) */
501 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
502 info->reg_cntfrq, boot->reg_cntfrq);
505 * The kernel uses self-hosted debug features and expects CPUs to
506 * support identical debug features. We presently need CTX_CMPs, WRPs,
507 * and BRPs to be identical.
508 * ID_AA64DFR1 is currently RES0.
510 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
511 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
512 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
513 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
515 * Even in big.LITTLE, processors should be identical instruction-set
518 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
519 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
520 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
521 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
524 * Differing PARange support is fine as long as all peripherals and
525 * memory are mapped within the minimum PARange of all CPUs.
526 * Linux should not care about secure memory.
528 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
529 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
530 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
531 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
532 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
533 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
536 * EL3 is not our concern.
537 * ID_AA64PFR1 is currently RES0.
539 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
540 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
541 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
542 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
545 * If we have AArch32, we care about 32-bit features for compat. These
546 * registers should be RES0 otherwise.
548 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
549 info->reg_id_dfr0, boot->reg_id_dfr0);
550 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
551 info->reg_id_isar0, boot->reg_id_isar0);
552 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
553 info->reg_id_isar1, boot->reg_id_isar1);
554 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
555 info->reg_id_isar2, boot->reg_id_isar2);
556 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
557 info->reg_id_isar3, boot->reg_id_isar3);
558 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
559 info->reg_id_isar4, boot->reg_id_isar4);
560 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
561 info->reg_id_isar5, boot->reg_id_isar5);
564 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
565 * ACTLR formats could differ across CPUs and therefore would have to
566 * be trapped for virtualization anyway.
568 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
569 info->reg_id_mmfr0, boot->reg_id_mmfr0);
570 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
571 info->reg_id_mmfr1, boot->reg_id_mmfr1);
572 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
573 info->reg_id_mmfr2, boot->reg_id_mmfr2);
574 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
575 info->reg_id_mmfr3, boot->reg_id_mmfr3);
576 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
577 info->reg_id_pfr0, boot->reg_id_pfr0);
578 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
579 info->reg_id_pfr1, boot->reg_id_pfr1);
580 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
581 info->reg_mvfr0, boot->reg_mvfr0);
582 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
583 info->reg_mvfr1, boot->reg_mvfr1);
584 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
585 info->reg_mvfr2, boot->reg_mvfr2);
588 * Mismatched CPU features are a recipe for disaster. Don't even
589 * pretend to support them.
591 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
592 "Unsupported CPU feature variation.\n");
595 u64 read_system_reg(u32 id)
597 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
599 /* We shouldn't get a request for an unsupported register */
601 return regp->sys_val;
604 #include <linux/irqchip/arm-gic-v3.h>
607 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
609 int val = cpuid_feature_extract_field(reg, entry->field_pos);
611 return val >= entry->min_field_value;
615 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
619 val = read_system_reg(entry->sys_reg);
620 return feature_matches(val, entry);
623 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
627 if (!has_cpuid_feature(entry))
630 has_sre = gic_enable_sre();
632 pr_warn_once("%s present but disabled by higher exception level\n",
638 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
640 u32 midr = read_cpuid_id();
643 /* Cavium ThunderX pass 1.x and 2.x */
645 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
647 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
650 static const struct arm64_cpu_capabilities arm64_features[] = {
652 .desc = "GIC system register CPU interface",
653 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
654 .matches = has_useable_gicv3_cpuif,
655 .sys_reg = SYS_ID_AA64PFR0_EL1,
656 .field_pos = ID_AA64PFR0_GIC_SHIFT,
657 .min_field_value = 1,
659 #ifdef CONFIG_ARM64_PAN
661 .desc = "Privileged Access Never",
662 .capability = ARM64_HAS_PAN,
663 .matches = has_cpuid_feature,
664 .sys_reg = SYS_ID_AA64MMFR1_EL1,
665 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
666 .min_field_value = 1,
667 .enable = cpu_enable_pan,
669 #endif /* CONFIG_ARM64_PAN */
670 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
672 .desc = "LSE atomic instructions",
673 .capability = ARM64_HAS_LSE_ATOMICS,
674 .matches = has_cpuid_feature,
675 .sys_reg = SYS_ID_AA64ISAR0_EL1,
676 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
677 .min_field_value = 2,
679 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
681 .desc = "Software prefetching using PRFM",
682 .capability = ARM64_HAS_NO_HW_PREFETCH,
683 .matches = has_no_hw_prefetch,
685 #ifdef CONFIG_ARM64_UAO
687 .desc = "User Access Override",
688 .capability = ARM64_HAS_UAO,
689 .matches = has_cpuid_feature,
690 .sys_reg = SYS_ID_AA64MMFR2_EL1,
691 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
692 .min_field_value = 1,
693 .enable = cpu_enable_uao,
695 #endif /* CONFIG_ARM64_UAO */
696 #ifdef CONFIG_ARM64_PAN
698 .capability = ARM64_ALT_PAN_NOT_UAO,
699 .matches = cpufeature_pan_not_uao,
701 #endif /* CONFIG_ARM64_PAN */
705 #define HWCAP_CAP(reg, field, min_value, type, cap) \
708 .matches = has_cpuid_feature, \
710 .field_pos = field, \
711 .min_field_value = min_value, \
712 .hwcap_type = type, \
716 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
717 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
718 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
719 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
720 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
721 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
722 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
723 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
724 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
726 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
727 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
728 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
729 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
730 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
735 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
737 switch (cap->hwcap_type) {
739 elf_hwcap |= cap->hwcap;
742 case CAP_COMPAT_HWCAP:
743 compat_elf_hwcap |= (u32)cap->hwcap;
745 case CAP_COMPAT_HWCAP2:
746 compat_elf_hwcap2 |= (u32)cap->hwcap;
755 /* Check if we have a particular HWCAP enabled */
756 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
760 switch (cap->hwcap_type) {
762 rc = (elf_hwcap & cap->hwcap) != 0;
765 case CAP_COMPAT_HWCAP:
766 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
768 case CAP_COMPAT_HWCAP2:
769 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
780 static void __init setup_cpu_hwcaps(void)
783 const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
785 for (i = 0; hwcaps[i].matches; i++)
786 if (hwcaps[i].matches(&hwcaps[i]))
787 cap_set_hwcap(&hwcaps[i]);
790 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
795 for (i = 0; caps[i].matches; i++) {
796 if (!caps[i].matches(&caps[i]))
799 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
800 pr_info("%s %s\n", info, caps[i].desc);
801 cpus_set_cap(caps[i].capability);
806 * Run through the enabled capabilities and enable() it on all active
810 enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
814 for (i = 0; caps[i].matches; i++)
815 if (caps[i].enable && cpus_have_cap(caps[i].capability))
816 on_each_cpu(caps[i].enable, NULL, true);
819 #ifdef CONFIG_HOTPLUG_CPU
822 * Flag to indicate if we have computed the system wide
823 * capabilities based on the boot time active CPUs. This
824 * will be used to determine if a new booting CPU should
825 * go through the verification process to make sure that it
826 * supports the system capabilities, without using a hotplug
829 static bool sys_caps_initialised;
831 static inline void set_sys_caps_initialised(void)
833 sys_caps_initialised = true;
837 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
839 static u64 __raw_read_system_reg(u32 sys_id)
842 case SYS_ID_PFR0_EL1: return read_cpuid(SYS_ID_PFR0_EL1);
843 case SYS_ID_PFR1_EL1: return read_cpuid(SYS_ID_PFR1_EL1);
844 case SYS_ID_DFR0_EL1: return read_cpuid(SYS_ID_DFR0_EL1);
845 case SYS_ID_MMFR0_EL1: return read_cpuid(SYS_ID_MMFR0_EL1);
846 case SYS_ID_MMFR1_EL1: return read_cpuid(SYS_ID_MMFR1_EL1);
847 case SYS_ID_MMFR2_EL1: return read_cpuid(SYS_ID_MMFR2_EL1);
848 case SYS_ID_MMFR3_EL1: return read_cpuid(SYS_ID_MMFR3_EL1);
849 case SYS_ID_ISAR0_EL1: return read_cpuid(SYS_ID_ISAR0_EL1);
850 case SYS_ID_ISAR1_EL1: return read_cpuid(SYS_ID_ISAR1_EL1);
851 case SYS_ID_ISAR2_EL1: return read_cpuid(SYS_ID_ISAR2_EL1);
852 case SYS_ID_ISAR3_EL1: return read_cpuid(SYS_ID_ISAR3_EL1);
853 case SYS_ID_ISAR4_EL1: return read_cpuid(SYS_ID_ISAR4_EL1);
854 case SYS_ID_ISAR5_EL1: return read_cpuid(SYS_ID_ISAR4_EL1);
855 case SYS_MVFR0_EL1: return read_cpuid(SYS_MVFR0_EL1);
856 case SYS_MVFR1_EL1: return read_cpuid(SYS_MVFR1_EL1);
857 case SYS_MVFR2_EL1: return read_cpuid(SYS_MVFR2_EL1);
859 case SYS_ID_AA64PFR0_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1);
860 case SYS_ID_AA64PFR1_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1);
861 case SYS_ID_AA64DFR0_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1);
862 case SYS_ID_AA64DFR1_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1);
863 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(SYS_ID_AA64MMFR0_EL1);
864 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(SYS_ID_AA64MMFR1_EL1);
865 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(SYS_ID_AA64MMFR2_EL1);
866 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(SYS_ID_AA64ISAR0_EL1);
867 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(SYS_ID_AA64ISAR1_EL1);
869 case SYS_CNTFRQ_EL0: return read_cpuid(SYS_CNTFRQ_EL0);
870 case SYS_CTR_EL0: return read_cpuid(SYS_CTR_EL0);
871 case SYS_DCZID_EL0: return read_cpuid(SYS_DCZID_EL0);
879 * Park the CPU which doesn't have the capability as advertised
882 static void fail_incapable_cpu(char *cap_type,
883 const struct arm64_cpu_capabilities *cap)
885 int cpu = smp_processor_id();
887 pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
888 /* Mark this CPU absent */
889 set_cpu_present(cpu, 0);
891 /* Check if we can park ourselves */
892 if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
893 cpu_ops[cpu]->cpu_die(cpu);
901 * Run through the enabled system capabilities and enable() it on this CPU.
902 * The capabilities were decided based on the available CPUs at the boot time.
903 * Any new CPU should match the system wide status of the capability. If the
904 * new CPU doesn't have a capability which the system now has enabled, we
905 * cannot do anything to fix it up and could cause unexpected failures. So
908 void verify_local_cpu_capabilities(void)
911 const struct arm64_cpu_capabilities *caps;
914 * If we haven't computed the system capabilities, there is nothing
917 if (!sys_caps_initialised)
920 caps = arm64_features;
921 for (i = 0; caps[i].matches; i++) {
922 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
925 * If the new CPU misses an advertised feature, we cannot proceed
926 * further, park the cpu.
928 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
929 fail_incapable_cpu("arm64_features", &caps[i]);
931 caps[i].enable(NULL);
934 for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
935 if (!cpus_have_hwcap(&caps[i]))
937 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
938 fail_incapable_cpu("arm64_hwcaps", &caps[i]);
942 #else /* !CONFIG_HOTPLUG_CPU */
944 static inline void set_sys_caps_initialised(void)
948 #endif /* CONFIG_HOTPLUG_CPU */
950 static void __init setup_feature_capabilities(void)
952 update_cpu_capabilities(arm64_features, "detected feature:");
953 enable_cpu_capabilities(arm64_features);
956 void __init setup_cpu_features(void)
961 /* Set the CPU feature capabilies */
962 setup_feature_capabilities();
965 /* Advertise that we have computed the system capabilities */
966 set_sys_caps_initialised();
969 * Check for sane CTR_EL0.CWG value.
971 cwg = cache_type_cwg();
972 cls = cache_line_size();
974 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
976 if (L1_CACHE_BYTES < cls)
977 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
978 L1_CACHE_BYTES, cls);
981 static bool __maybe_unused
982 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
984 return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));