2 * Record and handle CPU attributes.
4 * Copyright (C) 2014 ARM Ltd.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <asm/arch_timer.h>
18 #include <asm/cachetype.h>
20 #include <asm/cputype.h>
21 #include <asm/cpufeature.h>
23 #include <linux/bitops.h>
24 #include <linux/bug.h>
25 #include <linux/compat.h>
26 #include <linux/elf.h>
27 #include <linux/init.h>
28 #include <linux/kernel.h>
29 #include <linux/personality.h>
30 #include <linux/preempt.h>
31 #include <linux/printk.h>
32 #include <linux/seq_file.h>
33 #include <linux/sched.h>
34 #include <linux/smp.h>
35 #include <linux/delay.h>
38 * In case the boot CPU is hotpluggable, we record its initial state and
39 * current state separately. Certain system registers may contain different
40 * values depending on configuration at or after reset.
42 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
43 static struct cpuinfo_arm64 boot_cpu_data;
45 static char *icache_policy_str[] = {
46 [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
47 [ICACHE_POLICY_AIVIVT] = "AIVIVT",
48 [ICACHE_POLICY_VIPT] = "VIPT",
49 [ICACHE_POLICY_PIPT] = "PIPT",
52 unsigned long __icache_flags;
54 static const char *const hwcap_str[] = {
68 static const char *const compat_hwcap_str[] = {
94 static const char *const compat_hwcap2_str[] = {
102 #endif /* CONFIG_COMPAT */
104 static int c_show(struct seq_file *m, void *v)
107 bool compat = personality(current->personality) == PER_LINUX32;
109 for_each_online_cpu(i) {
110 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
111 u32 midr = cpuinfo->reg_midr;
114 * glibc reads /proc/cpuinfo to determine the number of
115 * online processors, looking for lines beginning with
116 * "processor". Give glibc what it expects.
118 seq_printf(m, "processor\t: %d\n", i);
120 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
121 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
123 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
124 loops_per_jiffy / (500000UL/HZ),
125 loops_per_jiffy / (5000UL/HZ) % 100);
128 * Dump out the common processor features in a single line.
129 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
130 * rather than attempting to parse this, but there's a body of
131 * software which does already (at least for 32-bit).
133 seq_puts(m, "Features\t:");
136 for (j = 0; compat_hwcap_str[j]; j++)
137 if (compat_elf_hwcap & (1 << j))
138 seq_printf(m, " %s", compat_hwcap_str[j]);
140 for (j = 0; compat_hwcap2_str[j]; j++)
141 if (compat_elf_hwcap2 & (1 << j))
142 seq_printf(m, " %s", compat_hwcap2_str[j]);
143 #endif /* CONFIG_COMPAT */
145 for (j = 0; hwcap_str[j]; j++)
146 if (elf_hwcap & (1 << j))
147 seq_printf(m, " %s", hwcap_str[j]);
151 seq_printf(m, "CPU implementer\t: 0x%02x\n",
152 MIDR_IMPLEMENTOR(midr));
153 seq_printf(m, "CPU architecture: 8\n");
154 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
155 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
156 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
162 static void *c_start(struct seq_file *m, loff_t *pos)
164 return *pos < 1 ? (void *)1 : NULL;
167 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
173 static void c_stop(struct seq_file *m, void *v)
177 const struct seq_operations cpuinfo_op = {
184 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
186 unsigned int cpu = smp_processor_id();
187 u32 l1ip = CTR_L1IP(info->reg_ctr);
189 if (l1ip != ICACHE_POLICY_PIPT) {
191 * VIPT caches are non-aliasing if the VA always equals the PA
192 * in all bit positions that are covered by the index. This is
193 * the case if the size of a way (# of sets * line size) does
194 * not exceed PAGE_SIZE.
196 u32 waysize = icache_get_numsets() * icache_get_linesize();
198 if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE)
199 set_bit(ICACHEF_ALIASING, &__icache_flags);
201 if (l1ip == ICACHE_POLICY_AIVIVT)
202 set_bit(ICACHEF_AIVIVT, &__icache_flags);
204 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
207 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
209 info->reg_cntfrq = arch_timer_get_cntfrq();
210 info->reg_ctr = read_cpuid_cachetype();
211 info->reg_dczid = read_cpuid(SYS_DCZID_EL0);
212 info->reg_midr = read_cpuid_id();
214 info->reg_id_aa64dfr0 = read_cpuid(SYS_ID_AA64DFR0_EL1);
215 info->reg_id_aa64dfr1 = read_cpuid(SYS_ID_AA64DFR1_EL1);
216 info->reg_id_aa64isar0 = read_cpuid(SYS_ID_AA64ISAR0_EL1);
217 info->reg_id_aa64isar1 = read_cpuid(SYS_ID_AA64ISAR1_EL1);
218 info->reg_id_aa64mmfr0 = read_cpuid(SYS_ID_AA64MMFR0_EL1);
219 info->reg_id_aa64mmfr1 = read_cpuid(SYS_ID_AA64MMFR1_EL1);
220 info->reg_id_aa64mmfr2 = read_cpuid(SYS_ID_AA64MMFR2_EL1);
221 info->reg_id_aa64pfr0 = read_cpuid(SYS_ID_AA64PFR0_EL1);
222 info->reg_id_aa64pfr1 = read_cpuid(SYS_ID_AA64PFR1_EL1);
224 info->reg_id_dfr0 = read_cpuid(SYS_ID_DFR0_EL1);
225 info->reg_id_isar0 = read_cpuid(SYS_ID_ISAR0_EL1);
226 info->reg_id_isar1 = read_cpuid(SYS_ID_ISAR1_EL1);
227 info->reg_id_isar2 = read_cpuid(SYS_ID_ISAR2_EL1);
228 info->reg_id_isar3 = read_cpuid(SYS_ID_ISAR3_EL1);
229 info->reg_id_isar4 = read_cpuid(SYS_ID_ISAR4_EL1);
230 info->reg_id_isar5 = read_cpuid(SYS_ID_ISAR5_EL1);
231 info->reg_id_mmfr0 = read_cpuid(SYS_ID_MMFR0_EL1);
232 info->reg_id_mmfr1 = read_cpuid(SYS_ID_MMFR1_EL1);
233 info->reg_id_mmfr2 = read_cpuid(SYS_ID_MMFR2_EL1);
234 info->reg_id_mmfr3 = read_cpuid(SYS_ID_MMFR3_EL1);
235 info->reg_id_pfr0 = read_cpuid(SYS_ID_PFR0_EL1);
236 info->reg_id_pfr1 = read_cpuid(SYS_ID_PFR1_EL1);
238 info->reg_mvfr0 = read_cpuid(SYS_MVFR0_EL1);
239 info->reg_mvfr1 = read_cpuid(SYS_MVFR1_EL1);
240 info->reg_mvfr2 = read_cpuid(SYS_MVFR2_EL1);
242 cpuinfo_detect_icache_policy(info);
244 check_local_cpu_errata();
247 void cpuinfo_store_cpu(void)
249 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
250 __cpuinfo_store_cpu(info);
251 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
254 void __init cpuinfo_store_boot_cpu(void)
256 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
257 __cpuinfo_store_cpu(info);
259 boot_cpu_data = *info;
260 init_cpu_features(&boot_cpu_data);