2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
31 #include <asm/memory.h>
32 #include <asm/ptrace.h>
33 #include <asm/thread_info.h>
34 #include <asm/uaccess.h>
35 #include <asm/asm-uaccess.h>
36 #include <asm/unistd.h>
39 * Context tracking subsystem. Used to instrument transitions
40 * between user and kernel mode.
42 .macro ct_user_exit, syscall = 0
43 #ifdef CONFIG_CONTEXT_TRACKING
44 bl context_tracking_user_exit
47 * Save/restore needed during syscalls. Restore syscall arguments from
48 * the values already saved on stack during kernel_entry.
51 ldp x2, x3, [sp, #S_X2]
52 ldp x4, x5, [sp, #S_X4]
53 ldp x6, x7, [sp, #S_X6]
59 #ifdef CONFIG_CONTEXT_TRACKING
60 bl context_tracking_user_enter
73 .macro kernel_entry, el, regsize = 64
74 sub sp, sp, #S_FRAME_SIZE
76 mov w0, w0 // zero upper 32 bits of x0
78 stp x0, x1, [sp, #16 * 0]
79 stp x2, x3, [sp, #16 * 1]
80 stp x4, x5, [sp, #16 * 2]
81 stp x6, x7, [sp, #16 * 3]
82 stp x8, x9, [sp, #16 * 4]
83 stp x10, x11, [sp, #16 * 5]
84 stp x12, x13, [sp, #16 * 6]
85 stp x14, x15, [sp, #16 * 7]
86 stp x16, x17, [sp, #16 * 8]
87 stp x18, x19, [sp, #16 * 9]
88 stp x20, x21, [sp, #16 * 10]
89 stp x22, x23, [sp, #16 * 11]
90 stp x24, x25, [sp, #16 * 12]
91 stp x26, x27, [sp, #16 * 13]
92 stp x28, x29, [sp, #16 * 14]
97 and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear,
98 ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
99 disable_step_tsk x19, x20 // exceptions when scheduling.
101 mov x29, xzr // fp pointed to user-space
103 add x21, sp, #S_FRAME_SIZE
105 /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
106 ldr x20, [tsk, #TI_ADDR_LIMIT]
107 str x20, [sp, #S_ORIG_ADDR_LIMIT]
108 mov x20, #TASK_SIZE_64
109 str x20, [tsk, #TI_ADDR_LIMIT]
110 .endif /* \el == 0 */
113 stp lr, x21, [sp, #S_LR]
115 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
117 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
118 * EL0, there is no need to check the state of TTBR0_EL1 since
119 * accesses are always enabled.
120 * Note that the meaning of this bit differs from the ARMv8.1 PAN
121 * feature as all TTBR0_EL1 accesses are disabled, not just those to
124 alternative_if ARM64_HAS_PAN
125 b 1f // skip TTBR0 PAN
126 alternative_else_nop_endif
130 tst x21, #0xffff << 48 // Check for the reserved ASID
131 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
132 b.eq 1f // TTBR0 access already disabled
133 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
136 __uaccess_ttbr0_disable x21
140 stp x22, x23, [sp, #S_PC]
143 * Set syscallno to -1 by default (overridden later if real syscall).
147 str x21, [sp, #S_SYSCALLNO]
151 * Set sp_el0 to current thread_info.
158 * Registers that may be useful after this macro is invoked:
162 * x23 - aborted PSTATE
166 .macro kernel_exit, el
168 /* Restore the task's original addr_limit. */
169 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
170 str x20, [tsk, #TI_ADDR_LIMIT]
173 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
178 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
180 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
183 alternative_if ARM64_HAS_PAN
184 b 2f // skip TTBR0 PAN
185 alternative_else_nop_endif
188 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
191 __uaccess_ttbr0_enable x0
195 * Enable errata workarounds only if returning to user. The only
196 * workaround currently required for TTBR0_EL1 changes are for the
197 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
200 post_ttbr0_update_workaround
204 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
210 ldr x23, [sp, #S_SP] // load return stack pointer
212 #ifdef CONFIG_ARM64_ERRATUM_845719
213 alternative_if_not ARM64_WORKAROUND_845719
216 #ifdef CONFIG_PID_IN_CONTEXTIDR
221 #ifdef CONFIG_PID_IN_CONTEXTIDR
222 mrs x29, contextidr_el1
223 msr contextidr_el1, x29
225 msr contextidr_el1, xzr
232 msr elr_el1, x21 // set up the return data
234 ldp x0, x1, [sp, #16 * 0]
235 ldp x2, x3, [sp, #16 * 1]
236 ldp x4, x5, [sp, #16 * 2]
237 ldp x6, x7, [sp, #16 * 3]
238 ldp x8, x9, [sp, #16 * 4]
239 ldp x10, x11, [sp, #16 * 5]
240 ldp x12, x13, [sp, #16 * 6]
241 ldp x14, x15, [sp, #16 * 7]
242 ldp x16, x17, [sp, #16 * 8]
243 ldp x18, x19, [sp, #16 * 9]
244 ldp x20, x21, [sp, #16 * 10]
245 ldp x22, x23, [sp, #16 * 11]
246 ldp x24, x25, [sp, #16 * 12]
247 ldp x26, x27, [sp, #16 * 13]
248 ldp x28, x29, [sp, #16 * 14]
250 add sp, sp, #S_FRAME_SIZE // restore sp
251 eret // return to kernel
254 .macro irq_stack_entry
255 mov x19, sp // preserve the original sp
258 * Compare sp with the current thread_info, if the top
259 * ~(THREAD_SIZE - 1) bits match, we are on a task stack, and
260 * should switch to the irq stack.
262 and x25, x19, #~(THREAD_SIZE - 1)
266 this_cpu_ptr irq_stack, x25, x26
267 mov x26, #IRQ_STACK_START_SP
270 /* switch to the irq stack */
274 * Add a dummy stack frame, this non-standard format is fixed up
277 stp x29, x19, [sp, #-16]!
284 * x19 should be preserved between irq_stack_entry and
287 .macro irq_stack_exit
292 * These are the registers used in the syscall handler, and allow us to
293 * have in theory up to 7 arguments to a function - x0 to x6.
295 * x7 is reserved for the system call number in 32-bit mode.
297 sc_nr .req x25 // number of system calls
298 scno .req x26 // syscall number
299 stbl .req x27 // syscall table pointer
300 tsk .req x28 // current thread_info
303 * Interrupt handling.
306 ldr_l x1, handle_arch_irq
318 .pushsection ".entry.text", "ax"
322 ventry el1_sync_invalid // Synchronous EL1t
323 ventry el1_irq_invalid // IRQ EL1t
324 ventry el1_fiq_invalid // FIQ EL1t
325 ventry el1_error_invalid // Error EL1t
327 ventry el1_sync // Synchronous EL1h
328 ventry el1_irq // IRQ EL1h
329 ventry el1_fiq_invalid // FIQ EL1h
330 ventry el1_error_invalid // Error EL1h
332 ventry el0_sync // Synchronous 64-bit EL0
333 ventry el0_irq // IRQ 64-bit EL0
334 ventry el0_fiq_invalid // FIQ 64-bit EL0
335 ventry el0_error_invalid // Error 64-bit EL0
338 ventry el0_sync_compat // Synchronous 32-bit EL0
339 ventry el0_irq_compat // IRQ 32-bit EL0
340 ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
341 ventry el0_error_invalid_compat // Error 32-bit EL0
343 ventry el0_sync_invalid // Synchronous 32-bit EL0
344 ventry el0_irq_invalid // IRQ 32-bit EL0
345 ventry el0_fiq_invalid // FIQ 32-bit EL0
346 ventry el0_error_invalid // Error 32-bit EL0
351 * Invalid mode handlers
353 .macro inv_entry, el, reason, regsize = 64
354 kernel_entry \el, \regsize
362 inv_entry 0, BAD_SYNC
363 ENDPROC(el0_sync_invalid)
367 ENDPROC(el0_irq_invalid)
371 ENDPROC(el0_fiq_invalid)
374 inv_entry 0, BAD_ERROR
375 ENDPROC(el0_error_invalid)
378 el0_fiq_invalid_compat:
379 inv_entry 0, BAD_FIQ, 32
380 ENDPROC(el0_fiq_invalid_compat)
382 el0_error_invalid_compat:
383 inv_entry 0, BAD_ERROR, 32
384 ENDPROC(el0_error_invalid_compat)
388 inv_entry 1, BAD_SYNC
389 ENDPROC(el1_sync_invalid)
393 ENDPROC(el1_irq_invalid)
397 ENDPROC(el1_fiq_invalid)
400 inv_entry 1, BAD_ERROR
401 ENDPROC(el1_error_invalid)
409 mrs x1, esr_el1 // read the syndrome register
410 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
411 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
413 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
415 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
417 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
419 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
421 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
423 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
429 * Fall through to the Data abort case
433 * Data abort handling
437 // re-enable interrupts if they were enabled in the aborted context
438 tbnz x23, #7, 1f // PSR_I_BIT
441 clear_address_tag x0, x3
442 mov x2, sp // struct pt_regs
445 // disable interrupts before pulling preserved data off the stack
450 * Stack or PC alignment exception handling
458 * Undefined instruction
465 * Debug exception handling
467 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
468 cinc x24, x24, eq // set bit '0'
469 tbz x24, #0, el1_inv // EL1 only
471 mov x2, sp // struct pt_regs
472 bl do_debug_exception
475 // TODO: add support for undefined instructions in kernel mode
487 #ifdef CONFIG_TRACE_IRQFLAGS
488 bl trace_hardirqs_off
494 #ifdef CONFIG_PREEMPT
495 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
496 cbnz w24, 1f // preempt count != 0
497 ldr x0, [tsk, #TI_FLAGS] // get flags
498 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
502 #ifdef CONFIG_TRACE_IRQFLAGS
508 #ifdef CONFIG_PREEMPT
511 1: bl preempt_schedule_irq // irq en/disable is done inside
512 ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
513 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
523 mrs x25, esr_el1 // read the syndrome register
524 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
525 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
527 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
529 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
531 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
533 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
535 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
537 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
539 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
541 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
543 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
551 mrs x25, esr_el1 // read the syndrome register
552 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
553 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
555 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
557 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
559 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
561 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
563 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
565 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
567 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
569 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
571 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
573 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
575 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
577 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
582 * AArch32 syscall handling
584 adrp stbl, compat_sys_call_table // load compat syscall table pointer
585 uxtw scno, w7 // syscall number in w7 (r7)
586 mov sc_nr, #__NR_compat_syscalls
597 * Data abort handling
600 // enable interrupts before calling the main handler
603 clear_address_tag x0, x26
610 * Instruction abort handling
613 // enable interrupts before calling the main handler
623 * Floating Point or Advanced SIMD access
633 * Floating Point or Advanced SIMD exception
643 * Stack or PC alignment exception handling
646 // enable interrupts before calling the main handler
656 * Undefined instruction
658 // enable interrupts before calling the main handler
666 * Debug exception handling
668 tbnz x24, #0, el0_inv // EL0 only
672 bl do_debug_exception
691 #ifdef CONFIG_TRACE_IRQFLAGS
692 bl trace_hardirqs_off
698 #ifdef CONFIG_TRACE_IRQFLAGS
705 * Register switch for AArch64. The callee-saved registers need to be saved
706 * and restored. On entry:
707 * x0 = previous task_struct (must be preserved across the switch)
708 * x1 = next task_struct
709 * Previous and next are guaranteed not to be the same.
713 mov x10, #THREAD_CPU_CONTEXT
716 stp x19, x20, [x8], #16 // store callee-saved registers
717 stp x21, x22, [x8], #16
718 stp x23, x24, [x8], #16
719 stp x25, x26, [x8], #16
720 stp x27, x28, [x8], #16
721 stp x29, x9, [x8], #16
724 ldp x19, x20, [x8], #16 // restore callee-saved registers
725 ldp x21, x22, [x8], #16
726 ldp x23, x24, [x8], #16
727 ldp x25, x26, [x8], #16
728 ldp x27, x28, [x8], #16
729 ldp x29, x9, [x8], #16
732 and x9, x9, #~(THREAD_SIZE - 1)
735 ENDPROC(cpu_switch_to)
738 * This is the fast syscall return path. We do as little as possible here,
739 * and this includes saving x0 back into the kernel stack.
742 disable_irq // disable interrupts
743 str x0, [sp, #S_X0] // returned x0
744 ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing
745 and x2, x1, #_TIF_SYSCALL_WORK
746 cbnz x2, ret_fast_syscall_trace
747 and x2, x1, #_TIF_WORK_MASK
748 cbnz x2, work_pending
749 enable_step_tsk x1, x2
751 ret_fast_syscall_trace:
752 enable_irq // enable interrupts
753 b __sys_trace_return_skipped // we already saved x0
756 * Ok, we need to do extra processing, enter the slow path.
759 tbnz x1, #TIF_NEED_RESCHED, work_resched
760 /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */
762 enable_irq // enable interrupts for do_notify_resume()
766 #ifdef CONFIG_TRACE_IRQFLAGS
767 bl trace_hardirqs_off // the IRQs are off here, inform the tracing code
772 * "slow" syscall return path.
775 disable_irq // disable interrupts
776 ldr x1, [tsk, #TI_FLAGS]
777 and x2, x1, #_TIF_WORK_MASK
778 cbnz x2, work_pending
779 enable_step_tsk x1, x2
784 * This is how we return from a fork.
788 cbz x19, 1f // not a kernel thread
791 1: get_thread_info tsk
793 ENDPROC(ret_from_fork)
800 adrp stbl, sys_call_table // load syscall table pointer
801 uxtw scno, w8 // syscall number in w8
802 mov sc_nr, #__NR_syscalls
803 el0_svc_naked: // compat entry point
804 stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
808 ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks
809 tst x16, #_TIF_SYSCALL_WORK
811 cmp scno, sc_nr // check upper syscall limit
813 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
814 blr x16 // call sys_* routine
823 * This is the really slow path. We're going to be doing context
824 * switches, and waiting for our parent to respond.
827 mov w0, #-1 // set default errno for
828 cmp scno, x0 // user-issued syscall(-1)
833 bl syscall_trace_enter
834 cmp w0, #-1 // skip the syscall?
835 b.eq __sys_trace_return_skipped
836 uxtw scno, w0 // syscall number (possibly new)
837 mov x1, sp // pointer to regs
838 cmp scno, sc_nr // check upper syscall limit
840 ldp x0, x1, [sp] // restore the syscall args
841 ldp x2, x3, [sp, #S_X2]
842 ldp x4, x5, [sp, #S_X4]
843 ldp x6, x7, [sp, #S_X6]
844 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
845 blr x16 // call sys_* routine
848 str x0, [sp, #S_X0] // save returned x0
849 __sys_trace_return_skipped:
851 bl syscall_trace_exit
859 .popsection // .entry.text
862 * Special system call wrappers.
864 ENTRY(sys_rt_sigreturn_wrapper)
867 ENDPROC(sys_rt_sigreturn_wrapper)