2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
31 #include <asm/memory.h>
32 #include <asm/ptrace.h>
33 #include <asm/thread_info.h>
34 #include <asm/uaccess.h>
35 #include <asm/unistd.h>
38 * Context tracking subsystem. Used to instrument transitions
39 * between user and kernel mode.
41 .macro ct_user_exit, syscall = 0
42 #ifdef CONFIG_CONTEXT_TRACKING
43 bl context_tracking_user_exit
46 * Save/restore needed during syscalls. Restore syscall arguments from
47 * the values already saved on stack during kernel_entry.
50 ldp x2, x3, [sp, #S_X2]
51 ldp x4, x5, [sp, #S_X4]
52 ldp x6, x7, [sp, #S_X6]
58 #ifdef CONFIG_CONTEXT_TRACKING
59 bl context_tracking_user_enter
72 .macro kernel_entry, el, regsize = 64
73 sub sp, sp, #S_FRAME_SIZE
75 mov w0, w0 // zero upper 32 bits of x0
77 stp x0, x1, [sp, #16 * 0]
78 stp x2, x3, [sp, #16 * 1]
79 stp x4, x5, [sp, #16 * 2]
80 stp x6, x7, [sp, #16 * 3]
81 stp x8, x9, [sp, #16 * 4]
82 stp x10, x11, [sp, #16 * 5]
83 stp x12, x13, [sp, #16 * 6]
84 stp x14, x15, [sp, #16 * 7]
85 stp x16, x17, [sp, #16 * 8]
86 stp x18, x19, [sp, #16 * 9]
87 stp x20, x21, [sp, #16 * 10]
88 stp x22, x23, [sp, #16 * 11]
89 stp x24, x25, [sp, #16 * 12]
90 stp x26, x27, [sp, #16 * 13]
91 stp x28, x29, [sp, #16 * 14]
96 and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear,
97 ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
98 disable_step_tsk x19, x20 // exceptions when scheduling.
100 mov x29, xzr // fp pointed to user-space
102 add x21, sp, #S_FRAME_SIZE
104 /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
105 ldr x20, [tsk, #TI_ADDR_LIMIT]
106 str x20, [sp, #S_ORIG_ADDR_LIMIT]
107 mov x20, #TASK_SIZE_64
108 str x20, [tsk, #TI_ADDR_LIMIT]
109 .endif /* \el == 0 */
112 stp lr, x21, [sp, #S_LR]
114 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
116 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
117 * EL0, there is no need to check the state of TTBR0_EL1 since
118 * accesses are always enabled.
119 * Note that the meaning of this bit differs from the ARMv8.1 PAN
120 * feature as all TTBR0_EL1 accesses are disabled, not just those to
123 alternative_if_not ARM64_HAS_PAN
126 b 1f // skip TTBR0 PAN
131 tst x21, #0xffff << 48 // Check for the reserved ASID
132 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
133 b.eq 1f // TTBR0 access already disabled
134 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
137 uaccess_ttbr0_disable x21
141 stp x22, x23, [sp, #S_PC]
144 * Set syscallno to -1 by default (overridden later if real syscall).
148 str x21, [sp, #S_SYSCALLNO]
152 * Set sp_el0 to current thread_info.
159 * Registers that may be useful after this macro is invoked:
163 * x23 - aborted PSTATE
167 .macro kernel_exit, el
169 /* Restore the task's original addr_limit. */
170 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
171 str x20, [tsk, #TI_ADDR_LIMIT]
174 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
179 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
181 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
184 alternative_if_not ARM64_HAS_PAN
187 b 2f // skip TTBR0 PAN
191 tbnz x22, #_PSR_PAN_BIT, 1f // Skip re-enabling TTBR0 access if previously disabled
194 uaccess_ttbr0_enable x0
198 * Enable errata workarounds only if returning to user. The only
199 * workaround currently required for TTBR0_EL1 changes are for the
200 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
203 post_ttbr0_update_workaround
207 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
213 ldr x23, [sp, #S_SP] // load return stack pointer
215 #ifdef CONFIG_ARM64_ERRATUM_845719
216 alternative_if_not ARM64_WORKAROUND_845719
219 #ifdef CONFIG_PID_IN_CONTEXTIDR
224 #ifdef CONFIG_PID_IN_CONTEXTIDR
225 mrs x29, contextidr_el1
226 msr contextidr_el1, x29
228 msr contextidr_el1, xzr
235 msr elr_el1, x21 // set up the return data
237 ldp x0, x1, [sp, #16 * 0]
238 ldp x2, x3, [sp, #16 * 1]
239 ldp x4, x5, [sp, #16 * 2]
240 ldp x6, x7, [sp, #16 * 3]
241 ldp x8, x9, [sp, #16 * 4]
242 ldp x10, x11, [sp, #16 * 5]
243 ldp x12, x13, [sp, #16 * 6]
244 ldp x14, x15, [sp, #16 * 7]
245 ldp x16, x17, [sp, #16 * 8]
246 ldp x18, x19, [sp, #16 * 9]
247 ldp x20, x21, [sp, #16 * 10]
248 ldp x22, x23, [sp, #16 * 11]
249 ldp x24, x25, [sp, #16 * 12]
250 ldp x26, x27, [sp, #16 * 13]
251 ldp x28, x29, [sp, #16 * 14]
253 add sp, sp, #S_FRAME_SIZE // restore sp
254 eret // return to kernel
257 .macro irq_stack_entry
258 mov x19, sp // preserve the original sp
261 * Compare sp with the current thread_info, if the top
262 * ~(THREAD_SIZE - 1) bits match, we are on a task stack, and
263 * should switch to the irq stack.
265 and x25, x19, #~(THREAD_SIZE - 1)
269 this_cpu_ptr irq_stack, x25, x26
270 mov x26, #IRQ_STACK_START_SP
273 /* switch to the irq stack */
277 * Add a dummy stack frame, this non-standard format is fixed up
280 stp x29, x19, [sp, #-16]!
287 * x19 should be preserved between irq_stack_entry and
290 .macro irq_stack_exit
295 * These are the registers used in the syscall handler, and allow us to
296 * have in theory up to 7 arguments to a function - x0 to x6.
298 * x7 is reserved for the system call number in 32-bit mode.
300 sc_nr .req x25 // number of system calls
301 scno .req x26 // syscall number
302 stbl .req x27 // syscall table pointer
303 tsk .req x28 // current thread_info
306 * Interrupt handling.
309 ldr_l x1, handle_arch_irq
321 .pushsection ".entry.text", "ax"
325 ventry el1_sync_invalid // Synchronous EL1t
326 ventry el1_irq_invalid // IRQ EL1t
327 ventry el1_fiq_invalid // FIQ EL1t
328 ventry el1_error_invalid // Error EL1t
330 ventry el1_sync // Synchronous EL1h
331 ventry el1_irq // IRQ EL1h
332 ventry el1_fiq_invalid // FIQ EL1h
333 ventry el1_error_invalid // Error EL1h
335 ventry el0_sync // Synchronous 64-bit EL0
336 ventry el0_irq // IRQ 64-bit EL0
337 ventry el0_fiq_invalid // FIQ 64-bit EL0
338 ventry el0_error_invalid // Error 64-bit EL0
341 ventry el0_sync_compat // Synchronous 32-bit EL0
342 ventry el0_irq_compat // IRQ 32-bit EL0
343 ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
344 ventry el0_error_invalid_compat // Error 32-bit EL0
346 ventry el0_sync_invalid // Synchronous 32-bit EL0
347 ventry el0_irq_invalid // IRQ 32-bit EL0
348 ventry el0_fiq_invalid // FIQ 32-bit EL0
349 ventry el0_error_invalid // Error 32-bit EL0
354 * Invalid mode handlers
356 .macro inv_entry, el, reason, regsize = 64
357 kernel_entry \el, \regsize
365 inv_entry 0, BAD_SYNC
366 ENDPROC(el0_sync_invalid)
370 ENDPROC(el0_irq_invalid)
374 ENDPROC(el0_fiq_invalid)
377 inv_entry 0, BAD_ERROR
378 ENDPROC(el0_error_invalid)
381 el0_fiq_invalid_compat:
382 inv_entry 0, BAD_FIQ, 32
383 ENDPROC(el0_fiq_invalid_compat)
385 el0_error_invalid_compat:
386 inv_entry 0, BAD_ERROR, 32
387 ENDPROC(el0_error_invalid_compat)
391 inv_entry 1, BAD_SYNC
392 ENDPROC(el1_sync_invalid)
396 ENDPROC(el1_irq_invalid)
400 ENDPROC(el1_fiq_invalid)
403 inv_entry 1, BAD_ERROR
404 ENDPROC(el1_error_invalid)
412 mrs x1, esr_el1 // read the syndrome register
413 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
414 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
416 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
418 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
420 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
422 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
424 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
426 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
432 * Fall through to the Data abort case
436 * Data abort handling
440 // re-enable interrupts if they were enabled in the aborted context
441 tbnz x23, #7, 1f // PSR_I_BIT
444 mov x2, sp // struct pt_regs
447 // disable interrupts before pulling preserved data off the stack
452 * Stack or PC alignment exception handling
460 * Undefined instruction
467 * Debug exception handling
469 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
470 cinc x24, x24, eq // set bit '0'
471 tbz x24, #0, el1_inv // EL1 only
473 mov x2, sp // struct pt_regs
474 bl do_debug_exception
477 // TODO: add support for undefined instructions in kernel mode
489 #ifdef CONFIG_TRACE_IRQFLAGS
490 bl trace_hardirqs_off
496 #ifdef CONFIG_PREEMPT
497 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
498 cbnz w24, 1f // preempt count != 0
499 ldr x0, [tsk, #TI_FLAGS] // get flags
500 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
504 #ifdef CONFIG_TRACE_IRQFLAGS
510 #ifdef CONFIG_PREEMPT
513 1: bl preempt_schedule_irq // irq en/disable is done inside
514 ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
515 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
525 mrs x25, esr_el1 // read the syndrome register
526 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
527 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
529 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
531 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
533 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
535 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
537 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
539 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
541 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
543 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
545 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
553 mrs x25, esr_el1 // read the syndrome register
554 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
555 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
557 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
559 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
561 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
563 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
565 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
567 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
569 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
571 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
573 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
575 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
577 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
579 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
584 * AArch32 syscall handling
586 adrp stbl, compat_sys_call_table // load compat syscall table pointer
587 uxtw scno, w7 // syscall number in w7 (r7)
588 mov sc_nr, #__NR_compat_syscalls
599 * Data abort handling
602 // enable interrupts before calling the main handler
605 bic x0, x26, #(0xff << 56)
612 * Instruction abort handling
615 // enable interrupts before calling the main handler
625 * Floating Point or Advanced SIMD access
635 * Floating Point or Advanced SIMD exception
645 * Stack or PC alignment exception handling
648 // enable interrupts before calling the main handler
658 * Undefined instruction
660 // enable interrupts before calling the main handler
668 * Debug exception handling
670 tbnz x24, #0, el0_inv // EL0 only
674 bl do_debug_exception
693 #ifdef CONFIG_TRACE_IRQFLAGS
694 bl trace_hardirqs_off
700 #ifdef CONFIG_TRACE_IRQFLAGS
707 * Register switch for AArch64. The callee-saved registers need to be saved
708 * and restored. On entry:
709 * x0 = previous task_struct (must be preserved across the switch)
710 * x1 = next task_struct
711 * Previous and next are guaranteed not to be the same.
715 mov x10, #THREAD_CPU_CONTEXT
718 stp x19, x20, [x8], #16 // store callee-saved registers
719 stp x21, x22, [x8], #16
720 stp x23, x24, [x8], #16
721 stp x25, x26, [x8], #16
722 stp x27, x28, [x8], #16
723 stp x29, x9, [x8], #16
726 ldp x19, x20, [x8], #16 // restore callee-saved registers
727 ldp x21, x22, [x8], #16
728 ldp x23, x24, [x8], #16
729 ldp x25, x26, [x8], #16
730 ldp x27, x28, [x8], #16
731 ldp x29, x9, [x8], #16
734 and x9, x9, #~(THREAD_SIZE - 1)
737 ENDPROC(cpu_switch_to)
740 * This is the fast syscall return path. We do as little as possible here,
741 * and this includes saving x0 back into the kernel stack.
744 disable_irq // disable interrupts
745 str x0, [sp, #S_X0] // returned x0
746 ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing
747 and x2, x1, #_TIF_SYSCALL_WORK
748 cbnz x2, ret_fast_syscall_trace
749 and x2, x1, #_TIF_WORK_MASK
750 cbnz x2, work_pending
751 enable_step_tsk x1, x2
753 ret_fast_syscall_trace:
754 enable_irq // enable interrupts
755 b __sys_trace_return_skipped // we already saved x0
758 * Ok, we need to do extra processing, enter the slow path.
761 tbnz x1, #TIF_NEED_RESCHED, work_resched
762 /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */
764 enable_irq // enable interrupts for do_notify_resume()
768 #ifdef CONFIG_TRACE_IRQFLAGS
769 bl trace_hardirqs_off // the IRQs are off here, inform the tracing code
774 * "slow" syscall return path.
777 disable_irq // disable interrupts
778 ldr x1, [tsk, #TI_FLAGS]
779 and x2, x1, #_TIF_WORK_MASK
780 cbnz x2, work_pending
781 enable_step_tsk x1, x2
786 * This is how we return from a fork.
790 cbz x19, 1f // not a kernel thread
793 1: get_thread_info tsk
795 ENDPROC(ret_from_fork)
802 adrp stbl, sys_call_table // load syscall table pointer
803 uxtw scno, w8 // syscall number in w8
804 mov sc_nr, #__NR_syscalls
805 el0_svc_naked: // compat entry point
806 stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
810 ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks
811 tst x16, #_TIF_SYSCALL_WORK
813 cmp scno, sc_nr // check upper syscall limit
815 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
816 blr x16 // call sys_* routine
825 * This is the really slow path. We're going to be doing context
826 * switches, and waiting for our parent to respond.
829 mov w0, #-1 // set default errno for
830 cmp scno, x0 // user-issued syscall(-1)
835 bl syscall_trace_enter
836 cmp w0, #-1 // skip the syscall?
837 b.eq __sys_trace_return_skipped
838 uxtw scno, w0 // syscall number (possibly new)
839 mov x1, sp // pointer to regs
840 cmp scno, sc_nr // check upper syscall limit
842 ldp x0, x1, [sp] // restore the syscall args
843 ldp x2, x3, [sp, #S_X2]
844 ldp x4, x5, [sp, #S_X4]
845 ldp x6, x7, [sp, #S_X6]
846 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
847 blr x16 // call sys_* routine
850 str x0, [sp, #S_X0] // save returned x0
851 __sys_trace_return_skipped:
853 bl syscall_trace_exit
861 .popsection // .entry.text
864 * Special system call wrappers.
866 ENTRY(sys_rt_sigreturn_wrapper)
869 ENDPROC(sys_rt_sigreturn_wrapper)