2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
28 #include <asm/ptrace.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cache.h>
31 #include <asm/cputype.h>
33 #include <asm/kernel-pgtable.h>
34 #include <asm/memory.h>
35 #include <asm/pgtable-hwdef.h>
36 #include <asm/pgtable.h>
38 #include <asm/sysreg.h>
39 #include <asm/thread_info.h>
42 #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
44 #if (TEXT_OFFSET & 0xfff) != 0
45 #error TEXT_OFFSET must be at least 4KB aligned
46 #elif (PAGE_OFFSET & 0x1fffff) != 0
47 #error PAGE_OFFSET must be at least 2MB aligned
48 #elif TEXT_OFFSET > 0x1fffff
49 #error TEXT_OFFSET must be less than 2MB
52 #define KERNEL_START _text
53 #define KERNEL_END _end
56 * Kernel startup entry point.
57 * ---------------------------
59 * The requirements are:
60 * MMU = off, D-cache = off, I-cache = on or off,
61 * x0 = physical address to the FDT blob.
63 * This code is mostly position independent so you call this at
64 * __pa(PAGE_OFFSET + TEXT_OFFSET).
66 * Note that the callee-saved registers are used for storing variables
67 * that are useful before the MMU is enabled. The allocations are described
68 * in the entry routines.
73 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
77 * This add instruction has no meaningful effect except that
78 * its opcode forms the magic "MZ" signature required by UEFI.
83 b stext // branch to kernel start, magic
86 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian
87 le64sym _kernel_size_le // Effective size of kernel image, little-endian
88 le64sym _kernel_flags_le // Informative flags, little-endian
92 .byte 0x41 // Magic number, "ARM\x64"
97 .long pe_header - _head // Offset to the PE header.
108 .short 0xaa64 // AArch64
109 .short 2 // nr_sections
110 .long 0 // TimeDateStamp
111 .long 0 // PointerToSymbolTable
112 .long 1 // NumberOfSymbols
113 .short section_table - optional_header // SizeOfOptionalHeader
114 .short 0x206 // Characteristics.
115 // IMAGE_FILE_DEBUG_STRIPPED |
116 // IMAGE_FILE_EXECUTABLE_IMAGE |
117 // IMAGE_FILE_LINE_NUMS_STRIPPED
119 .short 0x20b // PE32+ format
120 .byte 0x02 // MajorLinkerVersion
121 .byte 0x14 // MinorLinkerVersion
122 .long _end - efi_header_end // SizeOfCode
123 .long 0 // SizeOfInitializedData
124 .long 0 // SizeOfUninitializedData
125 .long __efistub_entry - _head // AddressOfEntryPoint
126 .long efi_header_end - _head // BaseOfCode
130 .long 0x1000 // SectionAlignment
131 .long PECOFF_FILE_ALIGNMENT // FileAlignment
132 .short 0 // MajorOperatingSystemVersion
133 .short 0 // MinorOperatingSystemVersion
134 .short 0 // MajorImageVersion
135 .short 0 // MinorImageVersion
136 .short 0 // MajorSubsystemVersion
137 .short 0 // MinorSubsystemVersion
138 .long 0 // Win32VersionValue
140 .long _end - _head // SizeOfImage
142 // Everything before the kernel image is considered part of the header
143 .long efi_header_end - _head // SizeOfHeaders
145 .short 0xa // Subsystem (EFI application)
146 .short 0 // DllCharacteristics
147 .quad 0 // SizeOfStackReserve
148 .quad 0 // SizeOfStackCommit
149 .quad 0 // SizeOfHeapReserve
150 .quad 0 // SizeOfHeapCommit
151 .long 0 // LoaderFlags
152 .long 0x6 // NumberOfRvaAndSizes
154 .quad 0 // ExportTable
155 .quad 0 // ImportTable
156 .quad 0 // ResourceTable
157 .quad 0 // ExceptionTable
158 .quad 0 // CertificationTable
159 .quad 0 // BaseRelocationTable
165 * The EFI application loader requires a relocation section
166 * because EFI applications must be relocatable. This is a
167 * dummy section as far as we are concerned.
171 .byte 0 // end of 0 padding of section name
174 .long 0 // SizeOfRawData
175 .long 0 // PointerToRawData
176 .long 0 // PointerToRelocations
177 .long 0 // PointerToLineNumbers
178 .short 0 // NumberOfRelocations
179 .short 0 // NumberOfLineNumbers
180 .long 0x42100040 // Characteristics (section flags)
186 .byte 0 // end of 0 padding of section name
187 .long _end - efi_header_end // VirtualSize
188 .long efi_header_end - _head // VirtualAddress
189 .long _edata - efi_header_end // SizeOfRawData
190 .long efi_header_end - _head // PointerToRawData
192 .long 0 // PointerToRelocations (0 for executables)
193 .long 0 // PointerToLineNumbers (0 for executables)
194 .short 0 // NumberOfRelocations (0 for executables)
195 .short 0 // NumberOfLineNumbers (0 for executables)
196 .long 0xe0500020 // Characteristics (section flags)
199 * EFI will load .text onwards at the 4k section alignment
200 * described in the PE/COFF header. To ensure that instruction
201 * sequences using an adrp and a :lo12: immediate will function
202 * correctly at this alignment, we must ensure that .text is
203 * placed at a 4k boundary in the Image to begin with.
212 bl preserve_boot_args
213 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
214 mov x23, xzr // KASLR offset, defaults to 0
215 adrp x24, __PHYS_OFFSET
216 bl set_cpu_boot_mode_flag
217 bl __create_page_tables // x25=TTBR0, x26=TTBR1
219 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
221 * On return, the CPU will be ready for the MMU to be turned on and
222 * the TCR will have been set.
224 bl __cpu_setup // initialise processor
225 adr_l x27, __primary_switch // address to jump to after
226 // MMU has been enabled
231 * Preserve the arguments passed by the bootloader in x0 .. x3
234 mov x21, x0 // x21=FDT
236 adr_l x0, boot_args // record the contents of
237 stp x21, x1, [x0] // x0 .. x3 at kernel entry
238 stp x2, x3, [x0, #16]
240 dmb sy // needed before dc ivac with
243 add x1, x0, #0x20 // 4 x 8 bytes
244 b __inval_cache_range // tail call
245 ENDPROC(preserve_boot_args)
248 * Macro to create a table entry to the next page.
250 * tbl: page table address
251 * virt: virtual address
252 * shift: #imm page table shift
253 * ptrs: #imm pointers per table page
256 * Corrupts: tmp1, tmp2
257 * Returns: tbl -> next level table page address
259 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
260 lsr \tmp1, \virt, #\shift
261 and \tmp1, \tmp1, #\ptrs - 1 // table index
262 add \tmp2, \tbl, #PAGE_SIZE
263 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
264 str \tmp2, [\tbl, \tmp1, lsl #3]
265 add \tbl, \tbl, #PAGE_SIZE // next level table page
269 * Macro to populate the PGD (and possibily PUD) for the corresponding
270 * block entry in the next level (tbl) for the given virtual address.
272 * Preserves: tbl, next, virt
273 * Corrupts: tmp1, tmp2
275 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
276 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
277 #if SWAPPER_PGTABLE_LEVELS > 3
278 create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
280 #if SWAPPER_PGTABLE_LEVELS > 2
281 create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
286 * Macro to populate block entries in the page table for the start..end
287 * virtual range (inclusive).
289 * Preserves: tbl, flags
290 * Corrupts: phys, start, end, pstate
292 .macro create_block_map, tbl, flags, phys, start, end
293 lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT
294 lsr \start, \start, #SWAPPER_BLOCK_SHIFT
295 and \start, \start, #PTRS_PER_PTE - 1 // table index
296 orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry
297 lsr \end, \end, #SWAPPER_BLOCK_SHIFT
298 and \end, \end, #PTRS_PER_PTE - 1 // table end index
299 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
300 add \start, \start, #1 // next entry
301 add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block
307 * Setup the initial page tables. We only setup the barest amount which is
308 * required to get the kernel running. The following sections are required:
309 * - identity mapping to enable the MMU (low address, TTBR0)
310 * - first few MB of the kernel linear mapping to jump to once the MMU has
313 __create_page_tables:
314 adrp x25, idmap_pg_dir
315 adrp x26, swapper_pg_dir
319 * Invalidate the idmap and swapper page tables to avoid potential
320 * dirty cache lines being evicted.
323 add x1, x26, #SWAPPER_DIR_SIZE
324 bl __inval_cache_range
327 * Clear the idmap and swapper page tables.
330 add x6, x26, #SWAPPER_DIR_SIZE
331 1: stp xzr, xzr, [x0], #16
332 stp xzr, xzr, [x0], #16
333 stp xzr, xzr, [x0], #16
334 stp xzr, xzr, [x0], #16
338 mov x7, SWAPPER_MM_MMUFLAGS
341 * Create the identity mapping.
343 mov x0, x25 // idmap_pg_dir
344 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
346 #ifndef CONFIG_ARM64_VA_BITS_48
347 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
348 #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT))
351 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be
352 * created that covers system RAM if that is located sufficiently high
353 * in the physical address space. So for the ID map, use an extended
354 * virtual range in that case, by configuring an additional translation
356 * First, we have to verify our assumption that the current value of
357 * VA_BITS was chosen such that all translation levels are fully
358 * utilised, and that lowering T0SZ will always result in an additional
359 * translation level to be configured.
361 #if VA_BITS != EXTRA_SHIFT
362 #error "Mismatch between VA_BITS and page size/number of translation levels"
366 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
367 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
368 * this number conveniently equals the number of leading zeroes in
369 * the physical address of __idmap_text_end.
371 adrp x5, __idmap_text_end
373 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
374 b.ge 1f // .. then skip additional level
379 dc ivac, x6 // Invalidate potentially stale cache line
381 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
385 create_pgd_entry x0, x3, x5, x6
386 mov x5, x3 // __pa(__idmap_text_start)
387 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
388 create_block_map x0, x7, x3, x5, x6
391 * Map the kernel image (starting with PHYS_OFFSET).
393 mov x0, x26 // swapper_pg_dir
394 mov_q x5, KIMAGE_VADDR
395 add x5, x5, x23 // add KASLR displacement
396 create_pgd_entry x0, x5, x3, x6
397 ldr w6, =kernel_img_size
399 mov x3, x24 // phys offset
400 create_block_map x0, x7, x3, x5, x6
403 * Since the page tables have been populated with non-cacheable
404 * accesses (MMU disabled), invalidate the idmap and swapper page
405 * tables again to remove any speculatively loaded cache lines.
408 add x1, x26, #SWAPPER_DIR_SIZE
410 bl __inval_cache_range
413 ENDPROC(__create_page_tables)
417 * The following fragment of code is executed with the MMU enabled.
419 .set initial_sp, init_thread_union + THREAD_START_SP
421 mov x28, lr // preserve LR
422 adr_l x8, vectors // load VBAR_EL1 with virtual
423 msr vbar_el1, x8 // vector table address
427 adr_l x0, __bss_start
432 dsb ishst // Make zero page visible to PTW
434 adr_l sp, initial_sp, x4
436 and x4, x4, #~(THREAD_SIZE - 1)
437 msr sp_el0, x4 // Save thread_info
438 str_l x21, __fdt_pointer, x5 // Save FDT pointer
440 ldr_l x4, kimage_vaddr // Save the offset between
441 sub x4, x4, x24 // the kernel virtual and
442 str_l x4, kimage_voffset, x5 // physical mappings
448 #ifdef CONFIG_RANDOMIZE_BASE
449 cbnz x23, 0f // already running randomized?
450 mov x0, x21 // pass FDT address in x0
451 bl kaslr_early_init // parse FDT for KASLR options
452 cbz x0, 0f // KASLR disabled? just proceed
453 mov x23, x0 // record KASLR offset
454 ret x28 // we must enable KASLR, return
459 ENDPROC(__primary_switched)
462 * end early head section, begin head code that is also used for
463 * hotplug and needs to have the same protections as the text region
465 .section ".text","ax"
468 .quad _text - TEXT_OFFSET
471 * If we're fortunate enough to boot at EL2, ensure that the world is
472 * sane before dropping to EL1.
474 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
475 * booted in EL1 or EL2 respectively.
479 cmp x0, #CurrentEL_EL2
482 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
483 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
487 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
488 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
490 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
494 /* Hyp configuration. */
495 2: mov x0, #(1 << 31) // 64-bit EL1
498 /* Generic timers. */
500 orr x0, x0, #3 // Enable EL1 physical timers
502 msr cntvoff_el2, xzr // Clear virtual offset
504 #ifdef CONFIG_ARM_GIC_V3
505 /* GICv3 system register access */
506 mrs x0, id_aa64pfr0_el1
511 mrs_s x0, ICC_SRE_EL2
512 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
513 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
514 msr_s ICC_SRE_EL2, x0
515 isb // Make sure SRE is now set
516 mrs_s x0, ICC_SRE_EL2 // Read SRE back,
517 tbz x0, #0, 3f // and check that it sticks
518 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
523 /* Populate ID registers. */
530 mov x0, #0x0800 // Set/clear RES{1,0} bits
531 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
532 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
535 /* Coprocessor traps. */
537 msr cptr_el2, x0 // Disable copro. traps to EL2
540 msr hstr_el2, xzr // Disable CP15 traps to EL2
544 mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
547 b.lt 4f // Skip if no PMU present
548 mrs x0, pmcr_el0 // Disable debug access traps
549 ubfx x0, x0, #11, #5 // to EL2 and allow access to
550 msr mdcr_el2, x0 // all PMU counters from EL1
553 /* Stage-2 translation */
556 /* Hypervisor stub */
557 adrp x0, __hyp_stub_vectors
558 add x0, x0, #:lo12:__hyp_stub_vectors
562 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
566 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
571 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
572 * in x20. See arch/arm64/include/asm/virt.h for more info.
574 set_cpu_boot_mode_flag:
575 adr_l x1, __boot_cpu_mode
576 cmp w20, #BOOT_CPU_MODE_EL2
579 1: str w20, [x1] // This CPU has booted in EL1
581 dc ivac, x1 // Invalidate potentially stale cache line
583 ENDPROC(set_cpu_boot_mode_flag)
586 * We need to find out the CPU boot mode long after boot, so we need to
587 * store it in a writable variable.
589 * This is not in .bss, because we set it sufficiently early that the boot-time
590 * zeroing of .bss would clobber it.
592 .pushsection .data..cacheline_aligned
593 .align L1_CACHE_SHIFT
594 ENTRY(__boot_cpu_mode)
595 .long BOOT_CPU_MODE_EL2
596 .long BOOT_CPU_MODE_EL1
600 * This provides a "holding pen" for platforms to hold all secondary
601 * cores are held until we're ready for them to initialise.
603 ENTRY(secondary_holding_pen)
604 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
605 bl set_cpu_boot_mode_flag
607 mov_q x1, MPIDR_HWID_BITMASK
609 adr_l x3, secondary_holding_pen_release
612 b.eq secondary_startup
615 ENDPROC(secondary_holding_pen)
618 * Secondary entry point that jumps straight into the kernel. Only to
619 * be used where CPUs are brought online dynamically by the kernel.
621 ENTRY(secondary_entry)
622 bl el2_setup // Drop to EL1
623 bl set_cpu_boot_mode_flag
625 ENDPROC(secondary_entry)
629 * Common entry point for secondary CPUs.
631 adrp x25, idmap_pg_dir
632 adrp x26, swapper_pg_dir
633 bl __cpu_setup // initialise processor
635 adr_l x27, __secondary_switch // address to jump to after enabling the MMU
637 ENDPROC(secondary_startup)
639 __secondary_switched:
644 ldr_l x0, secondary_data // get secondary_data.stack
646 and x0, x0, #~(THREAD_SIZE - 1)
647 msr sp_el0, x0 // save thread_info
649 b secondary_start_kernel
650 ENDPROC(__secondary_switched)
655 * x0 = SCTLR_EL1 value for turning on the MMU.
656 * x27 = *virtual* address to jump to upon completion
658 * Other registers depend on the function called upon completion.
660 * Checks if the selected granule size is supported by the CPU.
661 * If it isn't, park the CPU
663 .section ".idmap.text", "ax"
665 mrs x18, sctlr_el1 // preserve old SCTLR_EL1 value
666 mrs x1, ID_AA64MMFR0_EL1
667 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
668 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
669 b.ne __no_granule_support
670 msr ttbr0_el1, x25 // load TTBR0
671 msr ttbr1_el1, x26 // load TTBR1
676 * Invalidate the local I-cache so that any instructions fetched
677 * speculatively from the PoC are discarded, since they may have
678 * been dynamically patched at the PoU.
683 #ifdef CONFIG_RANDOMIZE_BASE
684 mov x19, x0 // preserve new SCTLR_EL1 value
688 * If we return here, we have a KASLR displacement in x23 which we need
689 * to take into account by discarding the current kernel mapping and
690 * creating a new one.
692 msr sctlr_el1, x18 // disable the MMU
694 bl __create_page_tables // recreate kernel mapping
696 msr sctlr_el1, x19 // re-enable the MMU
698 ic iallu // flush instructions fetched
699 dsb nsh // via old mapping
703 ENDPROC(__enable_mmu)
705 __no_granule_support:
707 b __no_granule_support
708 ENDPROC(__no_granule_support)
711 #ifdef CONFIG_RELOCATABLE
713 * Iterate over each entry in the relocation table, and apply the
714 * relocations in place.
716 ldr w8, =__dynsym_offset // offset to symbol table
717 ldr w9, =__rela_offset // offset to reloc table
718 ldr w10, =__rela_size // size of reloc table
720 mov_q x11, KIMAGE_VADDR // default virtual offset
721 add x11, x11, x23 // actual virtual offset
722 add x8, x8, x11 // __va(.dynsym)
723 add x9, x9, x11 // __va(.rela)
724 add x10, x9, x10 // __va(.rela) + sizeof(.rela)
728 ldp x11, x12, [x9], #24
730 cmp w12, #R_AARCH64_RELATIVE
732 add x13, x13, x23 // relocate
736 1: cmp w12, #R_AARCH64_ABS64
738 add x12, x12, x12, lsl #1 // symtab offset: 24x top word
739 add x12, x8, x12, lsr #(32 - 3) // ... shifted into bottom word
740 ldrsh w14, [x12, #6] // Elf64_Sym::st_shndx
741 ldr x15, [x12, #8] // Elf64_Sym::st_value
742 cmp w14, #-0xf // SHN_ABS (0xfff1) ?
743 add x14, x15, x23 // relocate
744 csel x15, x14, x15, ne
751 ldr x8, =__primary_switched
753 ENDPROC(__primary_switch)
756 ldr x8, =__secondary_switched
758 ENDPROC(__secondary_switch)