2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
26 #include <asm/assembler.h>
27 #include <asm/ptrace.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cache.h>
30 #include <asm/cputype.h>
31 #include <asm/memory.h>
32 #include <asm/thread_info.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
39 * swapper_pg_dir is the virtual address of the initial page table. We place
40 * the page tables 3 * PAGE_SIZE below KERNEL_RAM_VADDR. The idmap_pg_dir has
41 * 2 pages and is placed below swapper_pg_dir.
43 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
45 #if (KERNEL_RAM_VADDR & 0xfffff) != 0x80000
46 #error KERNEL_RAM_VADDR must start at 0xXXX80000
49 #define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
50 #define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
53 .equ swapper_pg_dir, KERNEL_RAM_VADDR - SWAPPER_DIR_SIZE
56 .equ idmap_pg_dir, swapper_pg_dir - IDMAP_DIR_SIZE
58 .macro pgtbl, ttb0, ttb1, phys
59 add \ttb1, \phys, #TEXT_OFFSET - SWAPPER_DIR_SIZE
60 sub \ttb0, \ttb1, #IDMAP_DIR_SIZE
63 #ifdef CONFIG_ARM64_64K_PAGES
64 #define BLOCK_SHIFT PAGE_SHIFT
65 #define BLOCK_SIZE PAGE_SIZE
67 #define BLOCK_SHIFT SECTION_SHIFT
68 #define BLOCK_SIZE SECTION_SIZE
71 #define KERNEL_START KERNEL_RAM_VADDR
72 #define KERNEL_END _end
75 * Initial memory map attributes.
78 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
79 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
81 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
82 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
85 #ifdef CONFIG_ARM64_64K_PAGES
86 #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
88 #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
92 * Kernel startup entry point.
93 * ---------------------------
95 * The requirements are:
96 * MMU = off, D-cache = off, I-cache = on or off,
97 * x0 = physical address to the FDT blob.
99 * This code is mostly position independent so you call this at
100 * __pa(PAGE_OFFSET + TEXT_OFFSET).
102 * Note that the callee-saved registers are used for storing variables
103 * that are useful before the MMU is enabled. The allocations are described
104 * in the entry routines.
109 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
114 * This add instruction has no meaningful effect except that
115 * its opcode forms the magic "MZ" signature required by UEFI.
120 b stext // branch to kernel start, magic
123 .quad TEXT_OFFSET // Image load offset from start of RAM
129 .byte 0x41 // Magic number, "ARM\x64"
134 .long pe_header - efi_head // Offset to the PE header.
145 .short 0xaa64 // AArch64
146 .short 2 // nr_sections
147 .long 0 // TimeDateStamp
148 .long 0 // PointerToSymbolTable
149 .long 1 // NumberOfSymbols
150 .short section_table - optional_header // SizeOfOptionalHeader
151 .short 0x206 // Characteristics.
152 // IMAGE_FILE_DEBUG_STRIPPED |
153 // IMAGE_FILE_EXECUTABLE_IMAGE |
154 // IMAGE_FILE_LINE_NUMS_STRIPPED
156 .short 0x20b // PE32+ format
157 .byte 0x02 // MajorLinkerVersion
158 .byte 0x14 // MinorLinkerVersion
159 .long _edata - stext // SizeOfCode
160 .long 0 // SizeOfInitializedData
161 .long 0 // SizeOfUninitializedData
162 .long efi_stub_entry - efi_head // AddressOfEntryPoint
163 .long stext - efi_head // BaseOfCode
167 .long 0x20 // SectionAlignment
168 .long 0x8 // FileAlignment
169 .short 0 // MajorOperatingSystemVersion
170 .short 0 // MinorOperatingSystemVersion
171 .short 0 // MajorImageVersion
172 .short 0 // MinorImageVersion
173 .short 0 // MajorSubsystemVersion
174 .short 0 // MinorSubsystemVersion
175 .long 0 // Win32VersionValue
177 .long _edata - efi_head // SizeOfImage
179 // Everything before the kernel image is considered part of the header
180 .long stext - efi_head // SizeOfHeaders
182 .short 0xa // Subsystem (EFI application)
183 .short 0 // DllCharacteristics
184 .quad 0 // SizeOfStackReserve
185 .quad 0 // SizeOfStackCommit
186 .quad 0 // SizeOfHeapReserve
187 .quad 0 // SizeOfHeapCommit
188 .long 0 // LoaderFlags
189 .long 0x6 // NumberOfRvaAndSizes
191 .quad 0 // ExportTable
192 .quad 0 // ImportTable
193 .quad 0 // ResourceTable
194 .quad 0 // ExceptionTable
195 .quad 0 // CertificationTable
196 .quad 0 // BaseRelocationTable
202 * The EFI application loader requires a relocation section
203 * because EFI applications must be relocatable. This is a
204 * dummy section as far as we are concerned.
208 .byte 0 // end of 0 padding of section name
211 .long 0 // SizeOfRawData
212 .long 0 // PointerToRawData
213 .long 0 // PointerToRelocations
214 .long 0 // PointerToLineNumbers
215 .short 0 // NumberOfRelocations
216 .short 0 // NumberOfLineNumbers
217 .long 0x42100040 // Characteristics (section flags)
223 .byte 0 // end of 0 padding of section name
224 .long _edata - stext // VirtualSize
225 .long stext - efi_head // VirtualAddress
226 .long _edata - stext // SizeOfRawData
227 .long stext - efi_head // PointerToRawData
229 .long 0 // PointerToRelocations (0 for executables)
230 .long 0 // PointerToLineNumbers (0 for executables)
231 .short 0 // NumberOfRelocations (0 for executables)
232 .short 0 // NumberOfLineNumbers (0 for executables)
233 .long 0xe0500020 // Characteristics (section flags)
238 mov x21, x0 // x21=FDT
239 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
240 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
241 bl set_cpu_boot_mode_flag
242 mrs x22, midr_el1 // x22=cpuid
244 bl lookup_processor_type
245 mov x23, x0 // x23=current cpu_table
246 cbz x23, __error_p // invalid processor (x23=0)?
248 bl __create_page_tables // x25=TTBR0, x26=TTBR1
250 * The following calls CPU specific code in a position independent
251 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
252 * cpu_info structure selected by lookup_processor_type above.
253 * On return, the CPU will be ready for the MMU to be turned on and
254 * the TCR will have been set.
256 ldr x27, __switch_data // address to jump to after
257 // MMU has been enabled
258 adr lr, __enable_mmu // return (PIC) address
259 ldr x12, [x23, #CPU_INFO_SETUP]
260 add x12, x12, x28 // __virt_to_phys
261 br x12 // initialise processor
265 * If we're fortunate enough to boot at EL2, ensure that the world is
266 * sane before dropping to EL1.
268 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
269 * booted in EL1 or EL2 respectively.
273 cmp x0, #PSR_MODE_EL2t
274 ccmp x0, #PSR_MODE_EL2h, #0x4, ne
277 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
278 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
282 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
283 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
285 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
289 /* Hyp configuration. */
290 2: mov x0, #(1 << 31) // 64-bit EL1
293 /* Generic timers. */
295 orr x0, x0, #3 // Enable EL1 physical timers
297 msr cntvoff_el2, xzr // Clear virtual offset
299 /* Populate ID registers. */
306 mov x0, #0x0800 // Set/clear RES{1,0} bits
307 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
308 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
311 /* Coprocessor traps. */
313 msr cptr_el2, x0 // Disable copro. traps to EL2
316 msr hstr_el2, xzr // Disable CP15 traps to EL2
319 /* Stage-2 translation */
322 /* Hypervisor stub */
323 adr x0, __hyp_stub_vectors
327 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
331 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
336 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
337 * in x20. See arch/arm64/include/asm/virt.h for more info.
339 ENTRY(set_cpu_boot_mode_flag)
340 ldr x1, =__boot_cpu_mode // Compute __boot_cpu_mode
342 cmp w20, #BOOT_CPU_MODE_EL2
345 1: str w20, [x1] // This CPU has booted in EL1
347 dc ivac, x1 // Invalidate potentially stale cache line
349 ENDPROC(set_cpu_boot_mode_flag)
352 * We need to find out the CPU boot mode long after boot, so we need to
353 * store it in a writable variable.
355 * This is not in .bss, because we set it sufficiently early that the boot-time
356 * zeroing of .bss would clobber it.
358 .pushsection .data..cacheline_aligned
359 ENTRY(__boot_cpu_mode)
360 .align L1_CACHE_SHIFT
361 .long BOOT_CPU_MODE_EL2
372 .quad secondary_holding_pen_release
375 * This provides a "holding pen" for platforms to hold all secondary
376 * cores are held until we're ready for them to initialise.
378 ENTRY(secondary_holding_pen)
379 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
380 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
381 bl set_cpu_boot_mode_flag
383 ldr x1, =MPIDR_HWID_BITMASK
391 b.eq secondary_startup
394 ENDPROC(secondary_holding_pen)
397 * Secondary entry point that jumps straight into the kernel. Only to
398 * be used where CPUs are brought online dynamically by the kernel.
400 ENTRY(secondary_entry)
401 bl el2_setup // Drop to EL1
402 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
403 bl set_cpu_boot_mode_flag
405 ENDPROC(secondary_entry)
407 ENTRY(secondary_startup)
409 * Common entry point for secondary CPUs.
411 mrs x22, midr_el1 // x22=cpuid
413 bl lookup_processor_type
414 mov x23, x0 // x23=current cpu_table
415 cbz x23, __error_p // invalid processor (x23=0)?
417 pgtbl x25, x26, x24 // x25=TTBR0, x26=TTBR1
418 ldr x12, [x23, #CPU_INFO_SETUP]
419 add x12, x12, x28 // __virt_to_phys
420 blr x12 // initialise processor
422 ldr x21, =secondary_data
423 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
425 ENDPROC(secondary_startup)
427 ENTRY(__secondary_switched)
428 ldr x0, [x21] // get secondary_data.stack
431 b secondary_start_kernel
432 ENDPROC(__secondary_switched)
433 #endif /* CONFIG_SMP */
436 * Setup common bits before finally enabling the MMU. Essentially this is just
437 * loading the page table pointer and vector base registers.
439 * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
445 msr ttbr0_el1, x25 // load TTBR0
446 msr ttbr1_el1, x26 // load TTBR1
449 ENDPROC(__enable_mmu)
452 * Enable the MMU. This completely changes the structure of the visible memory
453 * space. You will not be able to trace execution through this.
455 * x0 = system control register
456 * x27 = *virtual* address to jump to upon completion
458 * other registers depend on the function called upon completion
465 ENDPROC(__turn_mmu_on)
468 * Calculate the start of physical memory.
473 sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
474 add x24, x2, x28 // x24 = PHYS_OFFSET
476 ENDPROC(__calc_phys_offset)
483 * Macro to populate the PGD for the corresponding block entry in the next
484 * level (tbl) for the given virtual address.
486 * Preserves: pgd, tbl, virt
487 * Corrupts: tmp1, tmp2
489 .macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
490 lsr \tmp1, \virt, #PGDIR_SHIFT
491 and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
492 orr \tmp2, \tbl, #3 // PGD entry table type
493 str \tmp2, [\pgd, \tmp1, lsl #3]
497 * Macro to populate block entries in the page table for the start..end
498 * virtual range (inclusive).
500 * Preserves: tbl, flags
501 * Corrupts: phys, start, end, pstate
503 .macro create_block_map, tbl, flags, phys, start, end
504 lsr \phys, \phys, #BLOCK_SHIFT
505 lsr \start, \start, #BLOCK_SHIFT
506 and \start, \start, #PTRS_PER_PTE - 1 // table index
507 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
508 lsr \end, \end, #BLOCK_SHIFT
509 and \end, \end, #PTRS_PER_PTE - 1 // table end index
510 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
511 add \start, \start, #1 // next entry
512 add \phys, \phys, #BLOCK_SIZE // next block
518 * Setup the initial page tables. We only setup the barest amount which is
519 * required to get the kernel running. The following sections are required:
520 * - identity mapping to enable the MMU (low address, TTBR0)
521 * - first few MB of the kernel linear mapping to jump to once the MMU has
522 * been enabled, including the FDT blob (TTBR1)
523 * - pgd entry for fixed mappings (TTBR1)
525 __create_page_tables:
526 pgtbl x25, x26, x24 // idmap_pg_dir and swapper_pg_dir addresses
530 * Invalidate the idmap and swapper page tables to avoid potential
531 * dirty cache lines being evicted.
534 add x1, x26, #SWAPPER_DIR_SIZE
535 bl __inval_cache_range
538 * Clear the idmap and swapper page tables.
541 add x6, x26, #SWAPPER_DIR_SIZE
542 1: stp xzr, xzr, [x0], #16
543 stp xzr, xzr, [x0], #16
544 stp xzr, xzr, [x0], #16
545 stp xzr, xzr, [x0], #16
552 * Create the identity mapping.
554 add x0, x25, #PAGE_SIZE // section table address
555 ldr x3, =KERNEL_START
556 add x3, x3, x28 // __pa(KERNEL_START)
557 create_pgd_entry x25, x0, x3, x5, x6
559 mov x5, x3 // __pa(KERNEL_START)
560 add x6, x6, x28 // __pa(KERNEL_END)
561 create_block_map x0, x7, x3, x5, x6
564 * Map the kernel image (starting with PHYS_OFFSET).
566 add x0, x26, #PAGE_SIZE // section table address
568 create_pgd_entry x26, x0, x5, x3, x6
570 mov x3, x24 // phys offset
571 create_block_map x0, x7, x3, x5, x6
574 * Map the FDT blob (maximum 2MB; must be within 512MB of
577 mov x3, x21 // FDT phys address
578 and x3, x3, #~((1 << 21) - 1) // 2MB aligned
580 sub x5, x3, x24 // subtract PHYS_OFFSET
581 tst x5, #~((1 << 29) - 1) // within 512MB?
582 csel x21, xzr, x21, ne // zero the FDT pointer
584 add x5, x5, x6 // __va(FDT blob)
585 add x6, x5, #1 << 21 // 2MB for the FDT blob
586 sub x6, x6, #1 // inclusive range
587 create_block_map x0, x7, x3, x5, x6
590 * Create the pgd entry for the fixed mappings.
592 ldr x5, =FIXADDR_TOP // Fixed mapping virtual address
593 add x0, x26, #2 * PAGE_SIZE // section table address
594 create_pgd_entry x26, x0, x5, x6, x7
597 * Since the page tables have been populated with non-cacheable
598 * accesses (MMU disabled), invalidate the idmap and swapper page
599 * tables again to remove any speculatively loaded cache lines.
602 add x1, x26, #SWAPPER_DIR_SIZE
603 bl __inval_cache_range
607 ENDPROC(__create_page_tables)
611 .type __switch_data, %object
613 .quad __mmap_switched
614 .quad __bss_start // x6
616 .quad processor_id // x4
617 .quad __fdt_pointer // x5
618 .quad memstart_addr // x6
619 .quad init_thread_union + THREAD_START_SP // sp
622 * The following fragment of code is executed with the MMU on in MMU mode, and
623 * uses absolute addresses; this is not position independent.
626 adr x3, __switch_data + 8
628 ldp x6, x7, [x3], #16
631 str xzr, [x6], #8 // Clear BSS
634 ldp x4, x5, [x3], #16
638 str x22, [x4] // Save processor ID
639 str x21, [x5] // Save FDT pointer
640 str x24, [x6] // Save PHYS_OFFSET
643 ENDPROC(__mmap_switched)
646 * Exception handling. Something went wrong and we can't proceed. We ought to
647 * tell the user, but since we don't have any guarantee that we're even
648 * running on the right architecture, we do virtually nothing.
659 * This function gets the processor ID in w0 and searches the cpu_table[] for
660 * a match. It returns a pointer to the struct cpu_info it found. The
661 * cpu_table[] must end with an empty (all zeros) structure.
663 * This routine can be called via C code and it needs to work with the MMU
664 * both disabled and enabled (the offset is calculated automatically).
666 ENTRY(lookup_processor_type)
667 adr x1, __lookup_processor_type_data
669 sub x1, x1, x2 // get offset between VA and PA
670 add x3, x3, x1 // convert VA to PA
672 ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
673 cbz w5, 2f // end of list?
677 add x3, x3, #CPU_INFO_SZ
680 mov x3, #0 // unknown processor
684 ENDPROC(lookup_processor_type)
687 .type __lookup_processor_type_data, %object
688 __lookup_processor_type_data:
691 .size __lookup_processor_type_data, . - __lookup_processor_type_data
694 * Determine validity of the x21 FDT pointer.
695 * The dtb must be 8-byte aligned and live in the first 512M of memory.