2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
29 #include <asm/ptrace.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/cache.h>
32 #include <asm/cputype.h>
34 #include <asm/kernel-pgtable.h>
35 #include <asm/memory.h>
36 #include <asm/pgtable-hwdef.h>
37 #include <asm/pgtable.h>
39 #include <asm/sysreg.h>
40 #include <asm/thread_info.h>
43 #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
45 #if (TEXT_OFFSET & 0xfff) != 0
46 #error TEXT_OFFSET must be at least 4KB aligned
47 #elif (PAGE_OFFSET & 0x1fffff) != 0
48 #error PAGE_OFFSET must be at least 2MB aligned
49 #elif TEXT_OFFSET > 0x1fffff
50 #error TEXT_OFFSET must be less than 2MB
54 * Kernel startup entry point.
55 * ---------------------------
57 * The requirements are:
58 * MMU = off, D-cache = off, I-cache = on or off,
59 * x0 = physical address to the FDT blob.
61 * This code is mostly position independent so you call this at
62 * __pa(PAGE_OFFSET + TEXT_OFFSET).
64 * Note that the callee-saved registers are used for storing variables
65 * that are useful before the MMU is enabled. The allocations are described
66 * in the entry routines.
71 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
75 * This add instruction has no meaningful effect except that
76 * its opcode forms the magic "MZ" signature required by UEFI.
81 b stext // branch to kernel start, magic
84 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian
85 le64sym _kernel_size_le // Effective size of kernel image, little-endian
86 le64sym _kernel_flags_le // Informative flags, little-endian
90 .byte 0x41 // Magic number, "ARM\x64"
95 .long pe_header - _head // Offset to the PE header.
106 .short 0xaa64 // AArch64
107 .short 2 // nr_sections
108 .long 0 // TimeDateStamp
109 .long 0 // PointerToSymbolTable
110 .long 1 // NumberOfSymbols
111 .short section_table - optional_header // SizeOfOptionalHeader
112 .short 0x206 // Characteristics.
113 // IMAGE_FILE_DEBUG_STRIPPED |
114 // IMAGE_FILE_EXECUTABLE_IMAGE |
115 // IMAGE_FILE_LINE_NUMS_STRIPPED
117 .short 0x20b // PE32+ format
118 .byte 0x02 // MajorLinkerVersion
119 .byte 0x14 // MinorLinkerVersion
120 .long _end - efi_header_end // SizeOfCode
121 .long 0 // SizeOfInitializedData
122 .long 0 // SizeOfUninitializedData
123 .long __efistub_entry - _head // AddressOfEntryPoint
124 .long efi_header_end - _head // BaseOfCode
128 .long 0x1000 // SectionAlignment
129 .long PECOFF_FILE_ALIGNMENT // FileAlignment
130 .short 0 // MajorOperatingSystemVersion
131 .short 0 // MinorOperatingSystemVersion
132 .short 0 // MajorImageVersion
133 .short 0 // MinorImageVersion
134 .short 0 // MajorSubsystemVersion
135 .short 0 // MinorSubsystemVersion
136 .long 0 // Win32VersionValue
138 .long _end - _head // SizeOfImage
140 // Everything before the kernel image is considered part of the header
141 .long efi_header_end - _head // SizeOfHeaders
143 .short 0xa // Subsystem (EFI application)
144 .short 0 // DllCharacteristics
145 .quad 0 // SizeOfStackReserve
146 .quad 0 // SizeOfStackCommit
147 .quad 0 // SizeOfHeapReserve
148 .quad 0 // SizeOfHeapCommit
149 .long 0 // LoaderFlags
150 .long 0x6 // NumberOfRvaAndSizes
152 .quad 0 // ExportTable
153 .quad 0 // ImportTable
154 .quad 0 // ResourceTable
155 .quad 0 // ExceptionTable
156 .quad 0 // CertificationTable
157 .quad 0 // BaseRelocationTable
163 * The EFI application loader requires a relocation section
164 * because EFI applications must be relocatable. This is a
165 * dummy section as far as we are concerned.
169 .byte 0 // end of 0 padding of section name
172 .long 0 // SizeOfRawData
173 .long 0 // PointerToRawData
174 .long 0 // PointerToRelocations
175 .long 0 // PointerToLineNumbers
176 .short 0 // NumberOfRelocations
177 .short 0 // NumberOfLineNumbers
178 .long 0x42100040 // Characteristics (section flags)
184 .byte 0 // end of 0 padding of section name
185 .long _end - efi_header_end // VirtualSize
186 .long efi_header_end - _head // VirtualAddress
187 .long _edata - efi_header_end // SizeOfRawData
188 .long efi_header_end - _head // PointerToRawData
190 .long 0 // PointerToRelocations (0 for executables)
191 .long 0 // PointerToLineNumbers (0 for executables)
192 .short 0 // NumberOfRelocations (0 for executables)
193 .short 0 // NumberOfLineNumbers (0 for executables)
194 .long 0xe0500020 // Characteristics (section flags)
197 * EFI will load .text onwards at the 4k section alignment
198 * described in the PE/COFF header. To ensure that instruction
199 * sequences using an adrp and a :lo12: immediate will function
200 * correctly at this alignment, we must ensure that .text is
201 * placed at a 4k boundary in the Image to begin with.
210 bl preserve_boot_args
211 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
212 adrp x24, __PHYS_OFFSET
213 and x23, x24, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
214 bl set_cpu_boot_mode_flag
215 bl __create_page_tables // x25=TTBR0, x26=TTBR1
217 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
219 * On return, the CPU will be ready for the MMU to be turned on and
220 * the TCR will have been set.
222 bl __cpu_setup // initialise processor
223 adr_l x27, __primary_switch // address to jump to after
224 // MMU has been enabled
229 * Preserve the arguments passed by the bootloader in x0 .. x3
232 mov x21, x0 // x21=FDT
234 adr_l x0, boot_args // record the contents of
235 stp x21, x1, [x0] // x0 .. x3 at kernel entry
236 stp x2, x3, [x0, #16]
238 dmb sy // needed before dc ivac with
241 add x1, x0, #0x20 // 4 x 8 bytes
242 b __inval_cache_range // tail call
243 ENDPROC(preserve_boot_args)
246 * Macro to create a table entry to the next page.
248 * tbl: page table address
249 * virt: virtual address
250 * shift: #imm page table shift
251 * ptrs: #imm pointers per table page
254 * Corrupts: tmp1, tmp2
255 * Returns: tbl -> next level table page address
257 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
258 lsr \tmp1, \virt, #\shift
259 and \tmp1, \tmp1, #\ptrs - 1 // table index
260 add \tmp2, \tbl, #PAGE_SIZE
261 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
262 str \tmp2, [\tbl, \tmp1, lsl #3]
263 add \tbl, \tbl, #PAGE_SIZE // next level table page
267 * Macro to populate the PGD (and possibily PUD) for the corresponding
268 * block entry in the next level (tbl) for the given virtual address.
270 * Preserves: tbl, next, virt
271 * Corrupts: tmp1, tmp2
273 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
274 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
275 #if SWAPPER_PGTABLE_LEVELS > 3
276 create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
278 #if SWAPPER_PGTABLE_LEVELS > 2
279 create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
284 * Macro to populate block entries in the page table for the start..end
285 * virtual range (inclusive).
287 * Preserves: tbl, flags
288 * Corrupts: phys, start, end, pstate
290 .macro create_block_map, tbl, flags, phys, start, end
291 lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT
292 lsr \start, \start, #SWAPPER_BLOCK_SHIFT
293 and \start, \start, #PTRS_PER_PTE - 1 // table index
294 orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry
295 lsr \end, \end, #SWAPPER_BLOCK_SHIFT
296 and \end, \end, #PTRS_PER_PTE - 1 // table end index
297 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
298 add \start, \start, #1 // next entry
299 add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block
305 * Setup the initial page tables. We only setup the barest amount which is
306 * required to get the kernel running. The following sections are required:
307 * - identity mapping to enable the MMU (low address, TTBR0)
308 * - first few MB of the kernel linear mapping to jump to once the MMU has
311 __create_page_tables:
312 adrp x25, idmap_pg_dir
313 adrp x26, swapper_pg_dir
317 * Invalidate the idmap and swapper page tables to avoid potential
318 * dirty cache lines being evicted.
321 add x1, x26, #SWAPPER_DIR_SIZE
322 bl __inval_cache_range
325 * Clear the idmap and swapper page tables.
328 add x6, x26, #SWAPPER_DIR_SIZE
329 1: stp xzr, xzr, [x0], #16
330 stp xzr, xzr, [x0], #16
331 stp xzr, xzr, [x0], #16
332 stp xzr, xzr, [x0], #16
336 mov x7, SWAPPER_MM_MMUFLAGS
339 * Create the identity mapping.
341 mov x0, x25 // idmap_pg_dir
342 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
344 #ifndef CONFIG_ARM64_VA_BITS_48
345 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
346 #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT))
349 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be
350 * created that covers system RAM if that is located sufficiently high
351 * in the physical address space. So for the ID map, use an extended
352 * virtual range in that case, by configuring an additional translation
354 * First, we have to verify our assumption that the current value of
355 * VA_BITS was chosen such that all translation levels are fully
356 * utilised, and that lowering T0SZ will always result in an additional
357 * translation level to be configured.
359 #if VA_BITS != EXTRA_SHIFT
360 #error "Mismatch between VA_BITS and page size/number of translation levels"
364 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
365 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
366 * this number conveniently equals the number of leading zeroes in
367 * the physical address of __idmap_text_end.
369 adrp x5, __idmap_text_end
371 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
372 b.ge 1f // .. then skip additional level
377 dc ivac, x6 // Invalidate potentially stale cache line
379 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
383 create_pgd_entry x0, x3, x5, x6
384 mov x5, x3 // __pa(__idmap_text_start)
385 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
386 create_block_map x0, x7, x3, x5, x6
389 * Map the kernel image (starting with PHYS_OFFSET).
391 mov x0, x26 // swapper_pg_dir
392 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text)
393 add x5, x5, x23 // add KASLR displacement
394 create_pgd_entry x0, x5, x3, x6
395 adrp x6, _end // runtime __pa(_end)
396 adrp x3, _text // runtime __pa(_text)
397 sub x6, x6, x3 // _end - _text
398 add x6, x6, x5 // runtime __va(_end)
399 create_block_map x0, x7, x3, x5, x6
402 * Since the page tables have been populated with non-cacheable
403 * accesses (MMU disabled), invalidate the idmap and swapper page
404 * tables again to remove any speculatively loaded cache lines.
407 add x1, x26, #SWAPPER_DIR_SIZE
409 bl __inval_cache_range
412 ENDPROC(__create_page_tables)
416 * The following fragment of code is executed with the MMU enabled.
418 .set initial_sp, init_thread_union + THREAD_START_SP
420 mov x28, lr // preserve LR
421 adr_l x8, vectors // load VBAR_EL1 with virtual
422 msr vbar_el1, x8 // vector table address
426 adr_l x0, __bss_start
431 dsb ishst // Make zero page visible to PTW
433 adr_l sp, initial_sp, x4
435 and x4, x4, #~(THREAD_SIZE - 1)
436 msr sp_el0, x4 // Save thread_info
437 str_l x21, __fdt_pointer, x5 // Save FDT pointer
439 ldr_l x4, kimage_vaddr // Save the offset between
440 sub x4, x4, x24 // the kernel virtual and
441 str_l x4, kimage_voffset, x5 // physical mappings
447 #ifdef CONFIG_RANDOMIZE_BASE
448 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized?
450 mov x0, x21 // pass FDT address in x0
451 mov x1, x23 // pass modulo offset in x1
452 bl kaslr_early_init // parse FDT for KASLR options
453 cbz x0, 0f // KASLR disabled? just proceed
454 orr x23, x23, x0 // record KASLR offset
455 ret x28 // we must enable KASLR, return
460 ENDPROC(__primary_switched)
463 * end early head section, begin head code that is also used for
464 * hotplug and needs to have the same protections as the text region
466 .section ".text","ax"
469 .quad _text - TEXT_OFFSET
472 * If we're fortunate enough to boot at EL2, ensure that the world is
473 * sane before dropping to EL1.
475 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
476 * booted in EL1 or EL2 respectively.
480 cmp x0, #CurrentEL_EL2
483 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
484 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
488 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
489 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
491 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
495 /* Hyp configuration. */
496 2: mov x0, #(1 << 31) // 64-bit EL1
499 /* Generic timers. */
501 orr x0, x0, #3 // Enable EL1 physical timers
503 msr cntvoff_el2, xzr // Clear virtual offset
505 #ifdef CONFIG_ARM_GIC_V3
506 /* GICv3 system register access */
507 mrs x0, id_aa64pfr0_el1
512 mrs_s x0, ICC_SRE_EL2
513 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
514 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
515 msr_s ICC_SRE_EL2, x0
516 isb // Make sure SRE is now set
517 mrs_s x0, ICC_SRE_EL2 // Read SRE back,
518 tbz x0, #0, 3f // and check that it sticks
519 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
524 /* Populate ID registers. */
531 mov x0, #0x0800 // Set/clear RES{1,0} bits
532 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
533 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
536 /* Coprocessor traps. */
538 msr cptr_el2, x0 // Disable copro. traps to EL2
541 msr hstr_el2, xzr // Disable CP15 traps to EL2
545 mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
548 b.lt 4f // Skip if no PMU present
549 mrs x0, pmcr_el0 // Disable debug access traps
550 ubfx x0, x0, #11, #5 // to EL2 and allow access to
552 csel x0, xzr, x0, lt // all PMU counters from EL1
553 msr mdcr_el2, x0 // (if they exist)
555 /* Stage-2 translation */
558 /* Hypervisor stub */
559 adrp x0, __hyp_stub_vectors
560 add x0, x0, #:lo12:__hyp_stub_vectors
564 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
568 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
573 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
574 * in x20. See arch/arm64/include/asm/virt.h for more info.
576 set_cpu_boot_mode_flag:
577 adr_l x1, __boot_cpu_mode
578 cmp w20, #BOOT_CPU_MODE_EL2
581 1: str w20, [x1] // This CPU has booted in EL1
583 dc ivac, x1 // Invalidate potentially stale cache line
585 ENDPROC(set_cpu_boot_mode_flag)
588 * We need to find out the CPU boot mode long after boot, so we need to
589 * store it in a writable variable.
591 * This is not in .bss, because we set it sufficiently early that the boot-time
592 * zeroing of .bss would clobber it.
594 .pushsection .data..cacheline_aligned
595 .align L1_CACHE_SHIFT
596 ENTRY(__boot_cpu_mode)
597 .long BOOT_CPU_MODE_EL2
598 .long BOOT_CPU_MODE_EL1
602 * This provides a "holding pen" for platforms to hold all secondary
603 * cores are held until we're ready for them to initialise.
605 ENTRY(secondary_holding_pen)
606 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
607 bl set_cpu_boot_mode_flag
609 mov_q x1, MPIDR_HWID_BITMASK
611 adr_l x3, secondary_holding_pen_release
614 b.eq secondary_startup
617 ENDPROC(secondary_holding_pen)
620 * Secondary entry point that jumps straight into the kernel. Only to
621 * be used where CPUs are brought online dynamically by the kernel.
623 ENTRY(secondary_entry)
624 bl el2_setup // Drop to EL1
625 bl set_cpu_boot_mode_flag
627 ENDPROC(secondary_entry)
631 * Common entry point for secondary CPUs.
633 adrp x25, idmap_pg_dir
634 adrp x26, swapper_pg_dir
635 bl __cpu_setup // initialise processor
637 adr_l x27, __secondary_switch // address to jump to after enabling the MMU
639 ENDPROC(secondary_startup)
641 __secondary_switched:
646 ldr_l x0, secondary_data // get secondary_data.stack
648 and x0, x0, #~(THREAD_SIZE - 1)
649 msr sp_el0, x0 // save thread_info
651 b secondary_start_kernel
652 ENDPROC(__secondary_switched)
657 * x0 = SCTLR_EL1 value for turning on the MMU.
658 * x27 = *virtual* address to jump to upon completion
660 * Other registers depend on the function called upon completion.
662 * Checks if the selected granule size is supported by the CPU.
663 * If it isn't, park the CPU
665 .section ".idmap.text", "ax"
667 mrs x18, sctlr_el1 // preserve old SCTLR_EL1 value
668 mrs x1, ID_AA64MMFR0_EL1
669 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
670 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
671 b.ne __no_granule_support
672 msr ttbr0_el1, x25 // load TTBR0
673 msr ttbr1_el1, x26 // load TTBR1
678 * Invalidate the local I-cache so that any instructions fetched
679 * speculatively from the PoC are discarded, since they may have
680 * been dynamically patched at the PoU.
685 #ifdef CONFIG_RANDOMIZE_BASE
686 mov x19, x0 // preserve new SCTLR_EL1 value
690 * If we return here, we have a KASLR displacement in x23 which we need
691 * to take into account by discarding the current kernel mapping and
692 * creating a new one.
694 msr sctlr_el1, x18 // disable the MMU
696 bl __create_page_tables // recreate kernel mapping
698 msr sctlr_el1, x19 // re-enable the MMU
700 ic iallu // flush instructions fetched
701 dsb nsh // via old mapping
705 ENDPROC(__enable_mmu)
707 __no_granule_support:
709 b __no_granule_support
710 ENDPROC(__no_granule_support)
713 #ifdef CONFIG_RELOCATABLE
715 * Iterate over each entry in the relocation table, and apply the
716 * relocations in place.
718 ldr w9, =__rela_offset // offset to reloc table
719 ldr w10, =__rela_size // size of reloc table
721 mov_q x11, KIMAGE_VADDR // default virtual offset
722 add x11, x11, x23 // actual virtual offset
723 add x9, x9, x11 // __va(.rela)
724 add x10, x9, x10 // __va(.rela) + sizeof(.rela)
728 ldp x11, x12, [x9], #24
730 cmp w12, #R_AARCH64_RELATIVE
732 add x13, x13, x23 // relocate
738 ldr x8, =__primary_switched
740 ENDPROC(__primary_switch)
743 ldr x8, =__secondary_switched
745 ENDPROC(__secondary_switch)