2 * Based on arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/export.h>
21 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/ioport.h>
24 #include <linux/delay.h>
25 #include <linux/utsname.h>
26 #include <linux/initrd.h>
27 #include <linux/console.h>
28 #include <linux/cache.h>
29 #include <linux/bootmem.h>
30 #include <linux/seq_file.h>
31 #include <linux/screen_info.h>
32 #include <linux/init.h>
33 #include <linux/kexec.h>
34 #include <linux/crash_dump.h>
35 #include <linux/root_dev.h>
36 #include <linux/clk-provider.h>
37 #include <linux/cpu.h>
38 #include <linux/interrupt.h>
39 #include <linux/smp.h>
41 #include <linux/proc_fs.h>
42 #include <linux/memblock.h>
43 #include <linux/of_iommu.h>
44 #include <linux/of_fdt.h>
45 #include <linux/of_platform.h>
46 #include <linux/efi.h>
47 #include <linux/personality.h>
49 #include <asm/fixmap.h>
51 #include <asm/cputype.h>
53 #include <asm/cputable.h>
54 #include <asm/cpufeature.h>
55 #include <asm/cpu_ops.h>
56 #include <asm/sections.h>
57 #include <asm/setup.h>
58 #include <asm/smp_plat.h>
59 #include <asm/cacheflush.h>
60 #include <asm/tlbflush.h>
61 #include <asm/traps.h>
62 #include <asm/memblock.h>
66 unsigned int processor_id;
67 EXPORT_SYMBOL(processor_id);
69 unsigned long elf_hwcap __read_mostly;
70 EXPORT_SYMBOL_GPL(elf_hwcap);
73 #define COMPAT_ELF_HWCAP_DEFAULT \
74 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
75 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
76 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
77 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
78 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
80 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
81 unsigned int compat_elf_hwcap2 __read_mostly;
84 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
86 static const char *cpu_name;
87 phys_addr_t __fdt_pointer __initdata;
90 * Standard memory resources
92 static struct resource mem_res[] = {
94 .name = "Kernel code",
97 .flags = IORESOURCE_MEM
100 .name = "Kernel data",
103 .flags = IORESOURCE_MEM
107 #define kernel_code mem_res[0]
108 #define kernel_data mem_res[1]
110 void __init early_print(const char *str, ...)
116 vsnprintf(buf, sizeof(buf), str, ap);
122 void __init smp_setup_processor_id(void)
124 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
125 cpu_logical_map(0) = mpidr;
128 * clear __my_cpu_offset on boot CPU to avoid hang caused by
129 * using percpu variable early, for example, lockdep will
130 * access percpu variable inside lock_release
132 set_my_cpu_offset(0);
133 pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr);
136 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
138 return phys_id == cpu_logical_map(cpu);
141 struct mpidr_hash mpidr_hash;
144 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
145 * level in order to build a linear index from an
146 * MPIDR value. Resulting algorithm is a collision
147 * free hash carried out through shifting and ORing
149 static void __init smp_build_mpidr_hash(void)
151 u32 i, affinity, fs[4], bits[4], ls;
154 * Pre-scan the list of MPIDRS and filter out bits that do
155 * not contribute to affinity levels, ie they never toggle.
157 for_each_possible_cpu(i)
158 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
159 pr_debug("mask of set bits %#llx\n", mask);
161 * Find and stash the last and first bit set at all affinity levels to
162 * check how many bits are required to represent them.
164 for (i = 0; i < 4; i++) {
165 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
167 * Find the MSB bit and LSB bits position
168 * to determine how many bits are required
169 * to express the affinity level.
172 fs[i] = affinity ? ffs(affinity) - 1 : 0;
173 bits[i] = ls - fs[i];
176 * An index can be created from the MPIDR_EL1 by isolating the
177 * significant bits at each affinity level and by shifting
178 * them in order to compress the 32 bits values space to a
179 * compressed set of values. This is equivalent to hashing
180 * the MPIDR_EL1 through shifting and ORing. It is a collision free
181 * hash though not minimal since some levels might contain a number
182 * of CPUs that is not an exact power of 2 and their bit
183 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
185 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
186 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
187 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
189 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
190 fs[3] - (bits[2] + bits[1] + bits[0]);
191 mpidr_hash.mask = mask;
192 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
193 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
194 mpidr_hash.shift_aff[0],
195 mpidr_hash.shift_aff[1],
196 mpidr_hash.shift_aff[2],
197 mpidr_hash.shift_aff[3],
201 * 4x is an arbitrary value used to warn on a hash table much bigger
202 * than expected on most systems.
204 if (mpidr_hash_size() > 4 * num_possible_cpus())
205 pr_warn("Large number of MPIDR hash buckets detected\n");
206 __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
210 static void __init setup_processor(void)
212 struct cpu_info *cpu_info;
217 cpu_info = lookup_processor_type(read_cpuid_id());
219 printk("CPU configuration botched (ID %08x), unable to continue.\n",
224 cpu_name = cpu_info->cpu_name;
226 printk("CPU: %s [%08x] revision %d\n",
227 cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
229 sprintf(init_utsname()->machine, ELF_PLATFORM);
232 cpuinfo_store_boot_cpu();
235 * Check for sane CTR_EL0.CWG value.
237 cwg = cache_type_cwg();
238 cls = cache_line_size();
240 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
242 if (L1_CACHE_BYTES < cls)
243 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
244 L1_CACHE_BYTES, cls);
247 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
248 * The blocks we test below represent incremental functionality
249 * for non-negative values. Negative values are reserved.
251 features = read_cpuid(ID_AA64ISAR0_EL1);
252 block = (features >> 4) & 0xf;
253 if (!(block & 0x8)) {
257 elf_hwcap |= HWCAP_PMULL;
259 elf_hwcap |= HWCAP_AES;
265 block = (features >> 8) & 0xf;
266 if (block && !(block & 0x8))
267 elf_hwcap |= HWCAP_SHA1;
269 block = (features >> 12) & 0xf;
270 if (block && !(block & 0x8))
271 elf_hwcap |= HWCAP_SHA2;
273 block = (features >> 16) & 0xf;
274 if (block && !(block & 0x8))
275 elf_hwcap |= HWCAP_CRC32;
279 * ID_ISAR5_EL1 carries similar information as above, but pertaining to
280 * the Aarch32 32-bit execution state.
282 features = read_cpuid(ID_ISAR5_EL1);
283 block = (features >> 4) & 0xf;
284 if (!(block & 0x8)) {
288 compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
290 compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
296 block = (features >> 8) & 0xf;
297 if (block && !(block & 0x8))
298 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
300 block = (features >> 12) & 0xf;
301 if (block && !(block & 0x8))
302 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
304 block = (features >> 16) & 0xf;
305 if (block && !(block & 0x8))
306 compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
310 static void __init setup_machine_fdt(phys_addr_t dt_phys)
312 if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
314 "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
315 "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
316 "\nPlease check your bootloader.\n",
317 dt_phys, phys_to_virt(dt_phys));
323 dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
326 static void __init request_standard_resources(void)
328 struct memblock_region *region;
329 struct resource *res;
331 kernel_code.start = virt_to_phys(_text);
332 kernel_code.end = virt_to_phys(_etext - 1);
333 kernel_data.start = virt_to_phys(_sdata);
334 kernel_data.end = virt_to_phys(_end - 1);
336 for_each_memblock(memory, region) {
337 res = alloc_bootmem_low(sizeof(*res));
338 res->name = "System RAM";
339 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
340 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
341 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
343 request_resource(&iomem_resource, res);
345 if (kernel_code.start >= res->start &&
346 kernel_code.end <= res->end)
347 request_resource(res, &kernel_code);
348 if (kernel_data.start >= res->start &&
349 kernel_data.end <= res->end)
350 request_resource(res, &kernel_data);
354 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
356 void __init setup_arch(char **cmdline_p)
360 setup_machine_fdt(__fdt_pointer);
362 init_mm.start_code = (unsigned long) _text;
363 init_mm.end_code = (unsigned long) _etext;
364 init_mm.end_data = (unsigned long) _edata;
365 init_mm.brk = (unsigned long) _end;
367 *cmdline_p = boot_command_line;
370 early_ioremap_init();
375 * Unmask asynchronous aborts after bringing up possible earlycon.
376 * (Report possible System Errors once we can report this occurred)
378 local_async_enable();
381 arm64_memblock_init();
384 request_standard_resources();
386 early_ioremap_reset();
388 unflatten_device_tree();
392 cpu_read_bootcpu_ops();
395 smp_build_mpidr_hash();
399 #if defined(CONFIG_VGA_CONSOLE)
400 conswitchp = &vga_con;
401 #elif defined(CONFIG_DUMMY_CONSOLE)
402 conswitchp = &dummy_con;
407 static int __init arm64_device_init(void)
410 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
413 arch_initcall_sync(arm64_device_init);
415 static int __init topology_init(void)
419 for_each_possible_cpu(i) {
420 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
421 cpu->hotpluggable = 1;
422 register_cpu(cpu, i);
427 subsys_initcall(topology_init);
429 static const char *hwcap_str[] = {
442 static const char *compat_hwcap_str[] = {
467 static const char *compat_hwcap2_str[] = {
475 #endif /* CONFIG_COMPAT */
477 static int c_show(struct seq_file *m, void *v)
481 for_each_online_cpu(i) {
482 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
483 u32 midr = cpuinfo->reg_midr;
486 * glibc reads /proc/cpuinfo to determine the number of
487 * online processors, looking for lines beginning with
488 * "processor". Give glibc what it expects.
491 seq_printf(m, "processor\t: %d\n", i);
495 * Dump out the common processor features in a single line.
496 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
497 * rather than attempting to parse this, but there's a body of
498 * software which does already (at least for 32-bit).
500 seq_puts(m, "Features\t:");
501 if (personality(current->personality) == PER_LINUX32) {
503 for (j = 0; compat_hwcap_str[j]; j++)
504 if (compat_elf_hwcap & (1 << j))
505 seq_printf(m, " %s", compat_hwcap_str[j]);
507 for (j = 0; compat_hwcap2_str[j]; j++)
508 if (compat_elf_hwcap2 & (1 << j))
509 seq_printf(m, " %s", compat_hwcap2_str[j]);
510 #endif /* CONFIG_COMPAT */
512 for (j = 0; hwcap_str[j]; j++)
513 if (elf_hwcap & (1 << j))
514 seq_printf(m, " %s", hwcap_str[j]);
518 seq_printf(m, "CPU implementer\t: 0x%02x\n",
519 MIDR_IMPLEMENTOR(midr));
520 seq_printf(m, "CPU architecture: 8\n");
521 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
522 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
523 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
529 static void *c_start(struct seq_file *m, loff_t *pos)
531 return *pos < 1 ? (void *)1 : NULL;
534 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
540 static void c_stop(struct seq_file *m, void *v)
544 const struct seq_operations cpuinfo_op = {