arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/kvm_host.h>
  25 #include <linux/uaccess.h>
  26 #include <asm/kvm_arm.h>
  27 #include <asm/kvm_host.h>
  28 #include <asm/kvm_emulate.h>
  29 #include <asm/kvm_coproc.h>
  30 #include <asm/kvm_mmu.h>
  31 #include <asm/cacheflush.h>
  32 #include <asm/cputype.h>
  33 #include <trace/events/kvm.h>
  34
  35 #include "sys_regs.h"
  36
  37 /*
  38  * All of this file is extremly similar to the ARM coproc.c, but the
  39  * types are different. My gut feeling is that it should be pretty
  40  * easy to merge, but that would be an ABI breakage -- again. VFP
  41  * would also need to be abstracted.
  42  *
  43  * For AArch32, we only take care of what is being trapped. Anything
  44  * that has to do with init and userspace access has to go via the
  45  * 64bit interface.
  46  */
  47
  48 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  49 static u32 cache_levels;
  50
  51 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  52 #define CSSELR_MAX 12
  53
  54 /* Which cache CCSIDR represents depends on CSSELR value. */
  55 static u32 get_ccsidr(u32 csselr)
  56 {
  57         u32 ccsidr;
  58
  59         /* Make sure noone else changes CSSELR during this! */
  60         local_irq_disable();
  61         /* Put value into CSSELR */
  62         asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
  63         isb();
  64         /* Read result out of CCSIDR */
  65         asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
  66         local_irq_enable();
  67
  68         return ccsidr;
  69 }
  70
  71 static void do_dc_cisw(u32 val)
  72 {
  73         asm volatile("dc cisw, %x0" : : "r" (val));
  74         dsb();
  75 }
  76
  77 static void do_dc_csw(u32 val)
  78 {
  79         asm volatile("dc csw, %x0" : : "r" (val));
  80         dsb();
  81 }
  82
  83 /* See note at ARM ARM B1.14.4 */
  84 static bool access_dcsw(struct kvm_vcpu *vcpu,
  85                         const struct sys_reg_params *p,
  86                         const struct sys_reg_desc *r)
  87 {
  88         unsigned long val;
  89         int cpu;
  90
  91         if (!p->is_write)
  92                 return read_from_write_only(vcpu, p);
  93
  94         cpu = get_cpu();
  95
  96         cpumask_setall(&vcpu->arch.require_dcache_flush);
  97         cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
  98
  99         /* If we were already preempted, take the long way around */
 100         if (cpu != vcpu->arch.last_pcpu) {
 101                 flush_cache_all();
 102                 goto done;
 103         }
 104
 105         val = *vcpu_reg(vcpu, p->Rt);
 106
 107         switch (p->CRm) {
 108         case 6:                 /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
 109         case 14:                /* DCCISW */
 110                 do_dc_cisw(val);
 111                 break;
 112
 113         case 10:                /* DCCSW */
 114                 do_dc_csw(val);
 115                 break;
 116         }
 117
 118 done:
 119         put_cpu();
 120
 121         return true;
 122 }
 123
 124 /*
 125  * Generic accessor for VM registers. Only called as long as HCR_TVM
 126  * is set.
 127  */
 128 static bool access_vm_reg(struct kvm_vcpu *vcpu,
 129                           const struct sys_reg_params *p,
 130                           const struct sys_reg_desc *r)
 131 {
 132         unsigned long val;
 133
 134         BUG_ON(!p->is_write);
 135
 136         val = *vcpu_reg(vcpu, p->Rt);
 137         if (!p->is_aarch32) {
 138                 vcpu_sys_reg(vcpu, r->reg) = val;
 139         } else {
 140                 vcpu_cp15(vcpu, r->reg) = val & 0xffffffffUL;
 141                 if (!p->is_32bit)
 142                         vcpu_cp15(vcpu, r->reg + 1) = val >> 32;
 143         }
 144         return true;
 145 }
 146
 147 /*
 148  * SCTLR_EL1 accessor. Only called as long as HCR_TVM is set.  If the
 149  * guest enables the MMU, we stop trapping the VM sys_regs and leave
 150  * it in complete control of the caches.
 151  */
 152 static bool access_sctlr(struct kvm_vcpu *vcpu,
 153                          const struct sys_reg_params *p,
 154                          const struct sys_reg_desc *r)
 155 {
 156         access_vm_reg(vcpu, p, r);
 157
 158         if (vcpu_has_cache_enabled(vcpu)) {     /* MMU+Caches enabled? */
 159                 vcpu->arch.hcr_el2 &= ~HCR_TVM;
 160                 stage2_flush_vm(vcpu->kvm);
 161         }
 162
 163         return true;
 164 }
 165
 166 /*
 167  * We could trap ID_DFR0 and tell the guest we don't support performance
 168  * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
 169  * NAKed, so it will read the PMCR anyway.
 170  *
 171  * Therefore we tell the guest we have 0 counters.  Unfortunately, we
 172  * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
 173  * all PM registers, which doesn't crash the guest kernel at least.
 174  */
 175 static bool pm_fake(struct kvm_vcpu *vcpu,
 176                     const struct sys_reg_params *p,
 177                     const struct sys_reg_desc *r)
 178 {
 179         if (p->is_write)
 180                 return ignore_write(vcpu, p);
 181         else
 182                 return read_zero(vcpu, p);
 183 }
 184
 185 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 186 {
 187         u64 amair;
 188
 189         asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
 190         vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
 191 }
 192
 193 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 194 {
 195         /*
 196          * Simply map the vcpu_id into the Aff0 field of the MPIDR.
 197          */
 198         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff);
 199 }
 200
 201 /*
 202  * Architected system registers.
 203  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
 204  */
 205 static const struct sys_reg_desc sys_reg_descs[] = {
 206         /* DC ISW */
 207         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
 208           access_dcsw },
 209         /* DC CSW */
 210         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
 211           access_dcsw },
 212         /* DC CISW */
 213         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
 214           access_dcsw },
 215
 216         /* TEECR32_EL1 */
 217         { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 218           NULL, reset_val, TEECR32_EL1, 0 },
 219         /* TEEHBR32_EL1 */
 220         { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
 221           NULL, reset_val, TEEHBR32_EL1, 0 },
 222         /* DBGVCR32_EL2 */
 223         { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
 224           NULL, reset_val, DBGVCR32_EL2, 0 },
 225
 226         /* MPIDR_EL1 */
 227         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
 228           NULL, reset_mpidr, MPIDR_EL1 },
 229         /* SCTLR_EL1 */
 230         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 231           access_sctlr, reset_val, SCTLR_EL1, 0x00C50078 },
 232         /* CPACR_EL1 */
 233         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
 234           NULL, reset_val, CPACR_EL1, 0 },
 235         /* TTBR0_EL1 */
 236         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
 237           access_vm_reg, reset_unknown, TTBR0_EL1 },
 238         /* TTBR1_EL1 */
 239         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
 240           access_vm_reg, reset_unknown, TTBR1_EL1 },
 241         /* TCR_EL1 */
 242         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
 243           access_vm_reg, reset_val, TCR_EL1, 0 },
 244
 245         /* AFSR0_EL1 */
 246         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
 247           access_vm_reg, reset_unknown, AFSR0_EL1 },
 248         /* AFSR1_EL1 */
 249         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
 250           access_vm_reg, reset_unknown, AFSR1_EL1 },
 251         /* ESR_EL1 */
 252         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
 253           access_vm_reg, reset_unknown, ESR_EL1 },
 254         /* FAR_EL1 */
 255         { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
 256           access_vm_reg, reset_unknown, FAR_EL1 },
 257         /* PAR_EL1 */
 258         { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
 259           NULL, reset_unknown, PAR_EL1 },
 260
 261         /* PMINTENSET_EL1 */
 262         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
 263           pm_fake },
 264         /* PMINTENCLR_EL1 */
 265         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
 266           pm_fake },
 267
 268         /* MAIR_EL1 */
 269         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
 270           access_vm_reg, reset_unknown, MAIR_EL1 },
 271         /* AMAIR_EL1 */
 272         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
 273           access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 274
 275         /* VBAR_EL1 */
 276         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
 277           NULL, reset_val, VBAR_EL1, 0 },
 278         /* CONTEXTIDR_EL1 */
 279         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
 280           access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
 281         /* TPIDR_EL1 */
 282         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
 283           NULL, reset_unknown, TPIDR_EL1 },
 284
 285         /* CNTKCTL_EL1 */
 286         { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
 287           NULL, reset_val, CNTKCTL_EL1, 0},
 288
 289         /* CSSELR_EL1 */
 290         { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 291           NULL, reset_unknown, CSSELR_EL1 },
 292
 293         /* PMCR_EL0 */
 294         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
 295           pm_fake },
 296         /* PMCNTENSET_EL0 */
 297         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
 298           pm_fake },
 299         /* PMCNTENCLR_EL0 */
 300         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
 301           pm_fake },
 302         /* PMOVSCLR_EL0 */
 303         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
 304           pm_fake },
 305         /* PMSWINC_EL0 */
 306         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
 307           pm_fake },
 308         /* PMSELR_EL0 */
 309         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
 310           pm_fake },
 311         /* PMCEID0_EL0 */
 312         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 313           pm_fake },
 314         /* PMCEID1_EL0 */
 315         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
 316           pm_fake },
 317         /* PMCCNTR_EL0 */
 318         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
 319           pm_fake },
 320         /* PMXEVTYPER_EL0 */
 321         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
 322           pm_fake },
 323         /* PMXEVCNTR_EL0 */
 324         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
 325           pm_fake },
 326         /* PMUSERENR_EL0 */
 327         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
 328           pm_fake },
 329         /* PMOVSSET_EL0 */
 330         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
 331           pm_fake },
 332
 333         /* TPIDR_EL0 */
 334         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
 335           NULL, reset_unknown, TPIDR_EL0 },
 336         /* TPIDRRO_EL0 */
 337         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
 338           NULL, reset_unknown, TPIDRRO_EL0 },
 339
 340         /* DACR32_EL2 */
 341         { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
 342           NULL, reset_unknown, DACR32_EL2 },
 343         /* IFSR32_EL2 */
 344         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
 345           NULL, reset_unknown, IFSR32_EL2 },
 346         /* FPEXC32_EL2 */
 347         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
 348           NULL, reset_val, FPEXC32_EL2, 0x70 },
 349 };
 350
 351 /*
 352  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
 353  * depending on the way they are accessed (as a 32bit or a 64bit
 354  * register).
 355  */
 356 static const struct sys_reg_desc cp15_regs[] = {
 357         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
 358         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR },
 359         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
 360         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
 361         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
 362         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
 363         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
 364         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
 365         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
 366         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
 367         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
 368         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
 369
 370         /*
 371          * DC{C,I,CI}SW operations:
 372          */
 373         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
 374         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
 375         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
 376
 377         { Op1( 0), CRn( 9), CRm(12), Op2( 0), pm_fake },
 378         { Op1( 0), CRn( 9), CRm(12), Op2( 1), pm_fake },
 379         { Op1( 0), CRn( 9), CRm(12), Op2( 2), pm_fake },
 380         { Op1( 0), CRn( 9), CRm(12), Op2( 3), pm_fake },
 381         { Op1( 0), CRn( 9), CRm(12), Op2( 5), pm_fake },
 382         { Op1( 0), CRn( 9), CRm(12), Op2( 6), pm_fake },
 383         { Op1( 0), CRn( 9), CRm(12), Op2( 7), pm_fake },
 384         { Op1( 0), CRn( 9), CRm(13), Op2( 0), pm_fake },
 385         { Op1( 0), CRn( 9), CRm(13), Op2( 1), pm_fake },
 386         { Op1( 0), CRn( 9), CRm(13), Op2( 2), pm_fake },
 387         { Op1( 0), CRn( 9), CRm(14), Op2( 0), pm_fake },
 388         { Op1( 0), CRn( 9), CRm(14), Op2( 1), pm_fake },
 389         { Op1( 0), CRn( 9), CRm(14), Op2( 2), pm_fake },
 390
 391         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
 392         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
 393         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
 394         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
 395         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
 396
 397         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
 398 };
 399
 400 /* Target specific emulation tables */
 401 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
 402
 403 void kvm_register_target_sys_reg_table(unsigned int target,
 404                                        struct kvm_sys_reg_target_table *table)
 405 {
 406         target_tables[target] = table;
 407 }
 408
 409 /* Get specific register table for this target. */
 410 static const struct sys_reg_desc *get_target_table(unsigned target,
 411                                                    bool mode_is_64,
 412                                                    size_t *num)
 413 {
 414         struct kvm_sys_reg_target_table *table;
 415
 416         table = target_tables[target];
 417         if (mode_is_64) {
 418                 *num = table->table64.num;
 419                 return table->table64.table;
 420         } else {
 421                 *num = table->table32.num;
 422                 return table->table32.table;
 423         }
 424 }
 425
 426 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
 427                                          const struct sys_reg_desc table[],
 428                                          unsigned int num)
 429 {
 430         unsigned int i;
 431
 432         for (i = 0; i < num; i++) {
 433                 const struct sys_reg_desc *r = &table[i];
 434
 435                 if (params->Op0 != r->Op0)
 436                         continue;
 437                 if (params->Op1 != r->Op1)
 438                         continue;
 439                 if (params->CRn != r->CRn)
 440                         continue;
 441                 if (params->CRm != r->CRm)
 442                         continue;
 443                 if (params->Op2 != r->Op2)
 444                         continue;
 445
 446                 return r;
 447         }
 448         return NULL;
 449 }
 450
 451 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
 452 {
 453         kvm_inject_undefined(vcpu);
 454         return 1;
 455 }
 456
 457 int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
 458 {
 459         kvm_inject_undefined(vcpu);
 460         return 1;
 461 }
 462
 463 static void emulate_cp15(struct kvm_vcpu *vcpu,
 464                          const struct sys_reg_params *params)
 465 {
 466         size_t num;
 467         const struct sys_reg_desc *table, *r;
 468
 469         table = get_target_table(vcpu->arch.target, false, &num);
 470
 471         /* Search target-specific then generic table. */
 472         r = find_reg(params, table, num);
 473         if (!r)
 474                 r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
 475
 476         if (likely(r)) {
 477                 /*
 478                  * Not having an accessor means that we have
 479                  * configured a trap that we don't know how to
 480                  * handle. This certainly qualifies as a gross bug
 481                  * that should be fixed right away.
 482                  */
 483                 BUG_ON(!r->access);
 484
 485                 if (likely(r->access(vcpu, params, r))) {
 486                         /* Skip instruction, since it was emulated */
 487                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 488                         return;
 489                 }
 490                 /* If access function fails, it should complain. */
 491         }
 492
 493         kvm_err("Unsupported guest CP15 access at: %08lx\n", *vcpu_pc(vcpu));
 494         print_sys_reg_instr(params);
 495         kvm_inject_undefined(vcpu);
 496 }
 497
 498 /**
 499  * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
 500  * @vcpu: The VCPU pointer
 501  * @run:  The kvm_run struct
 502  */
 503 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 504 {
 505         struct sys_reg_params params;
 506         u32 hsr = kvm_vcpu_get_hsr(vcpu);
 507         int Rt2 = (hsr >> 10) & 0xf;
 508
 509         params.is_aarch32 = true;
 510         params.is_32bit = false;
 511         params.CRm = (hsr >> 1) & 0xf;
 512         params.Rt = (hsr >> 5) & 0xf;
 513         params.is_write = ((hsr & 1) == 0);
 514
 515         params.Op0 = 0;
 516         params.Op1 = (hsr >> 16) & 0xf;
 517         params.Op2 = 0;
 518         params.CRn = 0;
 519
 520         /*
 521          * Massive hack here. Store Rt2 in the top 32bits so we only
 522          * have one register to deal with. As we use the same trap
 523          * backends between AArch32 and AArch64, we get away with it.
 524          */
 525         if (params.is_write) {
 526                 u64 val = *vcpu_reg(vcpu, params.Rt);
 527                 val &= 0xffffffff;
 528                 val |= *vcpu_reg(vcpu, Rt2) << 32;
 529                 *vcpu_reg(vcpu, params.Rt) = val;
 530         }
 531
 532         emulate_cp15(vcpu, &params);
 533
 534         /* Do the opposite hack for the read side */
 535         if (!params.is_write) {
 536                 u64 val = *vcpu_reg(vcpu, params.Rt);
 537                 val >>= 32;
 538                 *vcpu_reg(vcpu, Rt2) = val;
 539         }
 540
 541         return 1;
 542 }
 543
 544 /**
 545  * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
 546  * @vcpu: The VCPU pointer
 547  * @run:  The kvm_run struct
 548  */
 549 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 550 {
 551         struct sys_reg_params params;
 552         u32 hsr = kvm_vcpu_get_hsr(vcpu);
 553
 554         params.is_aarch32 = true;
 555         params.is_32bit = true;
 556         params.CRm = (hsr >> 1) & 0xf;
 557         params.Rt  = (hsr >> 5) & 0xf;
 558         params.is_write = ((hsr & 1) == 0);
 559         params.CRn = (hsr >> 10) & 0xf;
 560         params.Op0 = 0;
 561         params.Op1 = (hsr >> 14) & 0x7;
 562         params.Op2 = (hsr >> 17) & 0x7;
 563
 564         emulate_cp15(vcpu, &params);
 565         return 1;
 566 }
 567
 568 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
 569                            const struct sys_reg_params *params)
 570 {
 571         size_t num;
 572         const struct sys_reg_desc *table, *r;
 573
 574         table = get_target_table(vcpu->arch.target, true, &num);
 575
 576         /* Search target-specific then generic table. */
 577         r = find_reg(params, table, num);
 578         if (!r)
 579                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
 580
 581         if (likely(r)) {
 582                 /*
 583                  * Not having an accessor means that we have
 584                  * configured a trap that we don't know how to
 585                  * handle. This certainly qualifies as a gross bug
 586                  * that should be fixed right away.
 587                  */
 588                 BUG_ON(!r->access);
 589
 590                 if (likely(r->access(vcpu, params, r))) {
 591                         /* Skip instruction, since it was emulated */
 592                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 593                         return 1;
 594                 }
 595                 /* If access function fails, it should complain. */
 596         } else {
 597                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
 598                         *vcpu_pc(vcpu));
 599                 print_sys_reg_instr(params);
 600         }
 601         kvm_inject_undefined(vcpu);
 602         return 1;
 603 }
 604
 605 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
 606                               const struct sys_reg_desc *table, size_t num)
 607 {
 608         unsigned long i;
 609
 610         for (i = 0; i < num; i++)
 611                 if (table[i].reset)
 612                         table[i].reset(vcpu, &table[i]);
 613 }
 614
 615 /**
 616  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
 617  * @vcpu: The VCPU pointer
 618  * @run:  The kvm_run struct
 619  */
 620 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
 621 {
 622         struct sys_reg_params params;
 623         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
 624
 625         params.is_aarch32 = false;
 626         params.is_32bit = false;
 627         params.Op0 = (esr >> 20) & 3;
 628         params.Op1 = (esr >> 14) & 0x7;
 629         params.CRn = (esr >> 10) & 0xf;
 630         params.CRm = (esr >> 1) & 0xf;
 631         params.Op2 = (esr >> 17) & 0x7;
 632         params.Rt = (esr >> 5) & 0x1f;
 633         params.is_write = !(esr & 1);
 634
 635         return emulate_sys_reg(vcpu, &params);
 636 }
 637
 638 /******************************************************************************
 639  * Userspace API
 640  *****************************************************************************/
 641
 642 static bool index_to_params(u64 id, struct sys_reg_params *params)
 643 {
 644         switch (id & KVM_REG_SIZE_MASK) {
 645         case KVM_REG_SIZE_U64:
 646                 /* Any unused index bits means it's not valid. */
 647                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
 648                               | KVM_REG_ARM_COPROC_MASK
 649                               | KVM_REG_ARM64_SYSREG_OP0_MASK
 650                               | KVM_REG_ARM64_SYSREG_OP1_MASK
 651                               | KVM_REG_ARM64_SYSREG_CRN_MASK
 652                               | KVM_REG_ARM64_SYSREG_CRM_MASK
 653                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
 654                         return false;
 655                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
 656                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
 657                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
 658                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
 659                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
 660                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
 661                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
 662                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
 663                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
 664                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
 665                 return true;
 666         default:
 667                 return false;
 668         }
 669 }
 670
 671 /* Decode an index value, and find the sys_reg_desc entry. */
 672 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
 673                                                     u64 id)
 674 {
 675         size_t num;
 676         const struct sys_reg_desc *table, *r;
 677         struct sys_reg_params params;
 678
 679         /* We only do sys_reg for now. */
 680         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
 681                 return NULL;
 682
 683         if (!index_to_params(id, &params))
 684                 return NULL;
 685
 686         table = get_target_table(vcpu->arch.target, true, &num);
 687         r = find_reg(&params, table, num);
 688         if (!r)
 689                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
 690
 691         /* Not saved in the sys_reg array? */
 692         if (r && !r->reg)
 693                 r = NULL;
 694
 695         return r;
 696 }
 697
 698 /*
 699  * These are the invariant sys_reg registers: we let the guest see the
 700  * host versions of these, so they're part of the guest state.
 701  *
 702  * A future CPU may provide a mechanism to present different values to
 703  * the guest, or a future kvm may trap them.
 704  */
 705
 706 #define FUNCTION_INVARIANT(reg)                                         \
 707         static void get_##reg(struct kvm_vcpu *v,                       \
 708                               const struct sys_reg_desc *r)             \
 709         {                                                               \
 710                 u64 val;                                                \
 711                                                                         \
 712                 asm volatile("mrs %0, " __stringify(reg) "\n"           \
 713                              : "=r" (val));                             \
 714                 ((struct sys_reg_desc *)r)->val = val;                  \
 715         }
 716
 717 FUNCTION_INVARIANT(midr_el1)
 718 FUNCTION_INVARIANT(ctr_el0)
 719 FUNCTION_INVARIANT(revidr_el1)
 720 FUNCTION_INVARIANT(id_pfr0_el1)
 721 FUNCTION_INVARIANT(id_pfr1_el1)
 722 FUNCTION_INVARIANT(id_dfr0_el1)
 723 FUNCTION_INVARIANT(id_afr0_el1)
 724 FUNCTION_INVARIANT(id_mmfr0_el1)
 725 FUNCTION_INVARIANT(id_mmfr1_el1)
 726 FUNCTION_INVARIANT(id_mmfr2_el1)
 727 FUNCTION_INVARIANT(id_mmfr3_el1)
 728 FUNCTION_INVARIANT(id_isar0_el1)
 729 FUNCTION_INVARIANT(id_isar1_el1)
 730 FUNCTION_INVARIANT(id_isar2_el1)
 731 FUNCTION_INVARIANT(id_isar3_el1)
 732 FUNCTION_INVARIANT(id_isar4_el1)
 733 FUNCTION_INVARIANT(id_isar5_el1)
 734 FUNCTION_INVARIANT(clidr_el1)
 735 FUNCTION_INVARIANT(aidr_el1)
 736
 737 /* ->val is filled in by kvm_sys_reg_table_init() */
 738 static struct sys_reg_desc invariant_sys_regs[] = {
 739         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
 740           NULL, get_midr_el1 },
 741         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
 742           NULL, get_revidr_el1 },
 743         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
 744           NULL, get_id_pfr0_el1 },
 745         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
 746           NULL, get_id_pfr1_el1 },
 747         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
 748           NULL, get_id_dfr0_el1 },
 749         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
 750           NULL, get_id_afr0_el1 },
 751         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
 752           NULL, get_id_mmfr0_el1 },
 753         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
 754           NULL, get_id_mmfr1_el1 },
 755         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
 756           NULL, get_id_mmfr2_el1 },
 757         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
 758           NULL, get_id_mmfr3_el1 },
 759         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
 760           NULL, get_id_isar0_el1 },
 761         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
 762           NULL, get_id_isar1_el1 },
 763         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
 764           NULL, get_id_isar2_el1 },
 765         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
 766           NULL, get_id_isar3_el1 },
 767         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
 768           NULL, get_id_isar4_el1 },
 769         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
 770           NULL, get_id_isar5_el1 },
 771         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
 772           NULL, get_clidr_el1 },
 773         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
 774           NULL, get_aidr_el1 },
 775         { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
 776           NULL, get_ctr_el0 },
 777 };
 778
 779 static int reg_from_user(void *val, const void __user *uaddr, u64 id)
 780 {
 781         /* This Just Works because we are little endian. */
 782         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
 783                 return -EFAULT;
 784         return 0;
 785 }
 786
 787 static int reg_to_user(void __user *uaddr, const void *val, u64 id)
 788 {
 789         /* This Just Works because we are little endian. */
 790         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
 791                 return -EFAULT;
 792         return 0;
 793 }
 794
 795 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
 796 {
 797         struct sys_reg_params params;
 798         const struct sys_reg_desc *r;
 799
 800         if (!index_to_params(id, &params))
 801                 return -ENOENT;
 802
 803         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
 804         if (!r)
 805                 return -ENOENT;
 806
 807         return reg_to_user(uaddr, &r->val, id);
 808 }
 809
 810 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
 811 {
 812         struct sys_reg_params params;
 813         const struct sys_reg_desc *r;
 814         int err;
 815         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
 816
 817         if (!index_to_params(id, &params))
 818                 return -ENOENT;
 819         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
 820         if (!r)
 821                 return -ENOENT;
 822
 823         err = reg_from_user(&val, uaddr, id);
 824         if (err)
 825                 return err;
 826
 827         /* This is what we mean by invariant: you can't change it. */
 828         if (r->val != val)
 829                 return -EINVAL;
 830
 831         return 0;
 832 }
 833
 834 static bool is_valid_cache(u32 val)
 835 {
 836         u32 level, ctype;
 837
 838         if (val >= CSSELR_MAX)
 839                 return -ENOENT;
 840
 841         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
 842         level = (val >> 1);
 843         ctype = (cache_levels >> (level * 3)) & 7;
 844
 845         switch (ctype) {
 846         case 0: /* No cache */
 847                 return false;
 848         case 1: /* Instruction cache only */
 849                 return (val & 1);
 850         case 2: /* Data cache only */
 851         case 4: /* Unified cache */
 852                 return !(val & 1);
 853         case 3: /* Separate instruction and data caches */
 854                 return true;
 855         default: /* Reserved: we can't know instruction or data. */
 856                 return false;
 857         }
 858 }
 859
 860 static int demux_c15_get(u64 id, void __user *uaddr)
 861 {
 862         u32 val;
 863         u32 __user *uval = uaddr;
 864
 865         /* Fail if we have unknown bits set. */
 866         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
 867                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
 868                 return -ENOENT;
 869
 870         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
 871         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
 872                 if (KVM_REG_SIZE(id) != 4)
 873                         return -ENOENT;
 874                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
 875                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
 876                 if (!is_valid_cache(val))
 877                         return -ENOENT;
 878
 879                 return put_user(get_ccsidr(val), uval);
 880         default:
 881                 return -ENOENT;
 882         }
 883 }
 884
 885 static int demux_c15_set(u64 id, void __user *uaddr)
 886 {
 887         u32 val, newval;
 888         u32 __user *uval = uaddr;
 889
 890         /* Fail if we have unknown bits set. */
 891         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
 892                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
 893                 return -ENOENT;
 894
 895         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
 896         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
 897                 if (KVM_REG_SIZE(id) != 4)
 898                         return -ENOENT;
 899                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
 900                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
 901                 if (!is_valid_cache(val))
 902                         return -ENOENT;
 903
 904                 if (get_user(newval, uval))
 905                         return -EFAULT;
 906
 907                 /* This is also invariant: you can't change it. */
 908                 if (newval != get_ccsidr(val))
 909                         return -EINVAL;
 910                 return 0;
 911         default:
 912                 return -ENOENT;
 913         }
 914 }
 915
 916 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 917 {
 918         const struct sys_reg_desc *r;
 919         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
 920
 921         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
 922                 return demux_c15_get(reg->id, uaddr);
 923
 924         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
 925                 return -ENOENT;
 926
 927         r = index_to_sys_reg_desc(vcpu, reg->id);
 928         if (!r)
 929                 return get_invariant_sys_reg(reg->id, uaddr);
 930
 931         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
 932 }
 933
 934 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 935 {
 936         const struct sys_reg_desc *r;
 937         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
 938
 939         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
 940                 return demux_c15_set(reg->id, uaddr);
 941
 942         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
 943                 return -ENOENT;
 944
 945         r = index_to_sys_reg_desc(vcpu, reg->id);
 946         if (!r)
 947                 return set_invariant_sys_reg(reg->id, uaddr);
 948
 949         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
 950 }
 951
 952 static unsigned int num_demux_regs(void)
 953 {
 954         unsigned int i, count = 0;
 955
 956         for (i = 0; i < CSSELR_MAX; i++)
 957                 if (is_valid_cache(i))
 958                         count++;
 959
 960         return count;
 961 }
 962
 963 static int write_demux_regids(u64 __user *uindices)
 964 {
 965         u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
 966         unsigned int i;
 967
 968         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
 969         for (i = 0; i < CSSELR_MAX; i++) {
 970                 if (!is_valid_cache(i))
 971                         continue;
 972                 if (put_user(val | i, uindices))
 973                         return -EFAULT;
 974                 uindices++;
 975         }
 976         return 0;
 977 }
 978
 979 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
 980 {
 981         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
 982                 KVM_REG_ARM64_SYSREG |
 983                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
 984                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
 985                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
 986                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
 987                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
 988 }
 989
 990 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
 991 {
 992         if (!*uind)
 993                 return true;
 994
 995         if (put_user(sys_reg_to_index(reg), *uind))
 996                 return false;
 997
 998         (*uind)++;
 999         return true;
1000 }
1001
1002 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
1003 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
1004 {
1005         const struct sys_reg_desc *i1, *i2, *end1, *end2;
1006         unsigned int total = 0;
1007         size_t num;
1008
1009         /* We check for duplicates here, to allow arch-specific overrides. */
1010         i1 = get_target_table(vcpu->arch.target, true, &num);
1011         end1 = i1 + num;
1012         i2 = sys_reg_descs;
1013         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
1014
1015         BUG_ON(i1 == end1 || i2 == end2);
1016
1017         /* Walk carefully, as both tables may refer to the same register. */
1018         while (i1 || i2) {
1019                 int cmp = cmp_sys_reg(i1, i2);
1020                 /* target-specific overrides generic entry. */
1021                 if (cmp <= 0) {
1022                         /* Ignore registers we trap but don't save. */
1023                         if (i1->reg) {
1024                                 if (!copy_reg_to_user(i1, &uind))
1025                                         return -EFAULT;
1026                                 total++;
1027                         }
1028                 } else {
1029                         /* Ignore registers we trap but don't save. */
1030                         if (i2->reg) {
1031                                 if (!copy_reg_to_user(i2, &uind))
1032                                         return -EFAULT;
1033                                 total++;
1034                         }
1035                 }
1036
1037                 if (cmp <= 0 && ++i1 == end1)
1038                         i1 = NULL;
1039                 if (cmp >= 0 && ++i2 == end2)
1040                         i2 = NULL;
1041         }
1042         return total;
1043 }
1044
1045 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
1046 {
1047         return ARRAY_SIZE(invariant_sys_regs)
1048                 + num_demux_regs()
1049                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
1050 }
1051
1052 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1053 {
1054         unsigned int i;
1055         int err;
1056
1057         /* Then give them all the invariant registers' indices. */
1058         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
1059                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
1060                         return -EFAULT;
1061                 uindices++;
1062         }
1063
1064         err = walk_sys_regs(vcpu, uindices);
1065         if (err < 0)
1066                 return err;
1067         uindices += err;
1068
1069         return write_demux_regids(uindices);
1070 }
1071
1072 void kvm_sys_reg_table_init(void)
1073 {
1074         unsigned int i;
1075         struct sys_reg_desc clidr;
1076
1077         /* Make sure tables are unique and in order. */
1078         for (i = 1; i < ARRAY_SIZE(sys_reg_descs); i++)
1079                 BUG_ON(cmp_sys_reg(&sys_reg_descs[i-1], &sys_reg_descs[i]) >= 0);
1080
1081         /* We abuse the reset function to overwrite the table itself. */
1082         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
1083                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
1084
1085         /*
1086          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
1087          *
1088          *   If software reads the Cache Type fields from Ctype1
1089          *   upwards, once it has seen a value of 0b000, no caches
1090          *   exist at further-out levels of the hierarchy. So, for
1091          *   example, if Ctype3 is the first Cache Type field with a
1092          *   value of 0b000, the values of Ctype4 to Ctype7 must be
1093          *   ignored.
1094          */
1095         get_clidr_el1(NULL, &clidr); /* Ugly... */
1096         cache_levels = clidr.val;
1097         for (i = 0; i < 7; i++)
1098                 if (((cache_levels >> (i*3)) & 7) == 0)
1099                         break;
1100         /* Clear all higher bits. */
1101         cache_levels &= (1 << (i*3))-1;
1102 }
1103
1104 /**
1105  * kvm_reset_sys_regs - sets system registers to reset value
1106  * @vcpu: The VCPU pointer
1107  *
1108  * This function finds the right table above and sets the registers on the
1109  * virtual CPU struct to their architecturally defined reset values.
1110  */
1111 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
1112 {
1113         size_t num;
1114         const struct sys_reg_desc *table;
1115
1116         /* Catch someone adding a register without putting in reset entry. */
1117         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
1118
1119         /* Generic chip reset first (so target could override). */
1120         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1121
1122         table = get_target_table(vcpu->arch.target, true, &num);
1123         reset_sys_reg_descs(vcpu, table, num);
1124
1125         for (num = 1; num < NR_SYS_REGS; num++)
1126                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
1127                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
1128 }