2 * Based on arch/arm/mm/context.c
4 * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/bitops.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
25 #include <asm/cpufeature.h>
26 #include <asm/mmu_context.h>
27 #include <asm/tlbflush.h>
30 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
32 static atomic64_t asid_generation;
33 static unsigned long *asid_map;
35 static DEFINE_PER_CPU(atomic64_t, active_asids);
36 static DEFINE_PER_CPU(u64, reserved_asids);
37 static cpumask_t tlb_flush_pending;
39 #define ASID_MASK (~GENMASK(asid_bits - 1, 0))
40 #define ASID_FIRST_VERSION (1UL << asid_bits)
41 #define NUM_USER_ASIDS ASID_FIRST_VERSION
43 static void flush_context(unsigned int cpu)
48 /* Update the list of reserved ASIDs and the ASID bitmap. */
49 bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
52 * Ensure the generation bump is observed before we xchg the
57 for_each_possible_cpu(i) {
58 asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0);
60 * If this CPU has already been through a
61 * rollover, but hasn't run another task in
62 * the meantime, we must preserve its reserved
63 * ASID, as this is the only trace we have of
64 * the process it is still running.
67 asid = per_cpu(reserved_asids, i);
68 __set_bit(asid & ~ASID_MASK, asid_map);
69 per_cpu(reserved_asids, i) = asid;
72 /* Queue a TLB invalidate and flush the I-cache if necessary. */
73 cpumask_setall(&tlb_flush_pending);
75 if (icache_is_aivivt())
79 static int is_reserved_asid(u64 asid)
82 for_each_possible_cpu(cpu)
83 if (per_cpu(reserved_asids, cpu) == asid)
88 static u64 new_context(struct mm_struct *mm, unsigned int cpu)
90 static u32 cur_idx = 1;
91 u64 asid = atomic64_read(&mm->context.id);
92 u64 generation = atomic64_read(&asid_generation);
96 * If our current ASID was active during a rollover, we
97 * can continue to use it and this was just a false alarm.
99 if (is_reserved_asid(asid))
100 return generation | (asid & ~ASID_MASK);
103 * We had a valid ASID in a previous life, so try to re-use
107 if (!__test_and_set_bit(asid, asid_map))
112 * Allocate a free ASID. If we can't find one, take a note of the
113 * currently active ASIDs and mark the TLBs as requiring flushes.
114 * We always count from ASID #1, as we use ASID #0 when setting a
115 * reserved TTBR0 for the init_mm.
117 asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx);
118 if (asid != NUM_USER_ASIDS)
121 /* We're out of ASIDs, so increment the global generation count */
122 generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION,
126 /* We have at least 1 ASID per CPU, so this will always succeed */
127 asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
130 __set_bit(asid, asid_map);
138 void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
143 asid = atomic64_read(&mm->context.id);
146 * The memory ordering here is subtle. We rely on the control
147 * dependency between the generation read and the update of
148 * active_asids to ensure that we are synchronised with a
149 * parallel rollover (i.e. this pairs with the smp_wmb() in
152 if (!((asid ^ atomic64_read(&asid_generation)) >> asid_bits)
153 && atomic64_xchg_relaxed(&per_cpu(active_asids, cpu), asid))
154 goto switch_mm_fastpath;
156 raw_spin_lock_irqsave(&cpu_asid_lock, flags);
157 /* Check that our ASID belongs to the current generation. */
158 asid = atomic64_read(&mm->context.id);
159 if ((asid ^ atomic64_read(&asid_generation)) >> asid_bits) {
160 asid = new_context(mm, cpu);
161 atomic64_set(&mm->context.id, asid);
164 if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
165 local_flush_tlb_all();
167 atomic64_set(&per_cpu(active_asids, cpu), asid);
168 raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
171 cpu_switch_mm(mm->pgd, mm);
174 static int asids_init(void)
176 int fld = cpuid_feature_extract_field(read_cpuid(ID_AA64MMFR0_EL1), 4);
180 pr_warn("Unknown ASID size (%d); assuming 8-bit\n", fld);
189 /* If we end up with more CPUs than ASIDs, expect things to crash */
190 WARN_ON(NUM_USER_ASIDS < num_possible_cpus());
191 atomic64_set(&asid_generation, ASID_FIRST_VERSION);
192 asid_map = kzalloc(BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(*asid_map),
195 panic("Failed to allocate bitmap for %lu ASIDs\n",
198 pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
201 early_initcall(asids_init);