arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/fb.h>
  10 #include <linux/init.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/usb/atmel_usba_udc.h>
  15
  16 #include <asm/io.h>
  17 #include <asm/irq.h>
  18
  19 #include <asm/arch/at32ap700x.h>
  20 #include <asm/arch/board.h>
  21 #include <asm/arch/portmux.h>
  22
  23 #include <video/atmel_lcdc.h>
  24
  25 #include "clock.h"
  26 #include "hmatrix.h"
  27 #include "pio.h"
  28 #include "pm.h"
  29
  30
  31 #define PBMEM(base)                                     \
  32         {                                               \
  33                 .start          = base,                 \
  34                 .end            = base + 0x3ff,         \
  35                 .flags          = IORESOURCE_MEM,       \
  36         }
  37 #define IRQ(num)                                        \
  38         {                                               \
  39                 .start          = num,                  \
  40                 .end            = num,                  \
  41                 .flags          = IORESOURCE_IRQ,       \
  42         }
  43 #define NAMED_IRQ(num, _name)                           \
  44         {                                               \
  45                 .start          = num,                  \
  46                 .end            = num,                  \
  47                 .name           = _name,                \
  48                 .flags          = IORESOURCE_IRQ,       \
  49         }
  50
  51 /* REVISIT these assume *every* device supports DMA, but several
  52  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  53  */
  54 #define DEFINE_DEV(_name, _id)                                  \
  55 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  56 static struct platform_device _name##_id##_device = {           \
  57         .name           = #_name,                               \
  58         .id             = _id,                                  \
  59         .dev            = {                                     \
  60                 .dma_mask = &_name##_id##_dma_mask,             \
  61                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  62         },                                                      \
  63         .resource       = _name##_id##_resource,                \
  64         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  65 }
  66 #define DEFINE_DEV_DATA(_name, _id)                             \
  67 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  68 static struct platform_device _name##_id##_device = {           \
  69         .name           = #_name,                               \
  70         .id             = _id,                                  \
  71         .dev            = {                                     \
  72                 .dma_mask = &_name##_id##_dma_mask,             \
  73                 .platform_data  = &_name##_id##_data,           \
  74                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  75         },                                                      \
  76         .resource       = _name##_id##_resource,                \
  77         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  78 }
  79
  80 #define select_peripheral(pin, periph, flags)                   \
  81         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  82
  83 #define DEV_CLK(_name, devname, bus, _index)                    \
  84 static struct clk devname##_##_name = {                         \
  85         .name           = #_name,                               \
  86         .dev            = &devname##_device.dev,                \
  87         .parent         = &bus##_clk,                           \
  88         .mode           = bus##_clk_mode,                       \
  89         .get_rate       = bus##_clk_get_rate,                   \
  90         .index          = _index,                               \
  91 }
  92
  93 static DEFINE_SPINLOCK(pm_lock);
  94
  95 unsigned long at32ap7000_osc_rates[3] = {
  96         [0] = 32768,
  97         /* FIXME: these are ATSTK1002-specific */
  98         [1] = 20000000,
  99         [2] = 12000000,
 100 };
 101
 102 static unsigned long osc_get_rate(struct clk *clk)
 103 {
 104         return at32ap7000_osc_rates[clk->index];
 105 }
 106
 107 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 108 {
 109         unsigned long div, mul, rate;
 110
 111         if (!(control & PM_BIT(PLLEN)))
 112                 return 0;
 113
 114         div = PM_BFEXT(PLLDIV, control) + 1;
 115         mul = PM_BFEXT(PLLMUL, control) + 1;
 116
 117         rate = clk->parent->get_rate(clk->parent);
 118         rate = (rate + div / 2) / div;
 119         rate *= mul;
 120
 121         return rate;
 122 }
 123
 124 static unsigned long pll0_get_rate(struct clk *clk)
 125 {
 126         u32 control;
 127
 128         control = pm_readl(PLL0);
 129
 130         return pll_get_rate(clk, control);
 131 }
 132
 133 static unsigned long pll1_get_rate(struct clk *clk)
 134 {
 135         u32 control;
 136
 137         control = pm_readl(PLL1);
 138
 139         return pll_get_rate(clk, control);
 140 }
 141
 142 /*
 143  * The AT32AP7000 has five primary clock sources: One 32kHz
 144  * oscillator, two crystal oscillators and two PLLs.
 145  */
 146 static struct clk osc32k = {
 147         .name           = "osc32k",
 148         .get_rate       = osc_get_rate,
 149         .users          = 1,
 150         .index          = 0,
 151 };
 152 static struct clk osc0 = {
 153         .name           = "osc0",
 154         .get_rate       = osc_get_rate,
 155         .users          = 1,
 156         .index          = 1,
 157 };
 158 static struct clk osc1 = {
 159         .name           = "osc1",
 160         .get_rate       = osc_get_rate,
 161         .index          = 2,
 162 };
 163 static struct clk pll0 = {
 164         .name           = "pll0",
 165         .get_rate       = pll0_get_rate,
 166         .parent         = &osc0,
 167 };
 168 static struct clk pll1 = {
 169         .name           = "pll1",
 170         .get_rate       = pll1_get_rate,
 171         .parent         = &osc0,
 172 };
 173
 174 /*
 175  * The main clock can be either osc0 or pll0.  The boot loader may
 176  * have chosen one for us, so we don't really know which one until we
 177  * have a look at the SM.
 178  */
 179 static struct clk *main_clock;
 180
 181 /*
 182  * Synchronous clocks are generated from the main clock. The clocks
 183  * must satisfy the constraint
 184  *   fCPU >= fHSB >= fPB
 185  * i.e. each clock must not be faster than its parent.
 186  */
 187 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 188 {
 189         return main_clock->get_rate(main_clock) >> shift;
 190 };
 191
 192 static void cpu_clk_mode(struct clk *clk, int enabled)
 193 {
 194         unsigned long flags;
 195         u32 mask;
 196
 197         spin_lock_irqsave(&pm_lock, flags);
 198         mask = pm_readl(CPU_MASK);
 199         if (enabled)
 200                 mask |= 1 << clk->index;
 201         else
 202                 mask &= ~(1 << clk->index);
 203         pm_writel(CPU_MASK, mask);
 204         spin_unlock_irqrestore(&pm_lock, flags);
 205 }
 206
 207 static unsigned long cpu_clk_get_rate(struct clk *clk)
 208 {
 209         unsigned long cksel, shift = 0;
 210
 211         cksel = pm_readl(CKSEL);
 212         if (cksel & PM_BIT(CPUDIV))
 213                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 214
 215         return bus_clk_get_rate(clk, shift);
 216 }
 217
 218 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 219 {
 220         u32 control;
 221         unsigned long parent_rate, child_div, actual_rate, div;
 222
 223         parent_rate = clk->parent->get_rate(clk->parent);
 224         control = pm_readl(CKSEL);
 225
 226         if (control & PM_BIT(HSBDIV))
 227                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 228         else
 229                 child_div = 1;
 230
 231         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 232                 actual_rate = parent_rate;
 233                 control &= ~PM_BIT(CPUDIV);
 234         } else {
 235                 unsigned int cpusel;
 236                 div = (parent_rate + rate / 2) / rate;
 237                 if (div > child_div)
 238                         div = child_div;
 239                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 240                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 241                 actual_rate = parent_rate / (1 << (cpusel + 1));
 242         }
 243
 244         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 245                         clk->name, rate, actual_rate);
 246
 247         if (apply)
 248                 pm_writel(CKSEL, control);
 249
 250         return actual_rate;
 251 }
 252
 253 static void hsb_clk_mode(struct clk *clk, int enabled)
 254 {
 255         unsigned long flags;
 256         u32 mask;
 257
 258         spin_lock_irqsave(&pm_lock, flags);
 259         mask = pm_readl(HSB_MASK);
 260         if (enabled)
 261                 mask |= 1 << clk->index;
 262         else
 263                 mask &= ~(1 << clk->index);
 264         pm_writel(HSB_MASK, mask);
 265         spin_unlock_irqrestore(&pm_lock, flags);
 266 }
 267
 268 static unsigned long hsb_clk_get_rate(struct clk *clk)
 269 {
 270         unsigned long cksel, shift = 0;
 271
 272         cksel = pm_readl(CKSEL);
 273         if (cksel & PM_BIT(HSBDIV))
 274                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 275
 276         return bus_clk_get_rate(clk, shift);
 277 }
 278
 279 static void pba_clk_mode(struct clk *clk, int enabled)
 280 {
 281         unsigned long flags;
 282         u32 mask;
 283
 284         spin_lock_irqsave(&pm_lock, flags);
 285         mask = pm_readl(PBA_MASK);
 286         if (enabled)
 287                 mask |= 1 << clk->index;
 288         else
 289                 mask &= ~(1 << clk->index);
 290         pm_writel(PBA_MASK, mask);
 291         spin_unlock_irqrestore(&pm_lock, flags);
 292 }
 293
 294 static unsigned long pba_clk_get_rate(struct clk *clk)
 295 {
 296         unsigned long cksel, shift = 0;
 297
 298         cksel = pm_readl(CKSEL);
 299         if (cksel & PM_BIT(PBADIV))
 300                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 301
 302         return bus_clk_get_rate(clk, shift);
 303 }
 304
 305 static void pbb_clk_mode(struct clk *clk, int enabled)
 306 {
 307         unsigned long flags;
 308         u32 mask;
 309
 310         spin_lock_irqsave(&pm_lock, flags);
 311         mask = pm_readl(PBB_MASK);
 312         if (enabled)
 313                 mask |= 1 << clk->index;
 314         else
 315                 mask &= ~(1 << clk->index);
 316         pm_writel(PBB_MASK, mask);
 317         spin_unlock_irqrestore(&pm_lock, flags);
 318 }
 319
 320 static unsigned long pbb_clk_get_rate(struct clk *clk)
 321 {
 322         unsigned long cksel, shift = 0;
 323
 324         cksel = pm_readl(CKSEL);
 325         if (cksel & PM_BIT(PBBDIV))
 326                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 327
 328         return bus_clk_get_rate(clk, shift);
 329 }
 330
 331 static struct clk cpu_clk = {
 332         .name           = "cpu",
 333         .get_rate       = cpu_clk_get_rate,
 334         .set_rate       = cpu_clk_set_rate,
 335         .users          = 1,
 336 };
 337 static struct clk hsb_clk = {
 338         .name           = "hsb",
 339         .parent         = &cpu_clk,
 340         .get_rate       = hsb_clk_get_rate,
 341 };
 342 static struct clk pba_clk = {
 343         .name           = "pba",
 344         .parent         = &hsb_clk,
 345         .mode           = hsb_clk_mode,
 346         .get_rate       = pba_clk_get_rate,
 347         .index          = 1,
 348 };
 349 static struct clk pbb_clk = {
 350         .name           = "pbb",
 351         .parent         = &hsb_clk,
 352         .mode           = hsb_clk_mode,
 353         .get_rate       = pbb_clk_get_rate,
 354         .users          = 1,
 355         .index          = 2,
 356 };
 357
 358 /* --------------------------------------------------------------------
 359  *  Generic Clock operations
 360  * -------------------------------------------------------------------- */
 361
 362 static void genclk_mode(struct clk *clk, int enabled)
 363 {
 364         u32 control;
 365
 366         control = pm_readl(GCCTRL(clk->index));
 367         if (enabled)
 368                 control |= PM_BIT(CEN);
 369         else
 370                 control &= ~PM_BIT(CEN);
 371         pm_writel(GCCTRL(clk->index), control);
 372 }
 373
 374 static unsigned long genclk_get_rate(struct clk *clk)
 375 {
 376         u32 control;
 377         unsigned long div = 1;
 378
 379         control = pm_readl(GCCTRL(clk->index));
 380         if (control & PM_BIT(DIVEN))
 381                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 382
 383         return clk->parent->get_rate(clk->parent) / div;
 384 }
 385
 386 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 387 {
 388         u32 control;
 389         unsigned long parent_rate, actual_rate, div;
 390
 391         parent_rate = clk->parent->get_rate(clk->parent);
 392         control = pm_readl(GCCTRL(clk->index));
 393
 394         if (rate > 3 * parent_rate / 4) {
 395                 actual_rate = parent_rate;
 396                 control &= ~PM_BIT(DIVEN);
 397         } else {
 398                 div = (parent_rate + rate) / (2 * rate) - 1;
 399                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 400                 actual_rate = parent_rate / (2 * (div + 1));
 401         }
 402
 403         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 404                 clk->name, rate, actual_rate);
 405
 406         if (apply)
 407                 pm_writel(GCCTRL(clk->index), control);
 408
 409         return actual_rate;
 410 }
 411
 412 int genclk_set_parent(struct clk *clk, struct clk *parent)
 413 {
 414         u32 control;
 415
 416         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 417                 clk->name, parent->name, clk->parent->name);
 418
 419         control = pm_readl(GCCTRL(clk->index));
 420
 421         if (parent == &osc1 || parent == &pll1)
 422                 control |= PM_BIT(OSCSEL);
 423         else if (parent == &osc0 || parent == &pll0)
 424                 control &= ~PM_BIT(OSCSEL);
 425         else
 426                 return -EINVAL;
 427
 428         if (parent == &pll0 || parent == &pll1)
 429                 control |= PM_BIT(PLLSEL);
 430         else
 431                 control &= ~PM_BIT(PLLSEL);
 432
 433         pm_writel(GCCTRL(clk->index), control);
 434         clk->parent = parent;
 435
 436         return 0;
 437 }
 438
 439 static void __init genclk_init_parent(struct clk *clk)
 440 {
 441         u32 control;
 442         struct clk *parent;
 443
 444         BUG_ON(clk->index > 7);
 445
 446         control = pm_readl(GCCTRL(clk->index));
 447         if (control & PM_BIT(OSCSEL))
 448                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 449         else
 450                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 451
 452         clk->parent = parent;
 453 }
 454
 455 /* --------------------------------------------------------------------
 456  *  System peripherals
 457  * -------------------------------------------------------------------- */
 458 static struct resource at32_pm0_resource[] = {
 459         {
 460                 .start  = 0xfff00000,
 461                 .end    = 0xfff0007f,
 462                 .flags  = IORESOURCE_MEM,
 463         },
 464         IRQ(20),
 465 };
 466
 467 static struct resource at32ap700x_rtc0_resource[] = {
 468         {
 469                 .start  = 0xfff00080,
 470                 .end    = 0xfff000af,
 471                 .flags  = IORESOURCE_MEM,
 472         },
 473         IRQ(21),
 474 };
 475
 476 static struct resource at32_wdt0_resource[] = {
 477         {
 478                 .start  = 0xfff000b0,
 479                 .end    = 0xfff000cf,
 480                 .flags  = IORESOURCE_MEM,
 481         },
 482 };
 483
 484 static struct resource at32_eic0_resource[] = {
 485         {
 486                 .start  = 0xfff00100,
 487                 .end    = 0xfff0013f,
 488                 .flags  = IORESOURCE_MEM,
 489         },
 490         IRQ(19),
 491 };
 492
 493 DEFINE_DEV(at32_pm, 0);
 494 DEFINE_DEV(at32ap700x_rtc, 0);
 495 DEFINE_DEV(at32_wdt, 0);
 496 DEFINE_DEV(at32_eic, 0);
 497
 498 /*
 499  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 500  * is always running.
 501  */
 502 static struct clk at32_pm_pclk = {
 503         .name           = "pclk",
 504         .dev            = &at32_pm0_device.dev,
 505         .parent         = &pbb_clk,
 506         .mode           = pbb_clk_mode,
 507         .get_rate       = pbb_clk_get_rate,
 508         .users          = 1,
 509         .index          = 0,
 510 };
 511
 512 static struct resource intc0_resource[] = {
 513         PBMEM(0xfff00400),
 514 };
 515 struct platform_device at32_intc0_device = {
 516         .name           = "intc",
 517         .id             = 0,
 518         .resource       = intc0_resource,
 519         .num_resources  = ARRAY_SIZE(intc0_resource),
 520 };
 521 DEV_CLK(pclk, at32_intc0, pbb, 1);
 522
 523 static struct clk ebi_clk = {
 524         .name           = "ebi",
 525         .parent         = &hsb_clk,
 526         .mode           = hsb_clk_mode,
 527         .get_rate       = hsb_clk_get_rate,
 528         .users          = 1,
 529 };
 530 static struct clk hramc_clk = {
 531         .name           = "hramc",
 532         .parent         = &hsb_clk,
 533         .mode           = hsb_clk_mode,
 534         .get_rate       = hsb_clk_get_rate,
 535         .users          = 1,
 536         .index          = 3,
 537 };
 538
 539 static struct resource smc0_resource[] = {
 540         PBMEM(0xfff03400),
 541 };
 542 DEFINE_DEV(smc, 0);
 543 DEV_CLK(pclk, smc0, pbb, 13);
 544 DEV_CLK(mck, smc0, hsb, 0);
 545
 546 static struct platform_device pdc_device = {
 547         .name           = "pdc",
 548         .id             = 0,
 549 };
 550 DEV_CLK(hclk, pdc, hsb, 4);
 551 DEV_CLK(pclk, pdc, pba, 16);
 552
 553 static struct clk pico_clk = {
 554         .name           = "pico",
 555         .parent         = &cpu_clk,
 556         .mode           = cpu_clk_mode,
 557         .get_rate       = cpu_clk_get_rate,
 558         .users          = 1,
 559 };
 560
 561 static struct resource dmaca0_resource[] = {
 562         {
 563                 .start  = 0xff200000,
 564                 .end    = 0xff20ffff,
 565                 .flags  = IORESOURCE_MEM,
 566         },
 567         IRQ(2),
 568 };
 569 DEFINE_DEV(dmaca, 0);
 570 DEV_CLK(hclk, dmaca0, hsb, 10);
 571
 572 /* --------------------------------------------------------------------
 573  * HMATRIX
 574  * -------------------------------------------------------------------- */
 575
 576 static struct clk hmatrix_clk = {
 577         .name           = "hmatrix_clk",
 578         .parent         = &pbb_clk,
 579         .mode           = pbb_clk_mode,
 580         .get_rate       = pbb_clk_get_rate,
 581         .index          = 2,
 582         .users          = 1,
 583 };
 584 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 585
 586 #define hmatrix_readl(reg)                                      \
 587         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 588 #define hmatrix_writel(reg,value)                               \
 589         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 590
 591 /*
 592  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 593  * External Bus Interface (EBI). This can be used to enable special
 594  * features like CompactFlash support, NAND Flash support, etc. on
 595  * certain chipselects.
 596  */
 597 static inline void set_ebi_sfr_bits(u32 mask)
 598 {
 599         u32 sfr;
 600
 601         clk_enable(&hmatrix_clk);
 602         sfr = hmatrix_readl(SFR4);
 603         sfr |= mask;
 604         hmatrix_writel(SFR4, sfr);
 605         clk_disable(&hmatrix_clk);
 606 }
 607
 608 /* --------------------------------------------------------------------
 609  *  Timer/Counter (TC)
 610  * -------------------------------------------------------------------- */
 611
 612 static struct resource at32_tcb0_resource[] = {
 613         PBMEM(0xfff00c00),
 614         IRQ(22),
 615 };
 616 static struct platform_device at32_tcb0_device = {
 617         .name           = "atmel_tcb",
 618         .id             = 0,
 619         .resource       = at32_tcb0_resource,
 620         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 621 };
 622 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 623
 624 static struct resource at32_tcb1_resource[] = {
 625         PBMEM(0xfff01000),
 626         IRQ(23),
 627 };
 628 static struct platform_device at32_tcb1_device = {
 629         .name           = "atmel_tcb",
 630         .id             = 1,
 631         .resource       = at32_tcb1_resource,
 632         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 633 };
 634 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 635
 636 /* --------------------------------------------------------------------
 637  *  PIO
 638  * -------------------------------------------------------------------- */
 639
 640 static struct resource pio0_resource[] = {
 641         PBMEM(0xffe02800),
 642         IRQ(13),
 643 };
 644 DEFINE_DEV(pio, 0);
 645 DEV_CLK(mck, pio0, pba, 10);
 646
 647 static struct resource pio1_resource[] = {
 648         PBMEM(0xffe02c00),
 649         IRQ(14),
 650 };
 651 DEFINE_DEV(pio, 1);
 652 DEV_CLK(mck, pio1, pba, 11);
 653
 654 static struct resource pio2_resource[] = {
 655         PBMEM(0xffe03000),
 656         IRQ(15),
 657 };
 658 DEFINE_DEV(pio, 2);
 659 DEV_CLK(mck, pio2, pba, 12);
 660
 661 static struct resource pio3_resource[] = {
 662         PBMEM(0xffe03400),
 663         IRQ(16),
 664 };
 665 DEFINE_DEV(pio, 3);
 666 DEV_CLK(mck, pio3, pba, 13);
 667
 668 static struct resource pio4_resource[] = {
 669         PBMEM(0xffe03800),
 670         IRQ(17),
 671 };
 672 DEFINE_DEV(pio, 4);
 673 DEV_CLK(mck, pio4, pba, 14);
 674
 675 void __init at32_add_system_devices(void)
 676 {
 677         platform_device_register(&at32_pm0_device);
 678         platform_device_register(&at32_intc0_device);
 679         platform_device_register(&at32ap700x_rtc0_device);
 680         platform_device_register(&at32_wdt0_device);
 681         platform_device_register(&at32_eic0_device);
 682         platform_device_register(&smc0_device);
 683         platform_device_register(&pdc_device);
 684         platform_device_register(&dmaca0_device);
 685
 686         platform_device_register(&at32_tcb0_device);
 687         platform_device_register(&at32_tcb1_device);
 688
 689         platform_device_register(&pio0_device);
 690         platform_device_register(&pio1_device);
 691         platform_device_register(&pio2_device);
 692         platform_device_register(&pio3_device);
 693         platform_device_register(&pio4_device);
 694 }
 695
 696 /* --------------------------------------------------------------------
 697  *  USART
 698  * -------------------------------------------------------------------- */
 699
 700 static struct atmel_uart_data atmel_usart0_data = {
 701         .use_dma_tx     = 1,
 702         .use_dma_rx     = 1,
 703 };
 704 static struct resource atmel_usart0_resource[] = {
 705         PBMEM(0xffe00c00),
 706         IRQ(6),
 707 };
 708 DEFINE_DEV_DATA(atmel_usart, 0);
 709 DEV_CLK(usart, atmel_usart0, pba, 3);
 710
 711 static struct atmel_uart_data atmel_usart1_data = {
 712         .use_dma_tx     = 1,
 713         .use_dma_rx     = 1,
 714 };
 715 static struct resource atmel_usart1_resource[] = {
 716         PBMEM(0xffe01000),
 717         IRQ(7),
 718 };
 719 DEFINE_DEV_DATA(atmel_usart, 1);
 720 DEV_CLK(usart, atmel_usart1, pba, 4);
 721
 722 static struct atmel_uart_data atmel_usart2_data = {
 723         .use_dma_tx     = 1,
 724         .use_dma_rx     = 1,
 725 };
 726 static struct resource atmel_usart2_resource[] = {
 727         PBMEM(0xffe01400),
 728         IRQ(8),
 729 };
 730 DEFINE_DEV_DATA(atmel_usart, 2);
 731 DEV_CLK(usart, atmel_usart2, pba, 5);
 732
 733 static struct atmel_uart_data atmel_usart3_data = {
 734         .use_dma_tx     = 1,
 735         .use_dma_rx     = 1,
 736 };
 737 static struct resource atmel_usart3_resource[] = {
 738         PBMEM(0xffe01800),
 739         IRQ(9),
 740 };
 741 DEFINE_DEV_DATA(atmel_usart, 3);
 742 DEV_CLK(usart, atmel_usart3, pba, 6);
 743
 744 static inline void configure_usart0_pins(void)
 745 {
 746         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 747         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 748 }
 749
 750 static inline void configure_usart1_pins(void)
 751 {
 752         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 753         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 754 }
 755
 756 static inline void configure_usart2_pins(void)
 757 {
 758         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 759         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 760 }
 761
 762 static inline void configure_usart3_pins(void)
 763 {
 764         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 765         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 766 }
 767
 768 static struct platform_device *__initdata at32_usarts[4];
 769
 770 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 771 {
 772         struct platform_device *pdev;
 773
 774         switch (hw_id) {
 775         case 0:
 776                 pdev = &atmel_usart0_device;
 777                 configure_usart0_pins();
 778                 break;
 779         case 1:
 780                 pdev = &atmel_usart1_device;
 781                 configure_usart1_pins();
 782                 break;
 783         case 2:
 784                 pdev = &atmel_usart2_device;
 785                 configure_usart2_pins();
 786                 break;
 787         case 3:
 788                 pdev = &atmel_usart3_device;
 789                 configure_usart3_pins();
 790                 break;
 791         default:
 792                 return;
 793         }
 794
 795         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 796                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 797                 struct atmel_uart_data *data = pdev->dev.platform_data;
 798                 data->regs = (void __iomem *)pdev->resource[0].start;
 799         }
 800
 801         pdev->id = line;
 802         at32_usarts[line] = pdev;
 803 }
 804
 805 struct platform_device *__init at32_add_device_usart(unsigned int id)
 806 {
 807         platform_device_register(at32_usarts[id]);
 808         return at32_usarts[id];
 809 }
 810
 811 struct platform_device *atmel_default_console_device;
 812
 813 void __init at32_setup_serial_console(unsigned int usart_id)
 814 {
 815         atmel_default_console_device = at32_usarts[usart_id];
 816 }
 817
 818 /* --------------------------------------------------------------------
 819  *  Ethernet
 820  * -------------------------------------------------------------------- */
 821
 822 #ifdef CONFIG_CPU_AT32AP7000
 823 static struct eth_platform_data macb0_data;
 824 static struct resource macb0_resource[] = {
 825         PBMEM(0xfff01800),
 826         IRQ(25),
 827 };
 828 DEFINE_DEV_DATA(macb, 0);
 829 DEV_CLK(hclk, macb0, hsb, 8);
 830 DEV_CLK(pclk, macb0, pbb, 6);
 831
 832 static struct eth_platform_data macb1_data;
 833 static struct resource macb1_resource[] = {
 834         PBMEM(0xfff01c00),
 835         IRQ(26),
 836 };
 837 DEFINE_DEV_DATA(macb, 1);
 838 DEV_CLK(hclk, macb1, hsb, 9);
 839 DEV_CLK(pclk, macb1, pbb, 7);
 840
 841 struct platform_device *__init
 842 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 843 {
 844         struct platform_device *pdev;
 845
 846         switch (id) {
 847         case 0:
 848                 pdev = &macb0_device;
 849
 850                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 851                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
 852                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
 853                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
 854                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
 855                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
 856                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
 857                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
 858                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
 859                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
 860
 861                 if (!data->is_rmii) {
 862                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
 863                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
 864                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
 865                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
 866                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
 867                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
 868                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
 869                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
 870                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
 871                 }
 872                 break;
 873
 874         case 1:
 875                 pdev = &macb1_device;
 876
 877                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
 878                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
 879                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
 880                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
 881                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
 882                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
 883                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
 884                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
 885                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
 886                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
 887
 888                 if (!data->is_rmii) {
 889                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
 890                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
 891                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
 892                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
 893                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
 894                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
 895                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
 896                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
 897                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
 898                 }
 899                 break;
 900
 901         default:
 902                 return NULL;
 903         }
 904
 905         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
 906         platform_device_register(pdev);
 907
 908         return pdev;
 909 }
 910 #endif
 911
 912 /* --------------------------------------------------------------------
 913  *  SPI
 914  * -------------------------------------------------------------------- */
 915 static struct resource atmel_spi0_resource[] = {
 916         PBMEM(0xffe00000),
 917         IRQ(3),
 918 };
 919 DEFINE_DEV(atmel_spi, 0);
 920 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
 921
 922 static struct resource atmel_spi1_resource[] = {
 923         PBMEM(0xffe00400),
 924         IRQ(4),
 925 };
 926 DEFINE_DEV(atmel_spi, 1);
 927 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
 928
 929 static void __init
 930 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
 931                       unsigned int n, const u8 *pins)
 932 {
 933         unsigned int pin, mode;
 934
 935         for (; n; n--, b++) {
 936                 b->bus_num = bus_num;
 937                 if (b->chip_select >= 4)
 938                         continue;
 939                 pin = (unsigned)b->controller_data;
 940                 if (!pin) {
 941                         pin = pins[b->chip_select];
 942                         b->controller_data = (void *)pin;
 943                 }
 944                 mode = AT32_GPIOF_OUTPUT;
 945                 if (!(b->mode & SPI_CS_HIGH))
 946                         mode |= AT32_GPIOF_HIGH;
 947                 at32_select_gpio(pin, mode);
 948         }
 949 }
 950
 951 struct platform_device *__init
 952 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 953 {
 954         /*
 955          * Manage the chipselects as GPIOs, normally using the same pins
 956          * the SPI controller expects; but boards can use other pins.
 957          */
 958         static u8 __initdata spi0_pins[] =
 959                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
 960                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
 961         static u8 __initdata spi1_pins[] =
 962                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
 963                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
 964         struct platform_device *pdev;
 965
 966         switch (id) {
 967         case 0:
 968                 pdev = &atmel_spi0_device;
 969                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
 970                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
 971                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
 972                 at32_spi_setup_slaves(0, b, n, spi0_pins);
 973                 break;
 974
 975         case 1:
 976                 pdev = &atmel_spi1_device;
 977                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
 978                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
 979                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
 980                 at32_spi_setup_slaves(1, b, n, spi1_pins);
 981                 break;
 982
 983         default:
 984                 return NULL;
 985         }
 986
 987         spi_register_board_info(b, n);
 988         platform_device_register(pdev);
 989         return pdev;
 990 }
 991
 992 /* --------------------------------------------------------------------
 993  *  TWI
 994  * -------------------------------------------------------------------- */
 995 static struct resource atmel_twi0_resource[] __initdata = {
 996         PBMEM(0xffe00800),
 997         IRQ(5),
 998 };
 999 static struct clk atmel_twi0_pclk = {
1000         .name           = "twi_pclk",
1001         .parent         = &pba_clk,
1002         .mode           = pba_clk_mode,
1003         .get_rate       = pba_clk_get_rate,
1004         .index          = 2,
1005 };
1006
1007 struct platform_device *__init at32_add_device_twi(unsigned int id,
1008                                                     struct i2c_board_info *b,
1009                                                     unsigned int n)
1010 {
1011         struct platform_device *pdev;
1012
1013         if (id != 0)
1014                 return NULL;
1015
1016         pdev = platform_device_alloc("atmel_twi", id);
1017         if (!pdev)
1018                 return NULL;
1019
1020         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1021                                 ARRAY_SIZE(atmel_twi0_resource)))
1022                 goto err_add_resources;
1023
1024         select_peripheral(PA(6),  PERIPH_A, 0); /* SDA  */
1025         select_peripheral(PA(7),  PERIPH_A, 0); /* SDL  */
1026
1027         atmel_twi0_pclk.dev = &pdev->dev;
1028
1029         if (b)
1030                 i2c_register_board_info(id, b, n);
1031
1032         platform_device_add(pdev);
1033         return pdev;
1034
1035 err_add_resources:
1036         platform_device_put(pdev);
1037         return NULL;
1038 }
1039
1040 /* --------------------------------------------------------------------
1041  * MMC
1042  * -------------------------------------------------------------------- */
1043 static struct resource atmel_mci0_resource[] __initdata = {
1044         PBMEM(0xfff02400),
1045         IRQ(28),
1046 };
1047 static struct clk atmel_mci0_pclk = {
1048         .name           = "mci_clk",
1049         .parent         = &pbb_clk,
1050         .mode           = pbb_clk_mode,
1051         .get_rate       = pbb_clk_get_rate,
1052         .index          = 9,
1053 };
1054
1055 struct platform_device *__init at32_add_device_mci(unsigned int id)
1056 {
1057         struct platform_device *pdev;
1058
1059         if (id != 0)
1060                 return NULL;
1061
1062         pdev = platform_device_alloc("atmel_mci", id);
1063         if (!pdev)
1064                 return NULL;
1065
1066         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1067                                 ARRAY_SIZE(atmel_mci0_resource)))
1068                 goto err_add_resources;
1069
1070         select_peripheral(PA(10), PERIPH_A, 0); /* CLK   */
1071         select_peripheral(PA(11), PERIPH_A, 0); /* CMD   */
1072         select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1073         select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1074         select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1075         select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1076
1077         atmel_mci0_pclk.dev = &pdev->dev;
1078
1079         platform_device_add(pdev);
1080         return pdev;
1081
1082 err_add_resources:
1083         platform_device_put(pdev);
1084         return NULL;
1085 }
1086
1087 /* --------------------------------------------------------------------
1088  *  LCDC
1089  * -------------------------------------------------------------------- */
1090 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1091 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1092 static struct resource atmel_lcdfb0_resource[] = {
1093         {
1094                 .start          = 0xff000000,
1095                 .end            = 0xff000fff,
1096                 .flags          = IORESOURCE_MEM,
1097         },
1098         IRQ(1),
1099         {
1100                 /* Placeholder for pre-allocated fb memory */
1101                 .start          = 0x00000000,
1102                 .end            = 0x00000000,
1103                 .flags          = 0,
1104         },
1105 };
1106 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1107 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1108 static struct clk atmel_lcdfb0_pixclk = {
1109         .name           = "lcdc_clk",
1110         .dev            = &atmel_lcdfb0_device.dev,
1111         .mode           = genclk_mode,
1112         .get_rate       = genclk_get_rate,
1113         .set_rate       = genclk_set_rate,
1114         .set_parent     = genclk_set_parent,
1115         .index          = 7,
1116 };
1117
1118 struct platform_device *__init
1119 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1120                      unsigned long fbmem_start, unsigned long fbmem_len)
1121 {
1122         struct platform_device *pdev;
1123         struct atmel_lcdfb_info *info;
1124         struct fb_monspecs *monspecs;
1125         struct fb_videomode *modedb;
1126         unsigned int modedb_size;
1127
1128         /*
1129          * Do a deep copy of the fb data, monspecs and modedb. Make
1130          * sure all allocations are done before setting up the
1131          * portmux.
1132          */
1133         monspecs = kmemdup(data->default_monspecs,
1134                            sizeof(struct fb_monspecs), GFP_KERNEL);
1135         if (!monspecs)
1136                 return NULL;
1137
1138         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1139         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1140         if (!modedb)
1141                 goto err_dup_modedb;
1142         monspecs->modedb = modedb;
1143
1144         switch (id) {
1145         case 0:
1146                 pdev = &atmel_lcdfb0_device;
1147                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
1148                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1149                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1150                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1151                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
1152                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
1153                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1154                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
1155                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1156                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1157                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1158                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1159                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1160                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1161                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1162                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1163                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1164                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1165                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1166                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1167                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1168                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1169                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1170                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1171                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1172                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1173                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1174                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1175                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1176                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1177                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1178
1179                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1180                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1181                 break;
1182
1183         default:
1184                 goto err_invalid_id;
1185         }
1186
1187         if (fbmem_len) {
1188                 pdev->resource[2].start = fbmem_start;
1189                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1190                 pdev->resource[2].flags = IORESOURCE_MEM;
1191         }
1192
1193         info = pdev->dev.platform_data;
1194         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1195         info->default_monspecs = monspecs;
1196
1197         platform_device_register(pdev);
1198         return pdev;
1199
1200 err_invalid_id:
1201         kfree(modedb);
1202 err_dup_modedb:
1203         kfree(monspecs);
1204         return NULL;
1205 }
1206 #endif
1207
1208 /* --------------------------------------------------------------------
1209  *  PWM
1210  * -------------------------------------------------------------------- */
1211 static struct resource atmel_pwm0_resource[] __initdata = {
1212         PBMEM(0xfff01400),
1213         IRQ(24),
1214 };
1215 static struct clk atmel_pwm0_mck = {
1216         .name           = "mck",
1217         .parent         = &pbb_clk,
1218         .mode           = pbb_clk_mode,
1219         .get_rate       = pbb_clk_get_rate,
1220         .index          = 5,
1221 };
1222
1223 struct platform_device *__init at32_add_device_pwm(u32 mask)
1224 {
1225         struct platform_device *pdev;
1226
1227         if (!mask)
1228                 return NULL;
1229
1230         pdev = platform_device_alloc("atmel_pwm", 0);
1231         if (!pdev)
1232                 return NULL;
1233
1234         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1235                                 ARRAY_SIZE(atmel_pwm0_resource)))
1236                 goto out_free_pdev;
1237
1238         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1239                 goto out_free_pdev;
1240
1241         if (mask & (1 << 0))
1242                 select_peripheral(PA(28), PERIPH_A, 0);
1243         if (mask & (1 << 1))
1244                 select_peripheral(PA(29), PERIPH_A, 0);
1245         if (mask & (1 << 2))
1246                 select_peripheral(PA(21), PERIPH_B, 0);
1247         if (mask & (1 << 3))
1248                 select_peripheral(PA(22), PERIPH_B, 0);
1249
1250         atmel_pwm0_mck.dev = &pdev->dev;
1251
1252         platform_device_add(pdev);
1253
1254         return pdev;
1255
1256 out_free_pdev:
1257         platform_device_put(pdev);
1258         return NULL;
1259 }
1260
1261 /* --------------------------------------------------------------------
1262  *  SSC
1263  * -------------------------------------------------------------------- */
1264 static struct resource ssc0_resource[] = {
1265         PBMEM(0xffe01c00),
1266         IRQ(10),
1267 };
1268 DEFINE_DEV(ssc, 0);
1269 DEV_CLK(pclk, ssc0, pba, 7);
1270
1271 static struct resource ssc1_resource[] = {
1272         PBMEM(0xffe02000),
1273         IRQ(11),
1274 };
1275 DEFINE_DEV(ssc, 1);
1276 DEV_CLK(pclk, ssc1, pba, 8);
1277
1278 static struct resource ssc2_resource[] = {
1279         PBMEM(0xffe02400),
1280         IRQ(12),
1281 };
1282 DEFINE_DEV(ssc, 2);
1283 DEV_CLK(pclk, ssc2, pba, 9);
1284
1285 struct platform_device *__init
1286 at32_add_device_ssc(unsigned int id, unsigned int flags)
1287 {
1288         struct platform_device *pdev;
1289
1290         switch (id) {
1291         case 0:
1292                 pdev = &ssc0_device;
1293                 if (flags & ATMEL_SSC_RF)
1294                         select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1295                 if (flags & ATMEL_SSC_RK)
1296                         select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1297                 if (flags & ATMEL_SSC_TK)
1298                         select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1299                 if (flags & ATMEL_SSC_TF)
1300                         select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1301                 if (flags & ATMEL_SSC_TD)
1302                         select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1303                 if (flags & ATMEL_SSC_RD)
1304                         select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1305                 break;
1306         case 1:
1307                 pdev = &ssc1_device;
1308                 if (flags & ATMEL_SSC_RF)
1309                         select_peripheral(PA(0), PERIPH_B, 0);  /* RF */
1310                 if (flags & ATMEL_SSC_RK)
1311                         select_peripheral(PA(1), PERIPH_B, 0);  /* RK */
1312                 if (flags & ATMEL_SSC_TK)
1313                         select_peripheral(PA(2), PERIPH_B, 0);  /* TK */
1314                 if (flags & ATMEL_SSC_TF)
1315                         select_peripheral(PA(3), PERIPH_B, 0);  /* TF */
1316                 if (flags & ATMEL_SSC_TD)
1317                         select_peripheral(PA(4), PERIPH_B, 0);  /* TD */
1318                 if (flags & ATMEL_SSC_RD)
1319                         select_peripheral(PA(5), PERIPH_B, 0);  /* RD */
1320                 break;
1321         case 2:
1322                 pdev = &ssc2_device;
1323                 if (flags & ATMEL_SSC_TD)
1324                         select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1325                 if (flags & ATMEL_SSC_RD)
1326                         select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1327                 if (flags & ATMEL_SSC_TK)
1328                         select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1329                 if (flags & ATMEL_SSC_TF)
1330                         select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1331                 if (flags & ATMEL_SSC_RF)
1332                         select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1333                 if (flags & ATMEL_SSC_RK)
1334                         select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1335                 break;
1336         default:
1337                 return NULL;
1338         }
1339
1340         platform_device_register(pdev);
1341         return pdev;
1342 }
1343
1344 /* --------------------------------------------------------------------
1345  *  USB Device Controller
1346  * -------------------------------------------------------------------- */
1347 static struct resource usba0_resource[] __initdata = {
1348         {
1349                 .start          = 0xff300000,
1350                 .end            = 0xff3fffff,
1351                 .flags          = IORESOURCE_MEM,
1352         }, {
1353                 .start          = 0xfff03000,
1354                 .end            = 0xfff033ff,
1355                 .flags          = IORESOURCE_MEM,
1356         },
1357         IRQ(31),
1358 };
1359 static struct clk usba0_pclk = {
1360         .name           = "pclk",
1361         .parent         = &pbb_clk,
1362         .mode           = pbb_clk_mode,
1363         .get_rate       = pbb_clk_get_rate,
1364         .index          = 12,
1365 };
1366 static struct clk usba0_hclk = {
1367         .name           = "hclk",
1368         .parent         = &hsb_clk,
1369         .mode           = hsb_clk_mode,
1370         .get_rate       = hsb_clk_get_rate,
1371         .index          = 6,
1372 };
1373
1374 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1375         [idx] = {                                               \
1376                 .name           = nam,                          \
1377                 .index          = idx,                          \
1378                 .fifo_size      = maxpkt,                       \
1379                 .nr_banks       = maxbk,                        \
1380                 .can_dma        = dma,                          \
1381                 .can_isoc       = isoc,                         \
1382         }
1383
1384 static struct usba_ep_data at32_usba_ep[] __initdata = {
1385         EP("ep0",     0,   64, 1, 0, 0),
1386         EP("ep1",     1,  512, 2, 1, 1),
1387         EP("ep2",     2,  512, 2, 1, 1),
1388         EP("ep3-int", 3,   64, 3, 1, 0),
1389         EP("ep4-int", 4,   64, 3, 1, 0),
1390         EP("ep5",     5, 1024, 3, 1, 1),
1391         EP("ep6",     6, 1024, 3, 1, 1),
1392 };
1393
1394 #undef EP
1395
1396 struct platform_device *__init
1397 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1398 {
1399         /*
1400          * pdata doesn't have room for any endpoints, so we need to
1401          * append room for the ones we need right after it.
1402          */
1403         struct {
1404                 struct usba_platform_data pdata;
1405                 struct usba_ep_data ep[7];
1406         } usba_data;
1407         struct platform_device *pdev;
1408
1409         if (id != 0)
1410                 return NULL;
1411
1412         pdev = platform_device_alloc("atmel_usba_udc", 0);
1413         if (!pdev)
1414                 return NULL;
1415
1416         if (platform_device_add_resources(pdev, usba0_resource,
1417                                           ARRAY_SIZE(usba0_resource)))
1418                 goto out_free_pdev;
1419
1420         if (data)
1421                 usba_data.pdata.vbus_pin = data->vbus_pin;
1422         else
1423                 usba_data.pdata.vbus_pin = -EINVAL;
1424
1425         data = &usba_data.pdata;
1426         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1427         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1428
1429         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1430                 goto out_free_pdev;
1431
1432         if (data->vbus_pin >= 0)
1433                 at32_select_gpio(data->vbus_pin, 0);
1434
1435         usba0_pclk.dev = &pdev->dev;
1436         usba0_hclk.dev = &pdev->dev;
1437
1438         platform_device_add(pdev);
1439
1440         return pdev;
1441
1442 out_free_pdev:
1443         platform_device_put(pdev);
1444         return NULL;
1445 }
1446
1447 /* --------------------------------------------------------------------
1448  * IDE / CompactFlash
1449  * -------------------------------------------------------------------- */
1450 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1451 static struct resource at32_smc_cs4_resource[] __initdata = {
1452         {
1453                 .start  = 0x04000000,
1454                 .end    = 0x07ffffff,
1455                 .flags  = IORESOURCE_MEM,
1456         },
1457         IRQ(~0UL), /* Magic IRQ will be overridden */
1458 };
1459 static struct resource at32_smc_cs5_resource[] __initdata = {
1460         {
1461                 .start  = 0x20000000,
1462                 .end    = 0x23ffffff,
1463                 .flags  = IORESOURCE_MEM,
1464         },
1465         IRQ(~0UL), /* Magic IRQ will be overridden */
1466 };
1467
1468 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1469                 unsigned int cs, unsigned int extint)
1470 {
1471         static unsigned int extint_pin_map[4] __initdata = {
1472                 GPIO_PIN_PB(25),
1473                 GPIO_PIN_PB(26),
1474                 GPIO_PIN_PB(27),
1475                 GPIO_PIN_PB(28),
1476         };
1477         static bool common_pins_initialized __initdata = false;
1478         unsigned int extint_pin;
1479         int ret;
1480
1481         if (extint >= ARRAY_SIZE(extint_pin_map))
1482                 return -EINVAL;
1483         extint_pin = extint_pin_map[extint];
1484
1485         switch (cs) {
1486         case 4:
1487                 ret = platform_device_add_resources(pdev,
1488                                 at32_smc_cs4_resource,
1489                                 ARRAY_SIZE(at32_smc_cs4_resource));
1490                 if (ret)
1491                         return ret;
1492
1493                 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
1494                 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1495                 break;
1496         case 5:
1497                 ret = platform_device_add_resources(pdev,
1498                                 at32_smc_cs5_resource,
1499                                 ARRAY_SIZE(at32_smc_cs5_resource));
1500                 if (ret)
1501                         return ret;
1502
1503                 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
1504                 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1505                 break;
1506         default:
1507                 return -EINVAL;
1508         }
1509
1510         if (!common_pins_initialized) {
1511                 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1  -> CS0_N */
1512                 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2  -> CS1_N */
1513                 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
1514                 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
1515                 common_pins_initialized = true;
1516         }
1517
1518         at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1519
1520         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1521         pdev->resource[1].end = pdev->resource[1].start;
1522
1523         return 0;
1524 }
1525
1526 struct platform_device *__init
1527 at32_add_device_ide(unsigned int id, unsigned int extint,
1528                     struct ide_platform_data *data)
1529 {
1530         struct platform_device *pdev;
1531
1532         pdev = platform_device_alloc("at32_ide", id);
1533         if (!pdev)
1534                 goto fail;
1535
1536         if (platform_device_add_data(pdev, data,
1537                                 sizeof(struct ide_platform_data)))
1538                 goto fail;
1539
1540         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1541                 goto fail;
1542
1543         platform_device_add(pdev);
1544         return pdev;
1545
1546 fail:
1547         platform_device_put(pdev);
1548         return NULL;
1549 }
1550
1551 struct platform_device *__init
1552 at32_add_device_cf(unsigned int id, unsigned int extint,
1553                     struct cf_platform_data *data)
1554 {
1555         struct platform_device *pdev;
1556
1557         pdev = platform_device_alloc("at32_cf", id);
1558         if (!pdev)
1559                 goto fail;
1560
1561         if (platform_device_add_data(pdev, data,
1562                                 sizeof(struct cf_platform_data)))
1563                 goto fail;
1564
1565         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1566                 goto fail;
1567
1568         if (data->detect_pin != GPIO_PIN_NONE)
1569                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1570         if (data->reset_pin != GPIO_PIN_NONE)
1571                 at32_select_gpio(data->reset_pin, 0);
1572         if (data->vcc_pin != GPIO_PIN_NONE)
1573                 at32_select_gpio(data->vcc_pin, 0);
1574         /* READY is used as extint, so we can't select it as gpio */
1575
1576         platform_device_add(pdev);
1577         return pdev;
1578
1579 fail:
1580         platform_device_put(pdev);
1581         return NULL;
1582 }
1583 #endif
1584
1585 /* --------------------------------------------------------------------
1586  * AC97C
1587  * -------------------------------------------------------------------- */
1588 static struct resource atmel_ac97c0_resource[] __initdata = {
1589         PBMEM(0xfff02800),
1590         IRQ(29),
1591 };
1592 static struct clk atmel_ac97c0_pclk = {
1593         .name           = "pclk",
1594         .parent         = &pbb_clk,
1595         .mode           = pbb_clk_mode,
1596         .get_rate       = pbb_clk_get_rate,
1597         .index          = 10,
1598 };
1599
1600 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1601 {
1602         struct platform_device *pdev;
1603
1604         if (id != 0)
1605                 return NULL;
1606
1607         pdev = platform_device_alloc("atmel_ac97c", id);
1608         if (!pdev)
1609                 return NULL;
1610
1611         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1612                                 ARRAY_SIZE(atmel_ac97c0_resource)))
1613                 goto err_add_resources;
1614
1615         select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1616         select_peripheral(PB(21), PERIPH_B, 0); /* SDO  */
1617         select_peripheral(PB(22), PERIPH_B, 0); /* SDI  */
1618         select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1619
1620         atmel_ac97c0_pclk.dev = &pdev->dev;
1621
1622         platform_device_add(pdev);
1623         return pdev;
1624
1625 err_add_resources:
1626         platform_device_put(pdev);
1627         return NULL;
1628 }
1629
1630 /* --------------------------------------------------------------------
1631  * ABDAC
1632  * -------------------------------------------------------------------- */
1633 static struct resource abdac0_resource[] __initdata = {
1634         PBMEM(0xfff02000),
1635         IRQ(27),
1636 };
1637 static struct clk abdac0_pclk = {
1638         .name           = "pclk",
1639         .parent         = &pbb_clk,
1640         .mode           = pbb_clk_mode,
1641         .get_rate       = pbb_clk_get_rate,
1642         .index          = 8,
1643 };
1644 static struct clk abdac0_sample_clk = {
1645         .name           = "sample_clk",
1646         .mode           = genclk_mode,
1647         .get_rate       = genclk_get_rate,
1648         .set_rate       = genclk_set_rate,
1649         .set_parent     = genclk_set_parent,
1650         .index          = 6,
1651 };
1652
1653 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1654 {
1655         struct platform_device *pdev;
1656
1657         if (id != 0)
1658                 return NULL;
1659
1660         pdev = platform_device_alloc("abdac", id);
1661         if (!pdev)
1662                 return NULL;
1663
1664         if (platform_device_add_resources(pdev, abdac0_resource,
1665                                 ARRAY_SIZE(abdac0_resource)))
1666                 goto err_add_resources;
1667
1668         select_peripheral(PB(20), PERIPH_A, 0); /* DATA1        */
1669         select_peripheral(PB(21), PERIPH_A, 0); /* DATA0        */
1670         select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1       */
1671         select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0       */
1672
1673         abdac0_pclk.dev = &pdev->dev;
1674         abdac0_sample_clk.dev = &pdev->dev;
1675
1676         platform_device_add(pdev);
1677         return pdev;
1678
1679 err_add_resources:
1680         platform_device_put(pdev);
1681         return NULL;
1682 }
1683
1684 /* --------------------------------------------------------------------
1685  *  GCLK
1686  * -------------------------------------------------------------------- */
1687 static struct clk gclk0 = {
1688         .name           = "gclk0",
1689         .mode           = genclk_mode,
1690         .get_rate       = genclk_get_rate,
1691         .set_rate       = genclk_set_rate,
1692         .set_parent     = genclk_set_parent,
1693         .index          = 0,
1694 };
1695 static struct clk gclk1 = {
1696         .name           = "gclk1",
1697         .mode           = genclk_mode,
1698         .get_rate       = genclk_get_rate,
1699         .set_rate       = genclk_set_rate,
1700         .set_parent     = genclk_set_parent,
1701         .index          = 1,
1702 };
1703 static struct clk gclk2 = {
1704         .name           = "gclk2",
1705         .mode           = genclk_mode,
1706         .get_rate       = genclk_get_rate,
1707         .set_rate       = genclk_set_rate,
1708         .set_parent     = genclk_set_parent,
1709         .index          = 2,
1710 };
1711 static struct clk gclk3 = {
1712         .name           = "gclk3",
1713         .mode           = genclk_mode,
1714         .get_rate       = genclk_get_rate,
1715         .set_rate       = genclk_set_rate,
1716         .set_parent     = genclk_set_parent,
1717         .index          = 3,
1718 };
1719 static struct clk gclk4 = {
1720         .name           = "gclk4",
1721         .mode           = genclk_mode,
1722         .get_rate       = genclk_get_rate,
1723         .set_rate       = genclk_set_rate,
1724         .set_parent     = genclk_set_parent,
1725         .index          = 4,
1726 };
1727
1728 struct clk *at32_clock_list[] = {
1729         &osc32k,
1730         &osc0,
1731         &osc1,
1732         &pll0,
1733         &pll1,
1734         &cpu_clk,
1735         &hsb_clk,
1736         &pba_clk,
1737         &pbb_clk,
1738         &at32_pm_pclk,
1739         &at32_intc0_pclk,
1740         &hmatrix_clk,
1741         &ebi_clk,
1742         &hramc_clk,
1743         &smc0_pclk,
1744         &smc0_mck,
1745         &pdc_hclk,
1746         &pdc_pclk,
1747         &dmaca0_hclk,
1748         &pico_clk,
1749         &pio0_mck,
1750         &pio1_mck,
1751         &pio2_mck,
1752         &pio3_mck,
1753         &pio4_mck,
1754         &at32_tcb0_t0_clk,
1755         &at32_tcb1_t0_clk,
1756         &atmel_usart0_usart,
1757         &atmel_usart1_usart,
1758         &atmel_usart2_usart,
1759         &atmel_usart3_usart,
1760         &atmel_pwm0_mck,
1761 #if defined(CONFIG_CPU_AT32AP7000)
1762         &macb0_hclk,
1763         &macb0_pclk,
1764         &macb1_hclk,
1765         &macb1_pclk,
1766 #endif
1767         &atmel_spi0_spi_clk,
1768         &atmel_spi1_spi_clk,
1769         &atmel_twi0_pclk,
1770         &atmel_mci0_pclk,
1771 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1772         &atmel_lcdfb0_hck1,
1773         &atmel_lcdfb0_pixclk,
1774 #endif
1775         &ssc0_pclk,
1776         &ssc1_pclk,
1777         &ssc2_pclk,
1778         &usba0_hclk,
1779         &usba0_pclk,
1780         &atmel_ac97c0_pclk,
1781         &abdac0_pclk,
1782         &abdac0_sample_clk,
1783         &gclk0,
1784         &gclk1,
1785         &gclk2,
1786         &gclk3,
1787         &gclk4,
1788 };
1789 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1790
1791 void __init at32_portmux_init(void)
1792 {
1793         at32_init_pio(&pio0_device);
1794         at32_init_pio(&pio1_device);
1795         at32_init_pio(&pio2_device);
1796         at32_init_pio(&pio3_device);
1797         at32_init_pio(&pio4_device);
1798 }
1799
1800 void __init at32_clock_init(void)
1801 {
1802         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1803         int i;
1804
1805         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
1806                 main_clock = &pll0;
1807                 cpu_clk.parent = &pll0;
1808         } else {
1809                 main_clock = &osc0;
1810                 cpu_clk.parent = &osc0;
1811         }
1812
1813         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1814                 pll0.parent = &osc1;
1815         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1816                 pll1.parent = &osc1;
1817
1818         genclk_init_parent(&gclk0);
1819         genclk_init_parent(&gclk1);
1820         genclk_init_parent(&gclk2);
1821         genclk_init_parent(&gclk3);
1822         genclk_init_parent(&gclk4);
1823 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1824         genclk_init_parent(&atmel_lcdfb0_pixclk);
1825 #endif
1826         genclk_init_parent(&abdac0_sample_clk);
1827
1828         /*
1829          * Turn on all clocks that have at least one user already, and
1830          * turn off everything else. We only do this for module
1831          * clocks, and even though it isn't particularly pretty to
1832          * check the address of the mode function, it should do the
1833          * trick...
1834          */
1835         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1836                 struct clk *clk = at32_clock_list[i];
1837
1838                 if (clk->users == 0)
1839                         continue;
1840
1841                 if (clk->mode == &cpu_clk_mode)
1842                         cpu_mask |= 1 << clk->index;
1843                 else if (clk->mode == &hsb_clk_mode)
1844                         hsb_mask |= 1 << clk->index;
1845                 else if (clk->mode == &pba_clk_mode)
1846                         pba_mask |= 1 << clk->index;
1847                 else if (clk->mode == &pbb_clk_mode)
1848                         pbb_mask |= 1 << clk->index;
1849         }
1850
1851         pm_writel(CPU_MASK, cpu_mask);
1852         pm_writel(HSB_MASK, hsb_mask);
1853         pm_writel(PBA_MASK, pba_mask);
1854         pm_writel(PBB_MASK, pbb_mask);
1855 }