2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/delay.h>
10 #include <linux/platform_data/dma-dw.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/gpio.h>
17 #include <linux/spi/spi.h>
18 #include <linux/usb/atmel_usba_udc.h>
20 #include <linux/platform_data/mmc-atmel-mci.h>
21 #include <linux/atmel-mci.h>
26 #include <mach/at32ap700x.h>
27 #include <mach/board.h>
28 #include <mach/hmatrix.h>
29 #include <mach/portmux.h>
30 #include <mach/sram.h>
32 #include <sound/atmel-abdac.h>
33 #include <sound/atmel-ac97c.h>
35 #include <video/atmel_lcdc.h>
45 .end = base + 0x3ff, \
46 .flags = IORESOURCE_MEM, \
52 .flags = IORESOURCE_IRQ, \
54 #define NAMED_IRQ(num, _name) \
59 .flags = IORESOURCE_IRQ, \
62 /* REVISIT these assume *every* device supports DMA, but several
63 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
65 #define DEFINE_DEV(_name, _id) \
66 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
67 static struct platform_device _name##_id##_device = { \
71 .dma_mask = &_name##_id##_dma_mask, \
72 .coherent_dma_mask = DMA_BIT_MASK(32), \
74 .resource = _name##_id##_resource, \
75 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
77 #define DEFINE_DEV_DATA(_name, _id) \
78 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
79 static struct platform_device _name##_id##_device = { \
83 .dma_mask = &_name##_id##_dma_mask, \
84 .platform_data = &_name##_id##_data, \
85 .coherent_dma_mask = DMA_BIT_MASK(32), \
87 .resource = _name##_id##_resource, \
88 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
91 #define select_peripheral(port, pin_mask, periph, flags) \
92 at32_select_periph(GPIO_##port##_BASE, pin_mask, \
95 #define DEV_CLK(_name, devname, bus, _index) \
96 static struct clk devname##_##_name = { \
98 .dev = &devname##_device.dev, \
99 .parent = &bus##_clk, \
100 .mode = bus##_clk_mode, \
101 .get_rate = bus##_clk_get_rate, \
105 static DEFINE_SPINLOCK(pm_lock);
107 static struct clk osc0;
108 static struct clk osc1;
110 static unsigned long osc_get_rate(struct clk *clk)
112 return at32_board_osc_rates[clk->index];
115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
117 unsigned long div, mul, rate;
119 div = PM_BFEXT(PLLDIV, control) + 1;
120 mul = PM_BFEXT(PLLMUL, control) + 1;
122 rate = clk->parent->get_rate(clk->parent);
123 rate = (rate + div / 2) / div;
129 static long pll_set_rate(struct clk *clk, unsigned long rate,
133 unsigned long mul_best_fit = 0;
135 unsigned long div_min;
136 unsigned long div_max;
137 unsigned long div_best_fit = 0;
139 unsigned long pll_in;
140 unsigned long actual = 0;
141 unsigned long rate_error;
142 unsigned long rate_error_prev = ~0UL;
145 /* Rate must be between 80 MHz and 200 Mhz. */
146 if (rate < 80000000UL || rate > 200000000UL)
149 ctrl = PM_BF(PLLOPT, 4);
150 base = clk->parent->get_rate(clk->parent);
152 /* PLL input frequency must be between 6 MHz and 32 MHz. */
153 div_min = DIV_ROUND_UP(base, 32000000UL);
154 div_max = base / 6000000UL;
156 if (div_max < div_min)
159 for (div = div_min; div <= div_max; div++) {
160 pll_in = (base + div / 2) / div;
161 mul = (rate + pll_in / 2) / pll_in;
166 actual = pll_in * mul;
167 rate_error = abs(actual - rate);
169 if (rate_error < rate_error_prev) {
172 rate_error_prev = rate_error;
179 if (div_best_fit == 0)
182 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
183 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
184 ctrl |= PM_BF(PLLCOUNT, 16);
186 if (clk->parent == &osc1)
187 ctrl |= PM_BIT(PLLOSC);
194 static unsigned long pll0_get_rate(struct clk *clk)
198 control = pm_readl(PLL0);
200 return pll_get_rate(clk, control);
203 static void pll1_mode(struct clk *clk, int enabled)
205 unsigned long timeout;
209 ctrl = pm_readl(PLL1);
212 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
213 pr_debug("clk %s: failed to enable, rate not set\n",
218 ctrl |= PM_BIT(PLLEN);
219 pm_writel(PLL1, ctrl);
221 /* Wait for PLL lock. */
222 for (timeout = 10000; timeout; timeout--) {
223 status = pm_readl(ISR);
224 if (status & PM_BIT(LOCK1))
229 if (!(status & PM_BIT(LOCK1)))
230 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
233 ctrl &= ~PM_BIT(PLLEN);
234 pm_writel(PLL1, ctrl);
238 static unsigned long pll1_get_rate(struct clk *clk)
242 control = pm_readl(PLL1);
244 return pll_get_rate(clk, control);
247 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
250 unsigned long actual_rate;
252 actual_rate = pll_set_rate(clk, rate, &ctrl);
255 if (actual_rate != rate)
259 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
260 clk->name, rate, actual_rate);
261 pm_writel(PLL1, ctrl);
267 static int pll1_set_parent(struct clk *clk, struct clk *parent)
274 ctrl = pm_readl(PLL1);
275 WARN_ON(ctrl & PM_BIT(PLLEN));
278 ctrl &= ~PM_BIT(PLLOSC);
279 else if (parent == &osc1)
280 ctrl |= PM_BIT(PLLOSC);
284 pm_writel(PLL1, ctrl);
285 clk->parent = parent;
291 * The AT32AP7000 has five primary clock sources: One 32kHz
292 * oscillator, two crystal oscillators and two PLLs.
294 static struct clk osc32k = {
296 .get_rate = osc_get_rate,
300 static struct clk osc0 = {
302 .get_rate = osc_get_rate,
306 static struct clk osc1 = {
308 .get_rate = osc_get_rate,
311 static struct clk pll0 = {
313 .get_rate = pll0_get_rate,
316 static struct clk pll1 = {
319 .get_rate = pll1_get_rate,
320 .set_rate = pll1_set_rate,
321 .set_parent = pll1_set_parent,
326 * The main clock can be either osc0 or pll0. The boot loader may
327 * have chosen one for us, so we don't really know which one until we
328 * have a look at the SM.
330 static struct clk *main_clock;
333 * Synchronous clocks are generated from the main clock. The clocks
334 * must satisfy the constraint
335 * fCPU >= fHSB >= fPB
336 * i.e. each clock must not be faster than its parent.
338 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
340 return main_clock->get_rate(main_clock) >> shift;
343 static void cpu_clk_mode(struct clk *clk, int enabled)
348 spin_lock_irqsave(&pm_lock, flags);
349 mask = pm_readl(CPU_MASK);
351 mask |= 1 << clk->index;
353 mask &= ~(1 << clk->index);
354 pm_writel(CPU_MASK, mask);
355 spin_unlock_irqrestore(&pm_lock, flags);
358 static unsigned long cpu_clk_get_rate(struct clk *clk)
360 unsigned long cksel, shift = 0;
362 cksel = pm_readl(CKSEL);
363 if (cksel & PM_BIT(CPUDIV))
364 shift = PM_BFEXT(CPUSEL, cksel) + 1;
366 return bus_clk_get_rate(clk, shift);
369 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
372 unsigned long parent_rate, child_div, actual_rate, div;
374 parent_rate = clk->parent->get_rate(clk->parent);
375 control = pm_readl(CKSEL);
377 if (control & PM_BIT(HSBDIV))
378 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
382 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
383 actual_rate = parent_rate;
384 control &= ~PM_BIT(CPUDIV);
387 div = (parent_rate + rate / 2) / rate;
390 cpusel = (div > 1) ? (fls(div) - 2) : 0;
391 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
392 actual_rate = parent_rate / (1 << (cpusel + 1));
395 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
396 clk->name, rate, actual_rate);
399 pm_writel(CKSEL, control);
404 static void hsb_clk_mode(struct clk *clk, int enabled)
409 spin_lock_irqsave(&pm_lock, flags);
410 mask = pm_readl(HSB_MASK);
412 mask |= 1 << clk->index;
414 mask &= ~(1 << clk->index);
415 pm_writel(HSB_MASK, mask);
416 spin_unlock_irqrestore(&pm_lock, flags);
419 static unsigned long hsb_clk_get_rate(struct clk *clk)
421 unsigned long cksel, shift = 0;
423 cksel = pm_readl(CKSEL);
424 if (cksel & PM_BIT(HSBDIV))
425 shift = PM_BFEXT(HSBSEL, cksel) + 1;
427 return bus_clk_get_rate(clk, shift);
430 void pba_clk_mode(struct clk *clk, int enabled)
435 spin_lock_irqsave(&pm_lock, flags);
436 mask = pm_readl(PBA_MASK);
438 mask |= 1 << clk->index;
440 mask &= ~(1 << clk->index);
441 pm_writel(PBA_MASK, mask);
442 spin_unlock_irqrestore(&pm_lock, flags);
445 unsigned long pba_clk_get_rate(struct clk *clk)
447 unsigned long cksel, shift = 0;
449 cksel = pm_readl(CKSEL);
450 if (cksel & PM_BIT(PBADIV))
451 shift = PM_BFEXT(PBASEL, cksel) + 1;
453 return bus_clk_get_rate(clk, shift);
456 static void pbb_clk_mode(struct clk *clk, int enabled)
461 spin_lock_irqsave(&pm_lock, flags);
462 mask = pm_readl(PBB_MASK);
464 mask |= 1 << clk->index;
466 mask &= ~(1 << clk->index);
467 pm_writel(PBB_MASK, mask);
468 spin_unlock_irqrestore(&pm_lock, flags);
471 static unsigned long pbb_clk_get_rate(struct clk *clk)
473 unsigned long cksel, shift = 0;
475 cksel = pm_readl(CKSEL);
476 if (cksel & PM_BIT(PBBDIV))
477 shift = PM_BFEXT(PBBSEL, cksel) + 1;
479 return bus_clk_get_rate(clk, shift);
482 static struct clk cpu_clk = {
484 .get_rate = cpu_clk_get_rate,
485 .set_rate = cpu_clk_set_rate,
488 static struct clk hsb_clk = {
491 .get_rate = hsb_clk_get_rate,
493 static struct clk pba_clk = {
496 .mode = hsb_clk_mode,
497 .get_rate = pba_clk_get_rate,
500 static struct clk pbb_clk = {
503 .mode = hsb_clk_mode,
504 .get_rate = pbb_clk_get_rate,
509 /* --------------------------------------------------------------------
510 * Generic Clock operations
511 * -------------------------------------------------------------------- */
513 static void genclk_mode(struct clk *clk, int enabled)
517 control = pm_readl(GCCTRL(clk->index));
519 control |= PM_BIT(CEN);
521 control &= ~PM_BIT(CEN);
522 pm_writel(GCCTRL(clk->index), control);
525 static unsigned long genclk_get_rate(struct clk *clk)
528 unsigned long div = 1;
530 control = pm_readl(GCCTRL(clk->index));
531 if (control & PM_BIT(DIVEN))
532 div = 2 * (PM_BFEXT(DIV, control) + 1);
534 return clk->parent->get_rate(clk->parent) / div;
537 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
540 unsigned long parent_rate, actual_rate, div;
542 parent_rate = clk->parent->get_rate(clk->parent);
543 control = pm_readl(GCCTRL(clk->index));
545 if (rate > 3 * parent_rate / 4) {
546 actual_rate = parent_rate;
547 control &= ~PM_BIT(DIVEN);
549 div = (parent_rate + rate) / (2 * rate) - 1;
550 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
551 actual_rate = parent_rate / (2 * (div + 1));
554 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
555 clk->name, rate, actual_rate);
558 pm_writel(GCCTRL(clk->index), control);
563 int genclk_set_parent(struct clk *clk, struct clk *parent)
567 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
568 clk->name, parent->name, clk->parent->name);
570 control = pm_readl(GCCTRL(clk->index));
572 if (parent == &osc1 || parent == &pll1)
573 control |= PM_BIT(OSCSEL);
574 else if (parent == &osc0 || parent == &pll0)
575 control &= ~PM_BIT(OSCSEL);
579 if (parent == &pll0 || parent == &pll1)
580 control |= PM_BIT(PLLSEL);
582 control &= ~PM_BIT(PLLSEL);
584 pm_writel(GCCTRL(clk->index), control);
585 clk->parent = parent;
590 static void __init genclk_init_parent(struct clk *clk)
595 BUG_ON(clk->index > 7);
597 control = pm_readl(GCCTRL(clk->index));
598 if (control & PM_BIT(OSCSEL))
599 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
601 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
603 clk->parent = parent;
606 static struct resource dw_dmac0_resource[] = {
610 DEFINE_DEV(dw_dmac, 0);
611 DEV_CLK(hclk, dw_dmac0, hsb, 10);
613 /* --------------------------------------------------------------------
615 * -------------------------------------------------------------------- */
616 static struct resource at32_pm0_resource[] = {
620 .flags = IORESOURCE_MEM,
625 static struct resource at32ap700x_rtc0_resource[] = {
629 .flags = IORESOURCE_MEM,
634 static struct resource at32_wdt0_resource[] = {
638 .flags = IORESOURCE_MEM,
642 static struct resource at32_eic0_resource[] = {
646 .flags = IORESOURCE_MEM,
651 DEFINE_DEV(at32_pm, 0);
652 DEFINE_DEV(at32ap700x_rtc, 0);
653 DEFINE_DEV(at32_wdt, 0);
654 DEFINE_DEV(at32_eic, 0);
657 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
660 static struct clk at32_pm_pclk = {
662 .dev = &at32_pm0_device.dev,
664 .mode = pbb_clk_mode,
665 .get_rate = pbb_clk_get_rate,
670 static struct resource intc0_resource[] = {
673 struct platform_device at32_intc0_device = {
676 .resource = intc0_resource,
677 .num_resources = ARRAY_SIZE(intc0_resource),
679 DEV_CLK(pclk, at32_intc0, pbb, 1);
681 static struct clk ebi_clk = {
684 .mode = hsb_clk_mode,
685 .get_rate = hsb_clk_get_rate,
688 static struct clk hramc_clk = {
691 .mode = hsb_clk_mode,
692 .get_rate = hsb_clk_get_rate,
696 static struct clk sdramc_clk = {
697 .name = "sdramc_clk",
699 .mode = pbb_clk_mode,
700 .get_rate = pbb_clk_get_rate,
705 static struct resource smc0_resource[] = {
709 DEV_CLK(pclk, smc0, pbb, 13);
710 DEV_CLK(mck, smc0, hsb, 0);
712 static struct platform_device pdc_device = {
716 DEV_CLK(hclk, pdc, hsb, 4);
717 DEV_CLK(pclk, pdc, pba, 16);
719 static struct clk pico_clk = {
722 .mode = cpu_clk_mode,
723 .get_rate = cpu_clk_get_rate,
727 /* --------------------------------------------------------------------
729 * -------------------------------------------------------------------- */
731 struct clk at32_hmatrix_clk = {
732 .name = "hmatrix_clk",
734 .mode = pbb_clk_mode,
735 .get_rate = pbb_clk_get_rate,
741 * Set bits in the HMATRIX Special Function Register (SFR) used by the
742 * External Bus Interface (EBI). This can be used to enable special
743 * features like CompactFlash support, NAND Flash support, etc. on
744 * certain chipselects.
746 static inline void set_ebi_sfr_bits(u32 mask)
748 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
751 /* --------------------------------------------------------------------
753 * -------------------------------------------------------------------- */
755 static struct resource at32_tcb0_resource[] = {
759 static struct platform_device at32_tcb0_device = {
762 .resource = at32_tcb0_resource,
763 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
765 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
767 static struct resource at32_tcb1_resource[] = {
771 static struct platform_device at32_tcb1_device = {
774 .resource = at32_tcb1_resource,
775 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
777 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
779 /* --------------------------------------------------------------------
781 * -------------------------------------------------------------------- */
783 static struct resource pio0_resource[] = {
788 DEV_CLK(mck, pio0, pba, 10);
790 static struct resource pio1_resource[] = {
795 DEV_CLK(mck, pio1, pba, 11);
797 static struct resource pio2_resource[] = {
802 DEV_CLK(mck, pio2, pba, 12);
804 static struct resource pio3_resource[] = {
809 DEV_CLK(mck, pio3, pba, 13);
811 static struct resource pio4_resource[] = {
816 DEV_CLK(mck, pio4, pba, 14);
818 static int __init system_device_init(void)
820 platform_device_register(&at32_pm0_device);
821 platform_device_register(&at32_intc0_device);
822 platform_device_register(&at32ap700x_rtc0_device);
823 platform_device_register(&at32_wdt0_device);
824 platform_device_register(&at32_eic0_device);
825 platform_device_register(&smc0_device);
826 platform_device_register(&pdc_device);
827 platform_device_register(&dw_dmac0_device);
829 platform_device_register(&at32_tcb0_device);
830 platform_device_register(&at32_tcb1_device);
832 platform_device_register(&pio0_device);
833 platform_device_register(&pio1_device);
834 platform_device_register(&pio2_device);
835 platform_device_register(&pio3_device);
836 platform_device_register(&pio4_device);
840 core_initcall(system_device_init);
842 /* --------------------------------------------------------------------
844 * -------------------------------------------------------------------- */
845 static struct resource atmel_psif0_resource[] __initdata = {
849 .flags = IORESOURCE_MEM,
853 static struct clk atmel_psif0_pclk = {
856 .mode = pba_clk_mode,
857 .get_rate = pba_clk_get_rate,
861 static struct resource atmel_psif1_resource[] __initdata = {
865 .flags = IORESOURCE_MEM,
869 static struct clk atmel_psif1_pclk = {
872 .mode = pba_clk_mode,
873 .get_rate = pba_clk_get_rate,
877 struct platform_device *__init at32_add_device_psif(unsigned int id)
879 struct platform_device *pdev;
882 if (!(id == 0 || id == 1))
885 pdev = platform_device_alloc("atmel_psif", id);
891 pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */
893 if (platform_device_add_resources(pdev, atmel_psif0_resource,
894 ARRAY_SIZE(atmel_psif0_resource)))
895 goto err_add_resources;
896 atmel_psif0_pclk.dev = &pdev->dev;
897 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
900 pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */
902 if (platform_device_add_resources(pdev, atmel_psif1_resource,
903 ARRAY_SIZE(atmel_psif1_resource)))
904 goto err_add_resources;
905 atmel_psif1_pclk.dev = &pdev->dev;
906 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
912 platform_device_add(pdev);
916 platform_device_put(pdev);
920 /* --------------------------------------------------------------------
922 * -------------------------------------------------------------------- */
924 static struct atmel_uart_data atmel_usart0_data = {
928 static struct resource atmel_usart0_resource[] = {
932 DEFINE_DEV_DATA(atmel_usart, 0);
933 DEV_CLK(usart, atmel_usart0, pba, 3);
935 static struct atmel_uart_data atmel_usart1_data = {
939 static struct resource atmel_usart1_resource[] = {
943 DEFINE_DEV_DATA(atmel_usart, 1);
944 DEV_CLK(usart, atmel_usart1, pba, 4);
946 static struct atmel_uart_data atmel_usart2_data = {
950 static struct resource atmel_usart2_resource[] = {
954 DEFINE_DEV_DATA(atmel_usart, 2);
955 DEV_CLK(usart, atmel_usart2, pba, 5);
957 static struct atmel_uart_data atmel_usart3_data = {
961 static struct resource atmel_usart3_resource[] = {
965 DEFINE_DEV_DATA(atmel_usart, 3);
966 DEV_CLK(usart, atmel_usart3, pba, 6);
968 static inline void configure_usart0_pins(int flags)
970 u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
971 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6);
972 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7);
973 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10);
975 select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
978 static inline void configure_usart1_pins(int flags)
980 u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
981 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19);
982 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20);
983 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16);
985 select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
988 static inline void configure_usart2_pins(int flags)
990 u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
991 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30);
992 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29);
993 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28);
995 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
998 static inline void configure_usart3_pins(int flags)
1000 u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1001 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16);
1002 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15);
1003 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19);
1005 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1008 static struct platform_device *__initdata at32_usarts[4];
1010 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1012 struct platform_device *pdev;
1013 struct atmel_uart_data *pdata;
1017 pdev = &atmel_usart0_device;
1018 configure_usart0_pins(flags);
1021 pdev = &atmel_usart1_device;
1022 configure_usart1_pins(flags);
1025 pdev = &atmel_usart2_device;
1026 configure_usart2_pins(flags);
1029 pdev = &atmel_usart3_device;
1030 configure_usart3_pins(flags);
1036 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1037 /* Addresses in the P4 segment are permanently mapped 1:1 */
1038 struct atmel_uart_data *data = pdev->dev.platform_data;
1039 data->regs = (void __iomem *)pdev->resource[0].start;
1043 pdata = pdev->dev.platform_data;
1045 at32_usarts[line] = pdev;
1048 struct platform_device *__init at32_add_device_usart(unsigned int id)
1050 platform_device_register(at32_usarts[id]);
1051 return at32_usarts[id];
1054 void __init at32_setup_serial_console(unsigned int usart_id)
1056 #ifdef CONFIG_SERIAL_ATMEL
1057 atmel_default_console_device = at32_usarts[usart_id];
1061 /* --------------------------------------------------------------------
1063 * -------------------------------------------------------------------- */
1065 #ifdef CONFIG_CPU_AT32AP7000
1066 static struct macb_platform_data macb0_data;
1067 static struct resource macb0_resource[] = {
1071 DEFINE_DEV_DATA(macb, 0);
1072 DEV_CLK(hclk, macb0, hsb, 8);
1073 DEV_CLK(pclk, macb0, pbb, 6);
1075 static struct macb_platform_data macb1_data;
1076 static struct resource macb1_resource[] = {
1080 DEFINE_DEV_DATA(macb, 1);
1081 DEV_CLK(hclk, macb1, hsb, 9);
1082 DEV_CLK(pclk, macb1, pbb, 7);
1084 struct platform_device *__init
1085 at32_add_device_eth(unsigned int id, struct macb_platform_data *data)
1087 struct platform_device *pdev;
1092 pdev = &macb0_device;
1094 pin_mask = (1 << 3); /* TXD0 */
1095 pin_mask |= (1 << 4); /* TXD1 */
1096 pin_mask |= (1 << 7); /* TXEN */
1097 pin_mask |= (1 << 8); /* TXCK */
1098 pin_mask |= (1 << 9); /* RXD0 */
1099 pin_mask |= (1 << 10); /* RXD1 */
1100 pin_mask |= (1 << 13); /* RXER */
1101 pin_mask |= (1 << 15); /* RXDV */
1102 pin_mask |= (1 << 16); /* MDC */
1103 pin_mask |= (1 << 17); /* MDIO */
1105 if (!data->is_rmii) {
1106 pin_mask |= (1 << 0); /* COL */
1107 pin_mask |= (1 << 1); /* CRS */
1108 pin_mask |= (1 << 2); /* TXER */
1109 pin_mask |= (1 << 5); /* TXD2 */
1110 pin_mask |= (1 << 6); /* TXD3 */
1111 pin_mask |= (1 << 11); /* RXD2 */
1112 pin_mask |= (1 << 12); /* RXD3 */
1113 pin_mask |= (1 << 14); /* RXCK */
1114 #ifndef CONFIG_BOARD_MIMC200
1115 pin_mask |= (1 << 18); /* SPD */
1119 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1124 pdev = &macb1_device;
1126 pin_mask = (1 << 13); /* TXD0 */
1127 pin_mask |= (1 << 14); /* TXD1 */
1128 pin_mask |= (1 << 11); /* TXEN */
1129 pin_mask |= (1 << 12); /* TXCK */
1130 pin_mask |= (1 << 10); /* RXD0 */
1131 pin_mask |= (1 << 6); /* RXD1 */
1132 pin_mask |= (1 << 5); /* RXER */
1133 pin_mask |= (1 << 4); /* RXDV */
1134 pin_mask |= (1 << 3); /* MDC */
1135 pin_mask |= (1 << 2); /* MDIO */
1137 #ifndef CONFIG_BOARD_MIMC200
1139 pin_mask |= (1 << 15); /* SPD */
1142 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1144 if (!data->is_rmii) {
1145 pin_mask = (1 << 19); /* COL */
1146 pin_mask |= (1 << 23); /* CRS */
1147 pin_mask |= (1 << 26); /* TXER */
1148 pin_mask |= (1 << 27); /* TXD2 */
1149 pin_mask |= (1 << 28); /* TXD3 */
1150 pin_mask |= (1 << 29); /* RXD2 */
1151 pin_mask |= (1 << 30); /* RXD3 */
1152 pin_mask |= (1 << 24); /* RXCK */
1154 select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1162 memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data));
1163 platform_device_register(pdev);
1169 /* --------------------------------------------------------------------
1171 * -------------------------------------------------------------------- */
1172 static struct resource atmel_spi0_resource[] = {
1176 DEFINE_DEV(atmel_spi, 0);
1177 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1179 static struct resource atmel_spi1_resource[] = {
1183 DEFINE_DEV(atmel_spi, 1);
1184 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1187 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1190 * Manage the chipselects as GPIOs, normally using the same pins
1191 * the SPI controller expects; but boards can use other pins.
1193 static u8 __initdata spi_pins[][4] = {
1194 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1195 GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1196 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1197 GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1199 unsigned int pin, mode;
1201 /* There are only 2 SPI controllers */
1205 for (; n; n--, b++) {
1206 b->bus_num = bus_num;
1207 if (b->chip_select >= 4)
1209 pin = (unsigned)b->controller_data;
1211 pin = spi_pins[bus_num][b->chip_select];
1212 b->controller_data = (void *)pin;
1214 mode = AT32_GPIOF_OUTPUT;
1215 if (!(b->mode & SPI_CS_HIGH))
1216 mode |= AT32_GPIOF_HIGH;
1217 at32_select_gpio(pin, mode);
1221 struct platform_device *__init
1222 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1224 struct platform_device *pdev;
1229 pdev = &atmel_spi0_device;
1230 pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */
1232 /* pullup MISO so a level is always defined */
1233 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1234 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1236 at32_spi_setup_slaves(0, b, n);
1240 pdev = &atmel_spi1_device;
1241 pin_mask = (1 << 1) | (1 << 5); /* MOSI */
1243 /* pullup MISO so a level is always defined */
1244 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1245 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1247 at32_spi_setup_slaves(1, b, n);
1254 spi_register_board_info(b, n);
1255 platform_device_register(pdev);
1259 /* --------------------------------------------------------------------
1261 * -------------------------------------------------------------------- */
1262 static struct resource atmel_twi0_resource[] __initdata = {
1266 static struct clk atmel_twi0_pclk = {
1269 .mode = pba_clk_mode,
1270 .get_rate = pba_clk_get_rate,
1274 struct platform_device *__init at32_add_device_twi(unsigned int id,
1275 struct i2c_board_info *b,
1278 struct platform_device *pdev;
1284 pdev = platform_device_alloc("atmel_twi", id);
1288 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1289 ARRAY_SIZE(atmel_twi0_resource)))
1290 goto err_add_resources;
1292 pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */
1294 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1296 atmel_twi0_pclk.dev = &pdev->dev;
1299 i2c_register_board_info(id, b, n);
1301 platform_device_add(pdev);
1305 platform_device_put(pdev);
1309 /* --------------------------------------------------------------------
1311 * -------------------------------------------------------------------- */
1312 static struct resource atmel_mci0_resource[] __initdata = {
1316 static struct clk atmel_mci0_pclk = {
1319 .mode = pbb_clk_mode,
1320 .get_rate = pbb_clk_get_rate,
1324 struct platform_device *__init
1325 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1327 struct platform_device *pdev;
1328 struct mci_dma_data *slave;
1332 if (id != 0 || !data)
1335 /* Must have at least one usable slot */
1336 if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1339 pdev = platform_device_alloc("atmel_mci", id);
1343 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1344 ARRAY_SIZE(atmel_mci0_resource)))
1347 slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
1351 slave->sdata.dma_dev = &dw_dmac0_device.dev;
1352 slave->sdata.src_id = 0;
1353 slave->sdata.dst_id = 1;
1354 slave->sdata.src_master = 1;
1355 slave->sdata.dst_master = 0;
1357 data->dma_slave = slave;
1359 if (platform_device_add_data(pdev, data,
1360 sizeof(struct mci_platform_data)))
1363 /* CLK line is common to both slots */
1364 pioa_mask = 1 << 10;
1366 switch (data->slot[0].bus_width) {
1368 pioa_mask |= 1 << 13; /* DATA1 */
1369 pioa_mask |= 1 << 14; /* DATA2 */
1370 pioa_mask |= 1 << 15; /* DATA3 */
1373 pioa_mask |= 1 << 11; /* CMD */
1374 pioa_mask |= 1 << 12; /* DATA0 */
1376 if (gpio_is_valid(data->slot[0].detect_pin))
1377 at32_select_gpio(data->slot[0].detect_pin, 0);
1378 if (gpio_is_valid(data->slot[0].wp_pin))
1379 at32_select_gpio(data->slot[0].wp_pin, 0);
1382 /* Slot is unused */
1388 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1391 switch (data->slot[1].bus_width) {
1393 piob_mask |= 1 << 8; /* DATA1 */
1394 piob_mask |= 1 << 9; /* DATA2 */
1395 piob_mask |= 1 << 10; /* DATA3 */
1398 piob_mask |= 1 << 6; /* CMD */
1399 piob_mask |= 1 << 7; /* DATA0 */
1400 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1402 if (gpio_is_valid(data->slot[1].detect_pin))
1403 at32_select_gpio(data->slot[1].detect_pin, 0);
1404 if (gpio_is_valid(data->slot[1].wp_pin))
1405 at32_select_gpio(data->slot[1].wp_pin, 0);
1408 /* Slot is unused */
1411 if (!data->slot[0].bus_width)
1414 data->slot[1].bus_width = 0;
1418 atmel_mci0_pclk.dev = &pdev->dev;
1420 platform_device_add(pdev);
1426 data->dma_slave = NULL;
1427 platform_device_put(pdev);
1431 /* --------------------------------------------------------------------
1433 * -------------------------------------------------------------------- */
1434 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1435 static struct atmel_lcdfb_pdata atmel_lcdfb0_data;
1436 static struct resource atmel_lcdfb0_resource[] = {
1438 .start = 0xff000000,
1440 .flags = IORESOURCE_MEM,
1444 /* Placeholder for pre-allocated fb memory */
1445 .start = 0x00000000,
1450 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1451 DEV_CLK(hclk, atmel_lcdfb0, hsb, 7);
1452 static struct clk atmel_lcdfb0_pixclk = {
1454 .dev = &atmel_lcdfb0_device.dev,
1455 .mode = genclk_mode,
1456 .get_rate = genclk_get_rate,
1457 .set_rate = genclk_set_rate,
1458 .set_parent = genclk_set_parent,
1462 struct platform_device *__init
1463 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_pdata *data,
1464 unsigned long fbmem_start, unsigned long fbmem_len,
1467 struct platform_device *pdev;
1468 struct atmel_lcdfb_pdata *info;
1469 struct fb_monspecs *monspecs;
1470 struct fb_videomode *modedb;
1471 unsigned int modedb_size;
1472 u32 portc_mask, portd_mask, porte_mask;
1475 * Do a deep copy of the fb data, monspecs and modedb. Make
1476 * sure all allocations are done before setting up the
1479 monspecs = kmemdup(data->default_monspecs,
1480 sizeof(struct fb_monspecs), GFP_KERNEL);
1484 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1485 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1487 goto err_dup_modedb;
1488 monspecs->modedb = modedb;
1492 pdev = &atmel_lcdfb0_device;
1494 if (pin_mask == 0ULL)
1495 /* Default to "full" lcdc control signals and 24bit */
1496 pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1498 /* LCDC on port C */
1499 portc_mask = pin_mask & 0xfff80000;
1500 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1502 /* LCDC on port D */
1503 portd_mask = pin_mask & 0x0003ffff;
1504 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1506 /* LCDC on port E */
1507 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1508 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1510 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1511 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1515 goto err_invalid_id;
1519 pdev->resource[2].start = fbmem_start;
1520 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1521 pdev->resource[2].flags = IORESOURCE_MEM;
1524 info = pdev->dev.platform_data;
1525 memcpy(info, data, sizeof(struct atmel_lcdfb_pdata));
1526 info->default_monspecs = monspecs;
1528 pdev->name = "at32ap-lcdfb";
1530 platform_device_register(pdev);
1541 /* --------------------------------------------------------------------
1543 * -------------------------------------------------------------------- */
1544 static struct resource atmel_pwm0_resource[] __initdata = {
1548 static struct clk atmel_pwm0_mck = {
1549 .name = "at91sam9rl-pwm",
1551 .mode = pbb_clk_mode,
1552 .get_rate = pbb_clk_get_rate,
1556 struct platform_device *__init at32_add_device_pwm(u32 mask)
1558 struct platform_device *pdev;
1564 pdev = platform_device_alloc("at91sam9rl-pwm", 0);
1568 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1569 ARRAY_SIZE(atmel_pwm0_resource)))
1573 if (mask & (1 << 0))
1574 pin_mask |= (1 << 28);
1575 if (mask & (1 << 1))
1576 pin_mask |= (1 << 29);
1578 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1581 if (mask & (1 << 2))
1582 pin_mask |= (1 << 21);
1583 if (mask & (1 << 3))
1584 pin_mask |= (1 << 22);
1586 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1588 atmel_pwm0_mck.dev = &pdev->dev;
1590 platform_device_add(pdev);
1595 platform_device_put(pdev);
1599 /* --------------------------------------------------------------------
1601 * -------------------------------------------------------------------- */
1602 static struct resource ssc0_resource[] = {
1607 DEV_CLK(pclk, ssc0, pba, 7);
1609 static struct resource ssc1_resource[] = {
1614 DEV_CLK(pclk, ssc1, pba, 8);
1616 static struct resource ssc2_resource[] = {
1621 DEV_CLK(pclk, ssc2, pba, 9);
1623 struct platform_device *__init
1624 at32_add_device_ssc(unsigned int id, unsigned int flags)
1626 struct platform_device *pdev;
1631 pdev = &ssc0_device;
1632 if (flags & ATMEL_SSC_RF)
1633 pin_mask |= (1 << 21); /* RF */
1634 if (flags & ATMEL_SSC_RK)
1635 pin_mask |= (1 << 22); /* RK */
1636 if (flags & ATMEL_SSC_TK)
1637 pin_mask |= (1 << 23); /* TK */
1638 if (flags & ATMEL_SSC_TF)
1639 pin_mask |= (1 << 24); /* TF */
1640 if (flags & ATMEL_SSC_TD)
1641 pin_mask |= (1 << 25); /* TD */
1642 if (flags & ATMEL_SSC_RD)
1643 pin_mask |= (1 << 26); /* RD */
1646 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1650 pdev = &ssc1_device;
1651 if (flags & ATMEL_SSC_RF)
1652 pin_mask |= (1 << 0); /* RF */
1653 if (flags & ATMEL_SSC_RK)
1654 pin_mask |= (1 << 1); /* RK */
1655 if (flags & ATMEL_SSC_TK)
1656 pin_mask |= (1 << 2); /* TK */
1657 if (flags & ATMEL_SSC_TF)
1658 pin_mask |= (1 << 3); /* TF */
1659 if (flags & ATMEL_SSC_TD)
1660 pin_mask |= (1 << 4); /* TD */
1661 if (flags & ATMEL_SSC_RD)
1662 pin_mask |= (1 << 5); /* RD */
1665 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1669 pdev = &ssc2_device;
1670 if (flags & ATMEL_SSC_TD)
1671 pin_mask |= (1 << 13); /* TD */
1672 if (flags & ATMEL_SSC_RD)
1673 pin_mask |= (1 << 14); /* RD */
1674 if (flags & ATMEL_SSC_TK)
1675 pin_mask |= (1 << 15); /* TK */
1676 if (flags & ATMEL_SSC_TF)
1677 pin_mask |= (1 << 16); /* TF */
1678 if (flags & ATMEL_SSC_RF)
1679 pin_mask |= (1 << 17); /* RF */
1680 if (flags & ATMEL_SSC_RK)
1681 pin_mask |= (1 << 18); /* RK */
1684 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1691 platform_device_register(pdev);
1695 /* --------------------------------------------------------------------
1696 * USB Device Controller
1697 * -------------------------------------------------------------------- */
1698 static struct resource usba0_resource[] __initdata = {
1700 .start = 0xff300000,
1702 .flags = IORESOURCE_MEM,
1704 .start = 0xfff03000,
1706 .flags = IORESOURCE_MEM,
1710 static struct clk usba0_pclk = {
1713 .mode = pbb_clk_mode,
1714 .get_rate = pbb_clk_get_rate,
1717 static struct clk usba0_hclk = {
1720 .mode = hsb_clk_mode,
1721 .get_rate = hsb_clk_get_rate,
1725 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1729 .fifo_size = maxpkt, \
1730 .nr_banks = maxbk, \
1735 static struct usba_ep_data at32_usba_ep[] __initdata = {
1736 EP("ep0", 0, 64, 1, 0, 0),
1737 EP("ep1", 1, 512, 2, 1, 1),
1738 EP("ep2", 2, 512, 2, 1, 1),
1739 EP("ep3-int", 3, 64, 3, 1, 0),
1740 EP("ep4-int", 4, 64, 3, 1, 0),
1741 EP("ep5", 5, 1024, 3, 1, 1),
1742 EP("ep6", 6, 1024, 3, 1, 1),
1747 struct platform_device *__init
1748 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1751 * pdata doesn't have room for any endpoints, so we need to
1752 * append room for the ones we need right after it.
1755 struct usba_platform_data pdata;
1756 struct usba_ep_data ep[7];
1758 struct platform_device *pdev;
1763 pdev = platform_device_alloc("atmel_usba_udc", 0);
1767 if (platform_device_add_resources(pdev, usba0_resource,
1768 ARRAY_SIZE(usba0_resource)))
1772 usba_data.pdata.vbus_pin = data->vbus_pin;
1773 usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
1775 usba_data.pdata.vbus_pin = -EINVAL;
1776 usba_data.pdata.vbus_pin_inverted = -EINVAL;
1779 data = &usba_data.pdata;
1780 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1781 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1783 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1786 if (gpio_is_valid(data->vbus_pin))
1787 at32_select_gpio(data->vbus_pin, 0);
1789 usba0_pclk.dev = &pdev->dev;
1790 usba0_hclk.dev = &pdev->dev;
1792 platform_device_add(pdev);
1797 platform_device_put(pdev);
1801 /* --------------------------------------------------------------------
1802 * IDE / CompactFlash
1803 * -------------------------------------------------------------------- */
1804 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1805 static struct resource at32_smc_cs4_resource[] __initdata = {
1807 .start = 0x04000000,
1809 .flags = IORESOURCE_MEM,
1811 IRQ(~0UL), /* Magic IRQ will be overridden */
1813 static struct resource at32_smc_cs5_resource[] __initdata = {
1815 .start = 0x20000000,
1817 .flags = IORESOURCE_MEM,
1819 IRQ(~0UL), /* Magic IRQ will be overridden */
1822 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1823 unsigned int cs, unsigned int extint)
1825 static unsigned int extint_pin_map[4] __initdata = {
1831 static bool common_pins_initialized __initdata = false;
1832 unsigned int extint_pin;
1836 if (extint >= ARRAY_SIZE(extint_pin_map))
1838 extint_pin = extint_pin_map[extint];
1842 ret = platform_device_add_resources(pdev,
1843 at32_smc_cs4_resource,
1844 ARRAY_SIZE(at32_smc_cs4_resource));
1849 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1850 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1853 ret = platform_device_add_resources(pdev,
1854 at32_smc_cs5_resource,
1855 ARRAY_SIZE(at32_smc_cs5_resource));
1860 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1861 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1867 if (!common_pins_initialized) {
1868 pin_mask = (1 << 19); /* CFCE1 -> CS0_N */
1869 pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */
1870 pin_mask |= (1 << 23); /* CFRNW -> DIR */
1871 pin_mask |= (1 << 24); /* NWAIT <- IORDY */
1873 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1875 common_pins_initialized = true;
1878 select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1880 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1881 pdev->resource[1].end = pdev->resource[1].start;
1886 struct platform_device *__init
1887 at32_add_device_ide(unsigned int id, unsigned int extint,
1888 struct ide_platform_data *data)
1890 struct platform_device *pdev;
1892 pdev = platform_device_alloc("at32_ide", id);
1896 if (platform_device_add_data(pdev, data,
1897 sizeof(struct ide_platform_data)))
1900 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1903 platform_device_add(pdev);
1907 platform_device_put(pdev);
1911 struct platform_device *__init
1912 at32_add_device_cf(unsigned int id, unsigned int extint,
1913 struct cf_platform_data *data)
1915 struct platform_device *pdev;
1917 pdev = platform_device_alloc("at32_cf", id);
1921 if (platform_device_add_data(pdev, data,
1922 sizeof(struct cf_platform_data)))
1925 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1928 if (gpio_is_valid(data->detect_pin))
1929 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1930 if (gpio_is_valid(data->reset_pin))
1931 at32_select_gpio(data->reset_pin, 0);
1932 if (gpio_is_valid(data->vcc_pin))
1933 at32_select_gpio(data->vcc_pin, 0);
1934 /* READY is used as extint, so we can't select it as gpio */
1936 platform_device_add(pdev);
1940 platform_device_put(pdev);
1945 /* --------------------------------------------------------------------
1946 * NAND Flash / SmartMedia
1947 * -------------------------------------------------------------------- */
1948 static struct resource smc_cs3_resource[] __initdata = {
1950 .start = 0x0c000000,
1952 .flags = IORESOURCE_MEM,
1954 .start = 0xfff03c00,
1956 .flags = IORESOURCE_MEM,
1960 struct platform_device *__init
1961 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1963 struct platform_device *pdev;
1965 if (id != 0 || !data)
1968 pdev = platform_device_alloc("atmel_nand", id);
1972 if (platform_device_add_resources(pdev, smc_cs3_resource,
1973 ARRAY_SIZE(smc_cs3_resource)))
1976 /* For at32ap7000, we use the reset workaround for nand driver */
1977 data->need_reset_workaround = true;
1979 if (platform_device_add_data(pdev, data,
1980 sizeof(struct atmel_nand_data)))
1983 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1984 if (data->enable_pin)
1985 at32_select_gpio(data->enable_pin,
1986 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1988 at32_select_gpio(data->rdy_pin, 0);
1990 at32_select_gpio(data->det_pin, 0);
1992 platform_device_add(pdev);
1996 platform_device_put(pdev);
2000 /* --------------------------------------------------------------------
2002 * -------------------------------------------------------------------- */
2003 static struct resource atmel_ac97c0_resource[] __initdata = {
2007 static struct clk atmel_ac97c0_pclk = {
2010 .mode = pbb_clk_mode,
2011 .get_rate = pbb_clk_get_rate,
2015 struct platform_device *__init
2016 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2019 struct platform_device *pdev;
2020 struct dw_dma_slave *rx_dws;
2021 struct dw_dma_slave *tx_dws;
2022 struct ac97c_platform_data _data;
2028 pdev = platform_device_alloc("atmel_ac97c", id);
2032 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2033 ARRAY_SIZE(atmel_ac97c0_resource)))
2034 goto out_free_resources;
2038 memset(data, 0, sizeof(struct ac97c_platform_data));
2039 data->reset_pin = -ENODEV;
2042 rx_dws = &data->rx_dws;
2043 tx_dws = &data->tx_dws;
2045 /* Check if DMA slave interface for capture should be configured. */
2046 if (flags & AC97C_CAPTURE) {
2047 rx_dws->dma_dev = &dw_dmac0_device.dev;
2049 rx_dws->src_master = 0;
2050 rx_dws->dst_master = 1;
2053 /* Check if DMA slave interface for playback should be configured. */
2054 if (flags & AC97C_PLAYBACK) {
2055 tx_dws->dma_dev = &dw_dmac0_device.dev;
2057 tx_dws->src_master = 0;
2058 tx_dws->dst_master = 1;
2061 if (platform_device_add_data(pdev, data,
2062 sizeof(struct ac97c_platform_data)))
2063 goto out_free_resources;
2065 /* SDO | SYNC | SCLK | SDI */
2066 pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2068 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2070 if (gpio_is_valid(data->reset_pin))
2071 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2074 atmel_ac97c0_pclk.dev = &pdev->dev;
2076 platform_device_add(pdev);
2080 platform_device_put(pdev);
2084 /* --------------------------------------------------------------------
2086 * -------------------------------------------------------------------- */
2087 static struct resource abdac0_resource[] __initdata = {
2091 static struct clk abdac0_pclk = {
2094 .mode = pbb_clk_mode,
2095 .get_rate = pbb_clk_get_rate,
2098 static struct clk abdac0_sample_clk = {
2099 .name = "sample_clk",
2100 .mode = genclk_mode,
2101 .get_rate = genclk_get_rate,
2102 .set_rate = genclk_set_rate,
2103 .set_parent = genclk_set_parent,
2107 struct platform_device *__init
2108 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2110 struct platform_device *pdev;
2111 struct dw_dma_slave *dws;
2114 if (id != 0 || !data)
2117 pdev = platform_device_alloc("atmel_abdac", id);
2121 if (platform_device_add_resources(pdev, abdac0_resource,
2122 ARRAY_SIZE(abdac0_resource)))
2123 goto out_free_resources;
2127 dws->dma_dev = &dw_dmac0_device.dev;
2129 dws->src_master = 0;
2130 dws->dst_master = 1;
2132 if (platform_device_add_data(pdev, data,
2133 sizeof(struct atmel_abdac_pdata)))
2134 goto out_free_resources;
2136 pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
2137 pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
2139 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2141 abdac0_pclk.dev = &pdev->dev;
2142 abdac0_sample_clk.dev = &pdev->dev;
2144 platform_device_add(pdev);
2148 platform_device_put(pdev);
2152 /* --------------------------------------------------------------------
2154 * -------------------------------------------------------------------- */
2155 static struct clk gclk0 = {
2157 .mode = genclk_mode,
2158 .get_rate = genclk_get_rate,
2159 .set_rate = genclk_set_rate,
2160 .set_parent = genclk_set_parent,
2163 static struct clk gclk1 = {
2165 .mode = genclk_mode,
2166 .get_rate = genclk_get_rate,
2167 .set_rate = genclk_set_rate,
2168 .set_parent = genclk_set_parent,
2171 static struct clk gclk2 = {
2173 .mode = genclk_mode,
2174 .get_rate = genclk_get_rate,
2175 .set_rate = genclk_set_rate,
2176 .set_parent = genclk_set_parent,
2179 static struct clk gclk3 = {
2181 .mode = genclk_mode,
2182 .get_rate = genclk_get_rate,
2183 .set_rate = genclk_set_rate,
2184 .set_parent = genclk_set_parent,
2187 static struct clk gclk4 = {
2189 .mode = genclk_mode,
2190 .get_rate = genclk_get_rate,
2191 .set_rate = genclk_set_rate,
2192 .set_parent = genclk_set_parent,
2196 static __initdata struct clk *init_clocks[] = {
2227 &atmel_usart0_usart,
2228 &atmel_usart1_usart,
2229 &atmel_usart2_usart,
2230 &atmel_usart3_usart,
2232 #if defined(CONFIG_CPU_AT32AP7000)
2238 &atmel_spi0_spi_clk,
2239 &atmel_spi1_spi_clk,
2242 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2244 &atmel_lcdfb0_pixclk,
2261 void __init setup_platform(void)
2263 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2266 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2268 cpu_clk.parent = &pll0;
2271 cpu_clk.parent = &osc0;
2274 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2275 pll0.parent = &osc1;
2276 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2277 pll1.parent = &osc1;
2279 genclk_init_parent(&gclk0);
2280 genclk_init_parent(&gclk1);
2281 genclk_init_parent(&gclk2);
2282 genclk_init_parent(&gclk3);
2283 genclk_init_parent(&gclk4);
2284 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2285 genclk_init_parent(&atmel_lcdfb0_pixclk);
2287 genclk_init_parent(&abdac0_sample_clk);
2290 * Build initial dynamic clock list by registering all clocks
2292 * At the same time, turn on all clocks that have at least one
2293 * user already, and turn off everything else. We only do this
2294 * for module clocks, and even though it isn't particularly
2295 * pretty to check the address of the mode function, it should
2298 for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2299 struct clk *clk = init_clocks[i];
2301 /* first, register clock */
2302 at32_clk_register(clk);
2304 if (clk->users == 0)
2307 if (clk->mode == &cpu_clk_mode)
2308 cpu_mask |= 1 << clk->index;
2309 else if (clk->mode == &hsb_clk_mode)
2310 hsb_mask |= 1 << clk->index;
2311 else if (clk->mode == &pba_clk_mode)
2312 pba_mask |= 1 << clk->index;
2313 else if (clk->mode == &pbb_clk_mode)
2314 pbb_mask |= 1 << clk->index;
2317 pm_writel(CPU_MASK, cpu_mask);
2318 pm_writel(HSB_MASK, hsb_mask);
2319 pm_writel(PBA_MASK, pba_mask);
2320 pm_writel(PBB_MASK, pbb_mask);
2322 /* Initialize the port muxes */
2323 at32_init_pio(&pio0_device);
2324 at32_init_pio(&pio1_device);
2325 at32_init_pio(&pio2_device);
2326 at32_init_pio(&pio3_device);
2327 at32_init_pio(&pio4_device);
2330 struct gen_pool *sram_pool;
2332 static int __init sram_init(void)
2334 struct gen_pool *pool;
2336 /* 1KiB granularity */
2337 pool = gen_pool_create(10, -1);
2341 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2348 gen_pool_destroy(pool);
2350 pr_err("Failed to create SRAM pool\n");
2353 core_initcall(sram_init);