2 * External interrupt handling for AT32AP CPUs
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/errno.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/random.h>
17 #include <linux/slab.h>
21 /* EIC register offsets */
22 #define EIC_IER 0x0000
23 #define EIC_IDR 0x0004
24 #define EIC_IMR 0x0008
25 #define EIC_ISR 0x000c
26 #define EIC_ICR 0x0010
27 #define EIC_MODE 0x0014
28 #define EIC_EDGE 0x0018
29 #define EIC_LEVEL 0x001c
30 #define EIC_NMIC 0x0024
32 /* Bitfields in NMIC */
33 #define EIC_NMIC_ENABLE (1 << 0)
35 /* Bit manipulation macros */
36 #define EIC_BIT(name) \
37 (1 << EIC_##name##_OFFSET)
38 #define EIC_BF(name,value) \
39 (((value) & ((1 << EIC_##name##_SIZE) - 1)) \
40 << EIC_##name##_OFFSET)
41 #define EIC_BFEXT(name,value) \
42 (((value) >> EIC_##name##_OFFSET) \
43 & ((1 << EIC_##name##_SIZE) - 1))
44 #define EIC_BFINS(name,value,old) \
45 (((old) & ~(((1 << EIC_##name##_SIZE) - 1) \
46 << EIC_##name##_OFFSET)) \
49 /* Register access macros */
50 #define eic_readl(port,reg) \
51 __raw_readl((port)->regs + EIC_##reg)
52 #define eic_writel(port,reg,value) \
53 __raw_writel((value), (port)->regs + EIC_##reg)
57 struct irq_chip *chip;
58 unsigned int first_irq;
61 static struct eic *nmi_eic;
62 static bool nmi_enabled;
64 static void eic_ack_irq(struct irq_chip *d)
66 struct eic *eic = irq_data_get_irq_chip_data(data);
67 eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
70 static void eic_mask_irq(struct irq_chip *d)
72 struct eic *eic = irq_data_get_irq_chip_data(data);
73 eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
76 static void eic_mask_ack_irq(struct irq_chip *d)
78 struct eic *eic = irq_data_get_irq_chip_data(data);
79 eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
80 eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
83 static void eic_unmask_irq(struct irq_chip *d)
85 struct eic *eic = irq_data_get_irq_chip_data(data);
86 eic_writel(eic, IER, 1 << (d->irq - eic->first_irq));
89 static int eic_set_irq_type(struct irq_chip *d, unsigned int flow_type)
91 struct eic *eic = irq_data_get_irq_chip_data(data);
92 struct irq_desc *desc;
93 unsigned int irq = d->irq;
94 unsigned int i = irq - eic->first_irq;
95 u32 mode, edge, level;
98 flow_type &= IRQ_TYPE_SENSE_MASK;
99 if (flow_type == IRQ_TYPE_NONE)
100 flow_type = IRQ_TYPE_LEVEL_LOW;
102 desc = irq_to_desc(irq);
104 mode = eic_readl(eic, MODE);
105 edge = eic_readl(eic, EDGE);
106 level = eic_readl(eic, LEVEL);
109 case IRQ_TYPE_LEVEL_LOW:
113 case IRQ_TYPE_LEVEL_HIGH:
117 case IRQ_TYPE_EDGE_RISING:
121 case IRQ_TYPE_EDGE_FALLING:
131 eic_writel(eic, MODE, mode);
132 eic_writel(eic, EDGE, edge);
133 eic_writel(eic, LEVEL, level);
135 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
136 flow_type |= IRQ_LEVEL;
137 __set_irq_handler_unlocked(irq, handle_level_irq);
139 __set_irq_handler_unlocked(irq, handle_edge_irq);
140 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
141 desc->status |= flow_type;
147 static struct irq_chip eic_chip = {
149 .irq_ack = eic_ack_irq,
150 .irq_mask = eic_mask_irq,
151 .irq_mask_ack = eic_mask_ack_irq,
152 .irq_unmask = eic_unmask_irq,
153 .irq_set_type = eic_set_irq_type,
156 static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
158 struct eic *eic = get_irq_desc_data(desc);
159 unsigned long status, pending;
162 status = eic_readl(eic, ISR);
163 pending = status & eic_readl(eic, IMR);
166 i = fls(pending) - 1;
167 pending &= ~(1 << i);
169 generic_handle_irq(i + eic->first_irq);
178 eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
183 void nmi_disable(void)
186 eic_writel(nmi_eic, NMIC, 0);
191 static int __init eic_probe(struct platform_device *pdev)
194 struct resource *regs;
196 unsigned int nr_of_irqs;
197 unsigned int int_irq;
201 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202 int_irq = platform_get_irq(pdev, 0);
203 if (!regs || !int_irq) {
204 dev_dbg(&pdev->dev, "missing regs and/or irq resource\n");
209 eic = kzalloc(sizeof(struct eic), GFP_KERNEL);
211 dev_dbg(&pdev->dev, "no memory for eic structure\n");
215 eic->first_irq = EIM_IRQ_BASE + 32 * pdev->id;
216 eic->regs = ioremap(regs->start, regs->end - regs->start + 1);
218 dev_dbg(&pdev->dev, "failed to map regs\n");
223 * Find out how many interrupt lines that are actually
224 * implemented in hardware.
226 eic_writel(eic, IDR, ~0UL);
227 eic_writel(eic, MODE, ~0UL);
228 pattern = eic_readl(eic, MODE);
229 nr_of_irqs = fls(pattern);
231 /* Trigger on low level unless overridden by driver */
232 eic_writel(eic, EDGE, 0UL);
233 eic_writel(eic, LEVEL, 0UL);
235 eic->chip = &eic_chip;
237 for (i = 0; i < nr_of_irqs; i++) {
238 set_irq_chip_and_handler(eic->first_irq + i, &eic_chip,
240 set_irq_chip_data(eic->first_irq + i, eic);
243 set_irq_chained_handler(int_irq, demux_eic_irq);
244 set_irq_data(int_irq, eic);
250 * Someone tried to enable NMI before we were
257 "External Interrupt Controller at 0x%p, IRQ %u\n",
260 "Handling %u external IRQs, starting with IRQ %u\n",
261 nr_of_irqs, eic->first_irq);
271 static struct platform_driver eic_driver = {
277 static int __init eic_init(void)
279 return platform_driver_probe(&eic_driver, eic_probe);
281 arch_initcall(eic_init);