11 config RWSEM_GENERIC_SPINLOCK
14 config RWSEM_XCHGADD_ALGORITHM
20 select HAVE_ARCH_TRACEHOOK
21 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
23 select HAVE_FUNCTION_GRAPH_TRACER
24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
28 select HAVE_KERNEL_GZIP if RAMKERNEL
29 select HAVE_KERNEL_BZIP2 if RAMKERNEL
30 select HAVE_KERNEL_LZMA if RAMKERNEL
31 select HAVE_KERNEL_LZO if RAMKERNEL
33 select HAVE_PERF_EVENTS
34 select ARCH_WANT_OPTIONAL_GPIOLIB
35 select HAVE_GENERIC_HARDIRQS
36 select GENERIC_ATOMIC64
37 select GENERIC_IRQ_PROBE
38 select IRQ_PER_CPU if SMP
39 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
61 config LOCKDEP_SUPPORT
64 config STACKTRACE_SUPPORT
67 config TRACE_IRQFLAGS_SUPPORT
72 source "kernel/Kconfig.preempt"
74 source "kernel/Kconfig.freezer"
76 menu "Blackfin Processor Options"
78 comment "Processor and Board Settings"
87 BF512 Processor Support.
92 BF514 Processor Support.
97 BF516 Processor Support.
102 BF518 Processor Support.
107 BF522 Processor Support.
112 BF523 Processor Support.
117 BF524 Processor Support.
122 BF525 Processor Support.
127 BF526 Processor Support.
132 BF527 Processor Support.
137 BF531 Processor Support.
142 BF532 Processor Support.
147 BF533 Processor Support.
152 BF534 Processor Support.
157 BF536 Processor Support.
162 BF537 Processor Support.
167 BF538 Processor Support.
172 BF539 Processor Support.
177 BF542 Processor Support.
182 BF542 Processor Support.
187 BF544 Processor Support.
192 BF544 Processor Support.
197 BF547 Processor Support.
202 BF547 Processor Support.
207 BF548 Processor Support.
212 BF548 Processor Support.
217 BF549 Processor Support.
222 BF549 Processor Support.
227 BF561 Processor Support.
233 BF609 Processor Support.
239 select TICKSOURCE_CORETMR
240 bool "Symmetric multi-processing support"
242 This enables support for systems with more than one CPU,
243 like the dual core BF561. If you have a system with only one
244 CPU, say N. If you have a system with more than one CPU, say Y.
246 If you don't know what to do here, say N.
254 bool "Support for hot-pluggable CPUs"
255 depends on SMP && HOTPLUG
260 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
261 default 2 if (BF537 || BF536 || BF534)
262 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
263 default 4 if (BF538 || BF539)
267 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
268 default 3 if (BF537 || BF536 || BF534 || BF54xM)
269 default 5 if (BF561 || BF538 || BF539)
270 default 6 if (BF533 || BF532 || BF531)
274 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
275 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
276 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
280 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
284 depends on (BF51x || BF52x || (BF54x && !BF54xM))
288 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
292 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
296 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
300 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
304 depends on (BF533 || BF532 || BF531)
316 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
319 config MEM_MT48LC64M4A2FB_7E
321 depends on (BFIN533_STAMP)
324 config MEM_MT48LC16M16A2TG_75
326 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
327 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
328 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
329 || BFIN527_BLUETECHNIX_CM)
332 config MEM_MT48LC32M8A2_75
334 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
337 config MEM_MT48LC8M32B2B5_7
339 depends on (BFIN561_BLUETECHNIX_CM)
342 config MEM_MT48LC32M16A2TG_75
344 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
347 config MEM_MT48H32M16LFCJ_75
349 depends on (BFIN526_EZBRD)
352 source "arch/blackfin/mach-bf518/Kconfig"
353 source "arch/blackfin/mach-bf527/Kconfig"
354 source "arch/blackfin/mach-bf533/Kconfig"
355 source "arch/blackfin/mach-bf561/Kconfig"
356 source "arch/blackfin/mach-bf537/Kconfig"
357 source "arch/blackfin/mach-bf538/Kconfig"
358 source "arch/blackfin/mach-bf548/Kconfig"
359 source "arch/blackfin/mach-bf609/Kconfig"
361 menu "Board customizations"
364 bool "Default bootloader kernel arguments"
367 string "Initial kernel command string"
368 depends on CMDLINE_BOOL
369 default "console=ttyBF0,57600"
371 If you don't have a boot loader capable of passing a command line string
372 to the kernel, you may specify one here. As a minimum, you should specify
373 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
376 hex "Kernel load address for booting"
378 range 0x1000 0x20000000
380 This option allows you to set the load address of the kernel.
381 This can be useful if you are on a board which has a small amount
382 of memory or you wish to reserve some memory at the beginning of
385 Note that you need to keep this value above 4k (0x1000) as this
386 memory region is used to capture NULL pointer references as well
387 as some core kernel functions.
389 config PHY_RAM_BASE_ADDRESS
390 hex "Physical RAM Base"
393 set BF609 FPGA physical SRAM base address
396 hex "Kernel ROM Base"
399 range 0x20000000 0x20400000 if !(BF54x || BF561)
400 range 0x20000000 0x30000000 if (BF54x || BF561)
402 Make sure your ROM base does not include any file-header
403 information that is prepended to the kernel.
405 For example, the bootable U-Boot format (created with
406 mkimage) has a 64 byte header (0x40). So while the image
407 you write to flash might start at say 0x20080000, you have
408 to add 0x40 to get the kernel's ROM base as it will come
411 comment "Clock/PLL Setup"
414 int "Frequency of the crystal on the board in Hz"
415 default "10000000" if BFIN532_IP0X
416 default "11059200" if BFIN533_STAMP
417 default "24576000" if PNAV10
418 default "25000000" # most people use this
419 default "27000000" if BFIN533_EZKIT
420 default "30000000" if BFIN561_EZKIT
421 default "24000000" if BFIN527_AD7160EVAL
423 The frequency of CLKIN crystal oscillator on the board in Hz.
424 Warning: This value should match the crystal on the board. Otherwise,
425 peripherals won't work properly.
427 config BFIN_KERNEL_CLOCK
428 bool "Re-program Clocks while Kernel boots?"
431 This option decides if kernel clocks are re-programed from the
432 bootloader settings. If the clocks are not set, the SDRAM settings
433 are also not changed, and the Bootloader does 100% of the hardware
438 depends on BFIN_KERNEL_CLOCK
443 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
446 If this is set the clock will be divided by 2, before it goes to the PLL.
450 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
452 default "22" if BFIN533_EZKIT
453 default "45" if BFIN533_STAMP
454 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
455 default "22" if BFIN533_BLUETECHNIX_CM
456 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
457 default "20" if BFIN561_EZKIT
458 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
459 default "25" if BFIN527_AD7160EVAL
461 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
462 PLL Frequency = (Crystal Frequency) * (this setting)
465 prompt "Core Clock Divider"
466 depends on BFIN_KERNEL_CLOCK
469 This sets the frequency of the core. It can be 1, 2, 4 or 8
470 Core Frequency = (PLL frequency) / (this setting)
486 int "System Clock Divider"
487 depends on BFIN_KERNEL_CLOCK
491 This sets the frequency of the system clock (including SDRAM or DDR).
492 This can be between 1 and 15
493 System Clock = (PLL frequency) / (this setting)
496 prompt "DDR SDRAM Chip Type"
497 depends on BFIN_KERNEL_CLOCK
499 default MEM_MT46V32M16_5B
501 config MEM_MT46V32M16_6T
504 config MEM_MT46V32M16_5B
509 prompt "DDR/SDRAM Timing"
510 depends on BFIN_KERNEL_CLOCK
511 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
513 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
514 The calculated SDRAM timing parameters may not be 100%
515 accurate - This option is therefore marked experimental.
517 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
518 bool "Calculate Timings (EXPERIMENTAL)"
519 depends on EXPERIMENTAL
521 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
522 bool "Provide accurate Timings based on target SCLK"
524 Please consult the Blackfin Hardware Reference Manuals as well
525 as the memory device datasheet.
526 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
529 menu "Memory Init Control"
530 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
547 config MEM_EBIU_DDRQUE
564 # Max & Min Speeds for various Chips
568 default 400000000 if BF512
569 default 400000000 if BF514
570 default 400000000 if BF516
571 default 400000000 if BF518
572 default 400000000 if BF522
573 default 600000000 if BF523
574 default 400000000 if BF524
575 default 600000000 if BF525
576 default 400000000 if BF526
577 default 600000000 if BF527
578 default 400000000 if BF531
579 default 400000000 if BF532
580 default 750000000 if BF533
581 default 500000000 if BF534
582 default 400000000 if BF536
583 default 600000000 if BF537
584 default 533333333 if BF538
585 default 533333333 if BF539
586 default 600000000 if BF542
587 default 533333333 if BF544
588 default 600000000 if BF547
589 default 600000000 if BF548
590 default 533333333 if BF549
591 default 600000000 if BF561
605 comment "Kernel Timer/Scheduler"
607 source kernel/Kconfig.hz
609 config GENERIC_CLOCKEVENTS
610 bool "Generic clock events"
613 menu "Clock event device"
614 depends on GENERIC_CLOCKEVENTS
615 config TICKSOURCE_GPTMR0
620 config TICKSOURCE_CORETMR
626 depends on GENERIC_CLOCKEVENTS
627 config CYCLES_CLOCKSOURCE
630 depends on !BFIN_SCRATCH_REG_CYCLES
633 If you say Y here, you will enable support for using the 'cycles'
634 registers as a clock source. Doing so means you will be unable to
635 safely write to the 'cycles' register during runtime. You will
636 still be able to read it (such as for performance monitoring), but
637 writing the registers will most likely crash the kernel.
639 config GPTMR0_CLOCKSOURCE
642 depends on !TICKSOURCE_GPTMR0
645 config ARCH_USES_GETTIMEOFFSET
646 depends on !GENERIC_CLOCKEVENTS
649 source kernel/time/Kconfig
654 prompt "Blackfin Exception Scratch Register"
655 default BFIN_SCRATCH_REG_RETN
657 Select the resource to reserve for the Exception handler:
658 - RETN: Non-Maskable Interrupt (NMI)
659 - RETE: Exception Return (JTAG/ICE)
660 - CYCLES: Performance counter
662 If you are unsure, please select "RETN".
664 config BFIN_SCRATCH_REG_RETN
667 Use the RETN register in the Blackfin exception handler
668 as a stack scratch register. This means you cannot
669 safely use NMI on the Blackfin while running Linux, but
670 you can debug the system with a JTAG ICE and use the
671 CYCLES performance registers.
673 If you are unsure, please select "RETN".
675 config BFIN_SCRATCH_REG_RETE
678 Use the RETE register in the Blackfin exception handler
679 as a stack scratch register. This means you cannot
680 safely use a JTAG ICE while debugging a Blackfin board,
681 but you can safely use the CYCLES performance registers
684 If you are unsure, please select "RETN".
686 config BFIN_SCRATCH_REG_CYCLES
689 Use the CYCLES register in the Blackfin exception handler
690 as a stack scratch register. This means you cannot
691 safely use the CYCLES performance registers on a Blackfin
692 board at anytime, but you can debug the system with a JTAG
695 If you are unsure, please select "RETN".
702 menu "Blackfin Kernel Optimizations"
704 comment "Memory Optimizations"
707 bool "Locate interrupt entry code in L1 Memory"
711 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
712 into L1 instruction memory. (less latency)
714 config EXCPT_IRQ_SYSC_L1
715 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
719 If enabled, the entire ASM lowlevel exception and interrupt entry code
720 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
724 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
728 If enabled, the frequently called do_irq dispatcher function is linked
729 into L1 instruction memory. (less latency)
731 config CORE_TIMER_IRQ_L1
732 bool "Locate frequently called timer_interrupt() function in L1 Memory"
736 If enabled, the frequently called timer_interrupt() function is linked
737 into L1 instruction memory. (less latency)
740 bool "Locate frequently idle function in L1 Memory"
744 If enabled, the frequently called idle function is linked
745 into L1 instruction memory. (less latency)
748 bool "Locate kernel schedule function in L1 Memory"
752 If enabled, the frequently called kernel schedule is linked
753 into L1 instruction memory. (less latency)
755 config ARITHMETIC_OPS_L1
756 bool "Locate kernel owned arithmetic functions in L1 Memory"
760 If enabled, arithmetic functions are linked
761 into L1 instruction memory. (less latency)
764 bool "Locate access_ok function in L1 Memory"
768 If enabled, the access_ok function is linked
769 into L1 instruction memory. (less latency)
772 bool "Locate memset function in L1 Memory"
776 If enabled, the memset function is linked
777 into L1 instruction memory. (less latency)
780 bool "Locate memcpy function in L1 Memory"
784 If enabled, the memcpy function is linked
785 into L1 instruction memory. (less latency)
788 bool "locate strcmp function in L1 Memory"
792 If enabled, the strcmp function is linked
793 into L1 instruction memory (less latency).
796 bool "locate strncmp function in L1 Memory"
800 If enabled, the strncmp function is linked
801 into L1 instruction memory (less latency).
804 bool "locate strcpy function in L1 Memory"
808 If enabled, the strcpy function is linked
809 into L1 instruction memory (less latency).
812 bool "locate strncpy function in L1 Memory"
816 If enabled, the strncpy function is linked
817 into L1 instruction memory (less latency).
819 config SYS_BFIN_SPINLOCK_L1
820 bool "Locate sys_bfin_spinlock function in L1 Memory"
824 If enabled, sys_bfin_spinlock function is linked
825 into L1 instruction memory. (less latency)
827 config IP_CHECKSUM_L1
828 bool "Locate IP Checksum function in L1 Memory"
832 If enabled, the IP Checksum function is linked
833 into L1 instruction memory. (less latency)
835 config CACHELINE_ALIGNED_L1
836 bool "Locate cacheline_aligned data to L1 Data Memory"
839 depends on !SMP && !BF531 && !CRC32
841 If enabled, cacheline_aligned data is linked
842 into L1 data memory. (less latency)
844 config SYSCALL_TAB_L1
845 bool "Locate Syscall Table L1 Data Memory"
847 depends on !SMP && !BF531
849 If enabled, the Syscall LUT is linked
850 into L1 data memory. (less latency)
852 config CPLB_SWITCH_TAB_L1
853 bool "Locate CPLB Switch Tables L1 Data Memory"
855 depends on !SMP && !BF531
857 If enabled, the CPLB Switch Tables are linked
858 into L1 data memory. (less latency)
860 config ICACHE_FLUSH_L1
861 bool "Locate icache flush funcs in L1 Inst Memory"
864 If enabled, the Blackfin icache flushing functions are linked
865 into L1 instruction memory.
867 Note that this might be required to address anomalies, but
868 these functions are pretty small, so it shouldn't be too bad.
869 If you are using a processor affected by an anomaly, the build
870 system will double check for you and prevent it.
872 config DCACHE_FLUSH_L1
873 bool "Locate dcache flush funcs in L1 Inst Memory"
877 If enabled, the Blackfin dcache flushing functions are linked
878 into L1 instruction memory.
881 bool "Support locating application stack in L1 Scratch Memory"
885 If enabled the application stack can be located in L1
886 scratch memory (less latency).
888 Currently only works with FLAT binaries.
890 config EXCEPTION_L1_SCRATCH
891 bool "Locate exception stack in L1 Scratch Memory"
893 depends on !SMP && !APP_STACK_L1
895 Whenever an exception occurs, use the L1 Scratch memory for
896 stack storage. You cannot place the stacks of FLAT binaries
897 in L1 when using this option.
899 If you don't use L1 Scratch, then you should say Y here.
901 comment "Speed Optimizations"
902 config BFIN_INS_LOWOVERHEAD
903 bool "ins[bwl] low overhead, higher interrupt latency"
907 Reads on the Blackfin are speculative. In Blackfin terms, this means
908 they can be interrupted at any time (even after they have been issued
909 on to the external bus), and re-issued after the interrupt occurs.
910 For memory - this is not a big deal, since memory does not change if
913 If a FIFO is sitting on the end of the read, it will see two reads,
914 when the core only sees one since the FIFO receives both the read
915 which is cancelled (and not delivered to the core) and the one which
916 is re-issued (which is delivered to the core).
918 To solve this, interrupts are turned off before reads occur to
919 I/O space. This option controls which the overhead/latency of
920 controlling interrupts during this time
921 "n" turns interrupts off every read
922 (higher overhead, but lower interrupt latency)
923 "y" turns interrupts off every loop
924 (low overhead, but longer interrupt latency)
926 default behavior is to leave this set to on (type "Y"). If you are experiencing
927 interrupt latency issues, it is safe and OK to turn this off.
932 prompt "Kernel executes from"
934 Choose the memory type that the kernel will be running in.
939 The kernel will be resident in RAM when running.
944 The kernel will be resident in FLASH/ROM when running.
948 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
957 tristate "Enable Blackfin General Purpose Timers API"
960 Enable support for the General Purpose Timers API. If you
963 To compile this driver as a module, choose M here: the module
964 will be called gptimers.
967 tristate "Enable PWM API support"
968 depends on BFIN_GPTIMERS
970 Enable support for the Pulse Width Modulation framework (as
971 found in linux/pwm.h).
973 To compile this driver as a module, choose M here: the module
977 prompt "Uncached DMA region"
978 default DMA_UNCACHED_1M
979 config DMA_UNCACHED_4M
980 bool "Enable 4M DMA region"
981 config DMA_UNCACHED_2M
982 bool "Enable 2M DMA region"
983 config DMA_UNCACHED_1M
984 bool "Enable 1M DMA region"
985 config DMA_UNCACHED_512K
986 bool "Enable 512K DMA region"
987 config DMA_UNCACHED_256K
988 bool "Enable 256K DMA region"
989 config DMA_UNCACHED_128K
990 bool "Enable 128K DMA region"
991 config DMA_UNCACHED_NONE
992 bool "Disable DMA region"
996 comment "Cache Support"
1001 config BFIN_EXTMEM_ICACHEABLE
1002 bool "Enable ICACHE for external memory"
1003 depends on BFIN_ICACHE
1005 config BFIN_L2_ICACHEABLE
1006 bool "Enable ICACHE for L2 SRAM"
1007 depends on BFIN_ICACHE
1008 depends on BF54x || BF561
1012 bool "Enable DCACHE"
1014 config BFIN_DCACHE_BANKA
1015 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1016 depends on BFIN_DCACHE && !BF531
1018 config BFIN_EXTMEM_DCACHEABLE
1019 bool "Enable DCACHE for external memory"
1020 depends on BFIN_DCACHE
1023 prompt "External memory DCACHE policy"
1024 depends on BFIN_EXTMEM_DCACHEABLE
1025 default BFIN_EXTMEM_WRITEBACK if !SMP
1026 default BFIN_EXTMEM_WRITETHROUGH if SMP
1027 config BFIN_EXTMEM_WRITEBACK
1032 Cached data will be written back to SDRAM only when needed.
1033 This can give a nice increase in performance, but beware of
1034 broken drivers that do not properly invalidate/flush their
1037 Write Through Policy:
1038 Cached data will always be written back to SDRAM when the
1039 cache is updated. This is a completely safe setting, but
1040 performance is worse than Write Back.
1042 If you are unsure of the options and you want to be safe,
1043 then go with Write Through.
1045 config BFIN_EXTMEM_WRITETHROUGH
1046 bool "Write through"
1049 Cached data will be written back to SDRAM only when needed.
1050 This can give a nice increase in performance, but beware of
1051 broken drivers that do not properly invalidate/flush their
1054 Write Through Policy:
1055 Cached data will always be written back to SDRAM when the
1056 cache is updated. This is a completely safe setting, but
1057 performance is worse than Write Back.
1059 If you are unsure of the options and you want to be safe,
1060 then go with Write Through.
1064 config BFIN_L2_DCACHEABLE
1065 bool "Enable DCACHE for L2 SRAM"
1066 depends on BFIN_DCACHE
1067 depends on (BF54x || BF561 || BF60x) && !SMP
1070 prompt "L2 SRAM DCACHE policy"
1071 depends on BFIN_L2_DCACHEABLE
1072 default BFIN_L2_WRITEBACK
1073 config BFIN_L2_WRITEBACK
1076 config BFIN_L2_WRITETHROUGH
1077 bool "Write through"
1081 comment "Memory Protection Unit"
1083 bool "Enable the memory protection unit (EXPERIMENTAL)"
1086 Use the processor's MPU to protect applications from accessing
1087 memory they do not own. This comes at a performance penalty
1088 and is recommended only for debugging.
1090 comment "Asynchronous Memory Configuration"
1092 menu "EBIU_AMGCTL Global Control"
1095 bool "Enable CLKOUT"
1099 bool "DMA has priority over core for ext. accesses"
1104 bool "Bank 0 16 bit packing enable"
1109 bool "Bank 1 16 bit packing enable"
1114 bool "Bank 2 16 bit packing enable"
1119 bool "Bank 3 16 bit packing enable"
1123 prompt "Enable Asynchronous Memory Banks"
1127 bool "Disable All Banks"
1130 bool "Enable Bank 0"
1132 config C_AMBEN_B0_B1
1133 bool "Enable Bank 0 & 1"
1135 config C_AMBEN_B0_B1_B2
1136 bool "Enable Bank 0 & 1 & 2"
1139 bool "Enable All Banks"
1143 menu "EBIU_AMBCTL Control"
1146 hex "Bank 0 (AMBCTL0.L)"
1149 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1150 used to control the Asynchronous Memory Bank 0 settings.
1153 hex "Bank 1 (AMBCTL0.H)"
1155 default 0x5558 if BF54x
1157 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1158 used to control the Asynchronous Memory Bank 1 settings.
1161 hex "Bank 2 (AMBCTL1.L)"
1164 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1165 used to control the Asynchronous Memory Bank 2 settings.
1168 hex "Bank 3 (AMBCTL1.H)"
1171 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1172 used to control the Asynchronous Memory Bank 3 settings.
1176 config EBIU_MBSCTLVAL
1177 hex "EBIU Bank Select Control Register"
1182 hex "Flash Memory Mode Control Register"
1187 hex "Flash Memory Bank Control Register"
1192 #############################################################################
1193 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1199 Support for PCI bus.
1201 source "drivers/pci/Kconfig"
1203 source "drivers/pcmcia/Kconfig"
1205 source "drivers/pci/hotplug/Kconfig"
1209 menu "Executable file formats"
1211 source "fs/Kconfig.binfmt"
1215 menu "Power management options"
1217 source "kernel/power/Kconfig"
1219 config ARCH_SUSPEND_POSSIBLE
1223 prompt "Standby Power Saving Mode"
1225 default PM_BFIN_SLEEP_DEEPER
1226 config PM_BFIN_SLEEP_DEEPER
1229 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1230 power dissipation by disabling the clock to the processor core (CCLK).
1231 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1232 to 0.85 V to provide the greatest power savings, while preserving the
1234 The PLL and system clock (SCLK) continue to operate at a very low
1235 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1236 the SDRAM is put into Self Refresh Mode. Typically an external event
1237 such as GPIO interrupt or RTC activity wakes up the processor.
1238 Various Peripherals such as UART, SPORT, PPI may not function as
1239 normal during Sleep Deeper, due to the reduced SCLK frequency.
1240 When in the sleep mode, system DMA access to L1 memory is not supported.
1242 If unsure, select "Sleep Deeper".
1244 config PM_BFIN_SLEEP
1247 Sleep Mode (High Power Savings) - The sleep mode reduces power
1248 dissipation by disabling the clock to the processor core (CCLK).
1249 The PLL and system clock (SCLK), however, continue to operate in
1250 this mode. Typically an external event or RTC activity will wake
1251 up the processor. When in the sleep mode, system DMA access to L1
1252 memory is not supported.
1254 If unsure, select "Sleep Deeper".
1257 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1260 config PM_BFIN_WAKE_PH6
1261 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1262 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1265 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1267 config PM_BFIN_WAKE_GP
1268 bool "Allow Wake-Up from GPIOs"
1269 depends on PM && BF54x
1272 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1273 (all processors, except ADSP-BF549). This option sets
1274 the general-purpose wake-up enable (GPWE) control bit to enable
1275 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1276 On ADSP-BF549 this option enables the the same functionality on the
1277 /MRXON pin also PH7.
1281 menu "CPU Frequency scaling"
1283 source "drivers/cpufreq/Kconfig"
1285 config BFIN_CPU_FREQ
1288 select CPU_FREQ_TABLE
1292 bool "CPU Voltage scaling"
1293 depends on EXPERIMENTAL
1297 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1298 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1299 manuals. There is a theoretical risk that during VDDINT transitions
1304 source "net/Kconfig"
1306 source "drivers/Kconfig"
1308 source "drivers/firmware/Kconfig"
1312 source "arch/blackfin/Kconfig.debug"
1314 source "security/Kconfig"
1316 source "crypto/Kconfig"
1318 source "lib/Kconfig"