2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
14 config RWSEM_GENERIC_SPINLOCK
17 config RWSEM_XCHGADD_ALGORITHM
24 select ARCH_WANT_OPTIONAL_GPIOLIB
33 config GENERIC_FIND_NEXT_BIT
36 config GENERIC_HWEIGHT
39 config GENERIC_HARDIRQS
42 config GENERIC_IRQ_PROBE
48 config FORCE_MAX_ZONEORDER
52 config GENERIC_CALIBRATE_DELAY
57 source "kernel/Kconfig.preempt"
59 source "kernel/Kconfig.freezer"
61 menu "Blackfin Processor Options"
63 comment "Processor and Board Settings"
72 BF512 Processor Support.
77 BF514 Processor Support.
82 BF516 Processor Support.
87 BF518 Processor Support.
92 BF522 Processor Support.
97 BF523 Processor Support.
102 BF524 Processor Support.
107 BF525 Processor Support.
112 BF526 Processor Support.
117 BF527 Processor Support.
122 BF531 Processor Support.
127 BF532 Processor Support.
132 BF533 Processor Support.
137 BF534 Processor Support.
142 BF536 Processor Support.
147 BF537 Processor Support.
152 BF538 Processor Support.
157 BF539 Processor Support.
162 BF542 Processor Support.
167 BF542 Processor Support.
172 BF544 Processor Support.
177 BF544 Processor Support.
182 BF547 Processor Support.
187 BF547 Processor Support.
192 BF548 Processor Support.
197 BF548 Processor Support.
202 BF549 Processor Support.
207 BF549 Processor Support.
212 BF561 Processor Support.
219 bool "Symmetric multi-processing support"
221 This enables support for systems with more than one CPU,
222 like the dual core BF561. If you have a system with only one
223 CPU, say N. If you have a system with more than one CPU, say Y.
225 If you don't know what to do here, say N.
239 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
240 default 2 if (BF537 || BF536 || BF534)
241 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
242 default 4 if (BF538 || BF539)
246 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
247 default 3 if (BF537 || BF536 || BF534 || BF54xM)
248 default 5 if (BF561 || BF538 || BF539)
249 default 6 if (BF533 || BF532 || BF531)
253 default BF_REV_0_0 if (BF51x || BF52x)
254 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
255 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
259 depends on (BF51x || BF52x || (BF54x && !BF54xM))
263 depends on (BF52x || (BF54x && !BF54xM))
267 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
271 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
275 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
279 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
283 depends on (BF533 || BF532 || BF531)
295 depends on (BF512 || BF514 || BF516 || BF518)
300 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
305 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
310 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
315 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
318 config MEM_GENERIC_BOARD
320 depends on GENERIC_BOARD
323 config MEM_MT48LC64M4A2FB_7E
325 depends on (BFIN533_STAMP)
328 config MEM_MT48LC16M16A2TG_75
330 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
331 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
332 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
335 config MEM_MT48LC32M8A2_75
337 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
340 config MEM_MT48LC8M32B2B5_7
342 depends on (BFIN561_BLUETECHNIX_CM)
345 config MEM_MT48LC32M16A2TG_75
347 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
350 config MEM_MT48LC32M8A2_75
352 depends on (BFIN518F_EZBRD)
355 source "arch/blackfin/mach-bf518/Kconfig"
356 source "arch/blackfin/mach-bf527/Kconfig"
357 source "arch/blackfin/mach-bf533/Kconfig"
358 source "arch/blackfin/mach-bf561/Kconfig"
359 source "arch/blackfin/mach-bf537/Kconfig"
360 source "arch/blackfin/mach-bf538/Kconfig"
361 source "arch/blackfin/mach-bf548/Kconfig"
363 menu "Board customizations"
366 bool "Default bootloader kernel arguments"
369 string "Initial kernel command string"
370 depends on CMDLINE_BOOL
371 default "console=ttyBF0,57600"
373 If you don't have a boot loader capable of passing a command line string
374 to the kernel, you may specify one here. As a minimum, you should specify
375 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
378 hex "Kernel load address for booting"
380 range 0x1000 0x20000000
382 This option allows you to set the load address of the kernel.
383 This can be useful if you are on a board which has a small amount
384 of memory or you wish to reserve some memory at the beginning of
387 Note that you need to keep this value above 4k (0x1000) as this
388 memory region is used to capture NULL pointer references as well
389 as some core kernel functions.
392 hex "Kernel ROM Base"
395 range 0x20000000 0x20400000 if !(BF54x || BF561)
396 range 0x20000000 0x30000000 if (BF54x || BF561)
399 comment "Clock/PLL Setup"
402 int "Frequency of the crystal on the board in Hz"
403 default "11059200" if BFIN533_STAMP
404 default "27000000" if BFIN533_EZKIT
405 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
406 default "30000000" if BFIN561_EZKIT
407 default "24576000" if PNAV10
408 default "10000000" if BFIN532_IP0X
410 The frequency of CLKIN crystal oscillator on the board in Hz.
411 Warning: This value should match the crystal on the board. Otherwise,
412 peripherals won't work properly.
414 config BFIN_KERNEL_CLOCK
415 bool "Re-program Clocks while Kernel boots?"
418 This option decides if kernel clocks are re-programed from the
419 bootloader settings. If the clocks are not set, the SDRAM settings
420 are also not changed, and the Bootloader does 100% of the hardware
425 depends on BFIN_KERNEL_CLOCK
430 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
433 If this is set the clock will be divided by 2, before it goes to the PLL.
437 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
439 default "22" if BFIN533_EZKIT
440 default "45" if BFIN533_STAMP
441 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
442 default "22" if BFIN533_BLUETECHNIX_CM
443 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
444 default "20" if BFIN561_EZKIT
445 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
447 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
448 PLL Frequency = (Crystal Frequency) * (this setting)
451 prompt "Core Clock Divider"
452 depends on BFIN_KERNEL_CLOCK
455 This sets the frequency of the core. It can be 1, 2, 4 or 8
456 Core Frequency = (PLL frequency) / (this setting)
472 int "System Clock Divider"
473 depends on BFIN_KERNEL_CLOCK
477 This sets the frequency of the system clock (including SDRAM or DDR).
478 This can be between 1 and 15
479 System Clock = (PLL frequency) / (this setting)
482 prompt "DDR SDRAM Chip Type"
483 depends on BFIN_KERNEL_CLOCK
485 default MEM_MT46V32M16_5B
487 config MEM_MT46V32M16_6T
490 config MEM_MT46V32M16_5B
495 prompt "DDR/SDRAM Timing"
496 depends on BFIN_KERNEL_CLOCK
497 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
499 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
500 The calculated SDRAM timing parameters may not be 100%
501 accurate - This option is therefore marked experimental.
503 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
504 bool "Calculate Timings (EXPERIMENTAL)"
505 depends on EXPERIMENTAL
507 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
508 bool "Provide accurate Timings based on target SCLK"
510 Please consult the Blackfin Hardware Reference Manuals as well
511 as the memory device datasheet.
512 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
515 menu "Memory Init Control"
516 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
533 config MEM_EBIU_DDRQUE
550 # Max & Min Speeds for various Chips
554 default 400000000 if BF512
555 default 400000000 if BF514
556 default 400000000 if BF516
557 default 400000000 if BF518
558 default 600000000 if BF522
559 default 400000000 if BF523
560 default 400000000 if BF524
561 default 600000000 if BF525
562 default 400000000 if BF526
563 default 600000000 if BF527
564 default 400000000 if BF531
565 default 400000000 if BF532
566 default 750000000 if BF533
567 default 500000000 if BF534
568 default 400000000 if BF536
569 default 600000000 if BF537
570 default 533333333 if BF538
571 default 533333333 if BF539
572 default 600000000 if BF542
573 default 533333333 if BF544
574 default 600000000 if BF547
575 default 600000000 if BF548
576 default 533333333 if BF549
577 default 600000000 if BF561
591 comment "Kernel Timer/Scheduler"
593 source kernel/Kconfig.hz
599 config GENERIC_CLOCKEVENTS
600 bool "Generic clock events"
601 depends on GENERIC_TIME
605 prompt "Kernel Tick Source"
606 depends on GENERIC_CLOCKEVENTS
607 default TICKSOURCE_CORETMR
609 config TICKSOURCE_GPTMR0
610 bool "Gptimer0 (SCLK domain)"
614 config TICKSOURCE_CORETMR
615 bool "Core timer (CCLK domain)"
619 config CYCLES_CLOCKSOURCE
620 bool "Use 'CYCLES' as a clocksource"
621 depends on GENERIC_CLOCKEVENTS
622 depends on !BFIN_SCRATCH_REG_CYCLES
625 If you say Y here, you will enable support for using the 'cycles'
626 registers as a clock source. Doing so means you will be unable to
627 safely write to the 'cycles' register during runtime. You will
628 still be able to read it (such as for performance monitoring), but
629 writing the registers will most likely crash the kernel.
631 config GPTMR0_CLOCKSOURCE
632 bool "Use GPTimer0 as a clocksource (higher rating)"
633 depends on GENERIC_CLOCKEVENTS
634 depends on !TICKSOURCE_GPTMR0
636 source kernel/time/Kconfig
641 prompt "Blackfin Exception Scratch Register"
642 default BFIN_SCRATCH_REG_RETN
644 Select the resource to reserve for the Exception handler:
645 - RETN: Non-Maskable Interrupt (NMI)
646 - RETE: Exception Return (JTAG/ICE)
647 - CYCLES: Performance counter
649 If you are unsure, please select "RETN".
651 config BFIN_SCRATCH_REG_RETN
654 Use the RETN register in the Blackfin exception handler
655 as a stack scratch register. This means you cannot
656 safely use NMI on the Blackfin while running Linux, but
657 you can debug the system with a JTAG ICE and use the
658 CYCLES performance registers.
660 If you are unsure, please select "RETN".
662 config BFIN_SCRATCH_REG_RETE
665 Use the RETE register in the Blackfin exception handler
666 as a stack scratch register. This means you cannot
667 safely use a JTAG ICE while debugging a Blackfin board,
668 but you can safely use the CYCLES performance registers
671 If you are unsure, please select "RETN".
673 config BFIN_SCRATCH_REG_CYCLES
676 Use the CYCLES register in the Blackfin exception handler
677 as a stack scratch register. This means you cannot
678 safely use the CYCLES performance registers on a Blackfin
679 board at anytime, but you can debug the system with a JTAG
682 If you are unsure, please select "RETN".
689 menu "Blackfin Kernel Optimizations"
692 comment "Memory Optimizations"
695 bool "Locate interrupt entry code in L1 Memory"
698 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
699 into L1 instruction memory. (less latency)
701 config EXCPT_IRQ_SYSC_L1
702 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
705 If enabled, the entire ASM lowlevel exception and interrupt entry code
706 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
710 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
713 If enabled, the frequently called do_irq dispatcher function is linked
714 into L1 instruction memory. (less latency)
716 config CORE_TIMER_IRQ_L1
717 bool "Locate frequently called timer_interrupt() function in L1 Memory"
720 If enabled, the frequently called timer_interrupt() function is linked
721 into L1 instruction memory. (less latency)
724 bool "Locate frequently idle function in L1 Memory"
727 If enabled, the frequently called idle function is linked
728 into L1 instruction memory. (less latency)
731 bool "Locate kernel schedule function in L1 Memory"
734 If enabled, the frequently called kernel schedule is linked
735 into L1 instruction memory. (less latency)
737 config ARITHMETIC_OPS_L1
738 bool "Locate kernel owned arithmetic functions in L1 Memory"
741 If enabled, arithmetic functions are linked
742 into L1 instruction memory. (less latency)
745 bool "Locate access_ok function in L1 Memory"
748 If enabled, the access_ok function is linked
749 into L1 instruction memory. (less latency)
752 bool "Locate memset function in L1 Memory"
755 If enabled, the memset function is linked
756 into L1 instruction memory. (less latency)
759 bool "Locate memcpy function in L1 Memory"
762 If enabled, the memcpy function is linked
763 into L1 instruction memory. (less latency)
765 config SYS_BFIN_SPINLOCK_L1
766 bool "Locate sys_bfin_spinlock function in L1 Memory"
769 If enabled, sys_bfin_spinlock function is linked
770 into L1 instruction memory. (less latency)
772 config IP_CHECKSUM_L1
773 bool "Locate IP Checksum function in L1 Memory"
776 If enabled, the IP Checksum function is linked
777 into L1 instruction memory. (less latency)
779 config CACHELINE_ALIGNED_L1
780 bool "Locate cacheline_aligned data to L1 Data Memory"
785 If enabled, cacheline_aligned data is linked
786 into L1 data memory. (less latency)
788 config SYSCALL_TAB_L1
789 bool "Locate Syscall Table L1 Data Memory"
793 If enabled, the Syscall LUT is linked
794 into L1 data memory. (less latency)
796 config CPLB_SWITCH_TAB_L1
797 bool "Locate CPLB Switch Tables L1 Data Memory"
801 If enabled, the CPLB Switch Tables are linked
802 into L1 data memory. (less latency)
805 bool "Support locating application stack in L1 Scratch Memory"
808 If enabled the application stack can be located in L1
809 scratch memory (less latency).
811 Currently only works with FLAT binaries.
813 config EXCEPTION_L1_SCRATCH
814 bool "Locate exception stack in L1 Scratch Memory"
816 depends on !APP_STACK_L1
818 Whenever an exception occurs, use the L1 Scratch memory for
819 stack storage. You cannot place the stacks of FLAT binaries
820 in L1 when using this option.
822 If you don't use L1 Scratch, then you should say Y here.
824 comment "Speed Optimizations"
825 config BFIN_INS_LOWOVERHEAD
826 bool "ins[bwl] low overhead, higher interrupt latency"
829 Reads on the Blackfin are speculative. In Blackfin terms, this means
830 they can be interrupted at any time (even after they have been issued
831 on to the external bus), and re-issued after the interrupt occurs.
832 For memory - this is not a big deal, since memory does not change if
835 If a FIFO is sitting on the end of the read, it will see two reads,
836 when the core only sees one since the FIFO receives both the read
837 which is cancelled (and not delivered to the core) and the one which
838 is re-issued (which is delivered to the core).
840 To solve this, interrupts are turned off before reads occur to
841 I/O space. This option controls which the overhead/latency of
842 controlling interrupts during this time
843 "n" turns interrupts off every read
844 (higher overhead, but lower interrupt latency)
845 "y" turns interrupts off every loop
846 (low overhead, but longer interrupt latency)
848 default behavior is to leave this set to on (type "Y"). If you are experiencing
849 interrupt latency issues, it is safe and OK to turn this off.
854 prompt "Kernel executes from"
856 Choose the memory type that the kernel will be running in.
861 The kernel will be resident in RAM when running.
866 The kernel will be resident in FLASH/ROM when running.
873 tristate "Enable Blackfin General Purpose Timers API"
876 Enable support for the General Purpose Timers API. If you
879 To compile this driver as a module, choose M here: the module
880 will be called gptimers.ko.
883 prompt "Uncached DMA region"
884 default DMA_UNCACHED_1M
885 config DMA_UNCACHED_4M
886 bool "Enable 4M DMA region"
887 config DMA_UNCACHED_2M
888 bool "Enable 2M DMA region"
889 config DMA_UNCACHED_1M
890 bool "Enable 1M DMA region"
891 config DMA_UNCACHED_NONE
892 bool "Disable DMA region"
896 comment "Cache Support"
901 config BFIN_DCACHE_BANKA
902 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
903 depends on BFIN_DCACHE && !BF531
905 config BFIN_ICACHE_LOCK
906 bool "Enable Instruction Cache Locking"
909 prompt "External memory cache policy"
910 depends on BFIN_DCACHE
911 default BFIN_WB if !SMP
912 default BFIN_WT if SMP
918 Cached data will be written back to SDRAM only when needed.
919 This can give a nice increase in performance, but beware of
920 broken drivers that do not properly invalidate/flush their
923 Write Through Policy:
924 Cached data will always be written back to SDRAM when the
925 cache is updated. This is a completely safe setting, but
926 performance is worse than Write Back.
928 If you are unsure of the options and you want to be safe,
929 then go with Write Through.
935 Cached data will be written back to SDRAM only when needed.
936 This can give a nice increase in performance, but beware of
937 broken drivers that do not properly invalidate/flush their
940 Write Through Policy:
941 Cached data will always be written back to SDRAM when the
942 cache is updated. This is a completely safe setting, but
943 performance is worse than Write Back.
945 If you are unsure of the options and you want to be safe,
946 then go with Write Through.
951 prompt "L2 SRAM cache policy"
952 depends on (BF54x || BF561)
962 config BFIN_L2_NOT_CACHED
968 bool "Enable the memory protection unit (EXPERIMENTAL)"
971 Use the processor's MPU to protect applications from accessing
972 memory they do not own. This comes at a performance penalty
973 and is recommended only for debugging.
975 comment "Asynchronous Memory Configuration"
977 menu "EBIU_AMGCTL Global Control"
983 bool "DMA has priority over core for ext. accesses"
988 bool "Bank 0 16 bit packing enable"
993 bool "Bank 1 16 bit packing enable"
998 bool "Bank 2 16 bit packing enable"
1003 bool "Bank 3 16 bit packing enable"
1007 prompt "Enable Asynchronous Memory Banks"
1011 bool "Disable All Banks"
1014 bool "Enable Bank 0"
1016 config C_AMBEN_B0_B1
1017 bool "Enable Bank 0 & 1"
1019 config C_AMBEN_B0_B1_B2
1020 bool "Enable Bank 0 & 1 & 2"
1023 bool "Enable All Banks"
1027 menu "EBIU_AMBCTL Control"
1029 hex "Bank 0 (AMBCTL0.L)"
1032 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1033 used to control the Asynchronous Memory Bank 0 settings.
1036 hex "Bank 1 (AMBCTL0.H)"
1038 default 0x5558 if BF54x
1040 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1041 used to control the Asynchronous Memory Bank 1 settings.
1044 hex "Bank 2 (AMBCTL1.L)"
1047 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1048 used to control the Asynchronous Memory Bank 2 settings.
1051 hex "Bank 3 (AMBCTL1.H)"
1054 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1055 used to control the Asynchronous Memory Bank 3 settings.
1059 config EBIU_MBSCTLVAL
1060 hex "EBIU Bank Select Control Register"
1065 hex "Flash Memory Mode Control Register"
1070 hex "Flash Memory Bank Control Register"
1075 #############################################################################
1076 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1082 Support for PCI bus.
1084 source "drivers/pci/Kconfig"
1087 bool "Support for hot-pluggable device"
1089 Say Y here if you want to plug devices into your computer while
1090 the system is running, and be able to use them quickly. In many
1091 cases, the devices can likewise be unplugged at any time too.
1093 One well known example of this is PCMCIA- or PC-cards, credit-card
1094 size devices such as network cards, modems or hard drives which are
1095 plugged into slots found on all modern laptop computers. Another
1096 example, used on modern desktops as well as laptops, is USB.
1098 Enable HOTPLUG and build a modular kernel. Get agent software
1099 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1100 Then your kernel will automatically call out to a user mode "policy
1101 agent" (/sbin/hotplug) to load modules and set up software needed
1102 to use devices as you hotplug them.
1104 source "drivers/pcmcia/Kconfig"
1106 source "drivers/pci/hotplug/Kconfig"
1110 menu "Executable file formats"
1112 source "fs/Kconfig.binfmt"
1116 menu "Power management options"
1117 source "kernel/power/Kconfig"
1119 config ARCH_SUSPEND_POSSIBLE
1124 prompt "Standby Power Saving Mode"
1126 default PM_BFIN_SLEEP_DEEPER
1127 config PM_BFIN_SLEEP_DEEPER
1130 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1131 power dissipation by disabling the clock to the processor core (CCLK).
1132 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1133 to 0.85 V to provide the greatest power savings, while preserving the
1135 The PLL and system clock (SCLK) continue to operate at a very low
1136 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1137 the SDRAM is put into Self Refresh Mode. Typically an external event
1138 such as GPIO interrupt or RTC activity wakes up the processor.
1139 Various Peripherals such as UART, SPORT, PPI may not function as
1140 normal during Sleep Deeper, due to the reduced SCLK frequency.
1141 When in the sleep mode, system DMA access to L1 memory is not supported.
1143 If unsure, select "Sleep Deeper".
1145 config PM_BFIN_SLEEP
1148 Sleep Mode (High Power Savings) - The sleep mode reduces power
1149 dissipation by disabling the clock to the processor core (CCLK).
1150 The PLL and system clock (SCLK), however, continue to operate in
1151 this mode. Typically an external event or RTC activity will wake
1152 up the processor. When in the sleep mode, system DMA access to L1
1153 memory is not supported.
1155 If unsure, select "Sleep Deeper".
1158 config PM_WAKEUP_BY_GPIO
1159 bool "Allow Wakeup from Standby by GPIO"
1160 depends on PM && !BF54x
1162 config PM_WAKEUP_GPIO_NUMBER
1165 depends on PM_WAKEUP_BY_GPIO
1169 prompt "GPIO Polarity"
1170 depends on PM_WAKEUP_BY_GPIO
1171 default PM_WAKEUP_GPIO_POLAR_H
1172 config PM_WAKEUP_GPIO_POLAR_H
1174 config PM_WAKEUP_GPIO_POLAR_L
1176 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1178 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1180 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1184 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1187 config PM_BFIN_WAKE_PH6
1188 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1189 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1192 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1194 config PM_BFIN_WAKE_GP
1195 bool "Allow Wake-Up from GPIOs"
1196 depends on PM && BF54x
1199 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1200 (all processors, except ADSP-BF549). This option sets
1201 the general-purpose wake-up enable (GPWE) control bit to enable
1202 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1203 On ADSP-BF549 this option enables the the same functionality on the
1204 /MRXON pin also PH7.
1208 menu "CPU Frequency scaling"
1210 source "drivers/cpufreq/Kconfig"
1212 config BFIN_CPU_FREQ
1215 select CPU_FREQ_TABLE
1219 bool "CPU Voltage scaling"
1220 depends on EXPERIMENTAL
1224 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1225 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1226 manuals. There is a theoretical risk that during VDDINT transitions
1231 source "net/Kconfig"
1233 source "drivers/Kconfig"
1237 source "arch/blackfin/Kconfig.debug"
1239 source "security/Kconfig"
1241 source "crypto/Kconfig"
1243 source "lib/Kconfig"